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-rw-r--r--llvm/utils/TableGen/TableGen.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp
index b0e0385a45c..cf0b0c24f83 100644
--- a/llvm/utils/TableGen/TableGen.cpp
+++ b/llvm/utils/TableGen/TableGen.cpp
@@ -32,6 +32,7 @@ enum ActionType {
GenAsmMatcher,
GenDisassembler,
GenPseudoLowering,
+ GenCompressInst,
GenCallingConv,
GenDAGISel,
GenDFAPacketizer,
@@ -72,6 +73,8 @@ namespace {
"Generate disassembler"),
clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
"Generate pseudo instruction lowering"),
+ clEnumValN(GenCompressInst, "gen-compress-inst-emitter",
+ "Generate RISCV compressed instructions."),
clEnumValN(GenAsmMatcher, "gen-asm-matcher",
"Generate assembly instruction matcher"),
clEnumValN(GenDAGISel, "gen-dag-isel",
@@ -144,6 +147,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
case GenPseudoLowering:
EmitPseudoLowering(Records, OS);
break;
+ case GenCompressInst:
+ EmitCompressInst(Records, OS);
+ break;
case GenDAGISel:
EmitDAGISel(Records, OS);
break;
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