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-rw-r--r--llvm/utils/TableGen/TableGen.cpp6
1 files changed, 6 insertions, 0 deletions
diff --git a/llvm/utils/TableGen/TableGen.cpp b/llvm/utils/TableGen/TableGen.cpp
index 6937f20b441..aa1aefd5e4a 100644
--- a/llvm/utils/TableGen/TableGen.cpp
+++ b/llvm/utils/TableGen/TableGen.cpp
@@ -46,6 +46,7 @@ enum ActionType {
GenAttributes,
GenSearchableTables,
GenGlobalISel,
+ GenX86EVEX2VEXTables,
GenRegisterBank,
};
@@ -96,6 +97,8 @@ namespace {
"Generate generic binary-searchable table"),
clEnumValN(GenGlobalISel, "gen-global-isel",
"Generate GlobalISel selector"),
+ clEnumValN(GenX86EVEX2VEXTables, "gen-x86-EVEX2VEX-tables",
+ "Generate X86 EVEX to VEX compress tables"),
clEnumValN(GenRegisterBank, "gen-register-bank",
"Generate registers bank descriptions")));
@@ -189,6 +192,9 @@ bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
case GenRegisterBank:
EmitRegisterBank(Records, OS);
break;
+ case GenX86EVEX2VEXTables:
+ EmitX86EVEX2VEXTables(Records, OS);
+ break;
}
return false;
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