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-rw-r--r--llvm/utils/TableGen/RISCVCompressInstEmitter.cpp18
1 files changed, 11 insertions, 7 deletions
diff --git a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
index 87c825b3422..f95b3bf9cb4 100644
--- a/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
+++ b/llvm/utils/TableGen/RISCVCompressInstEmitter.cpp
@@ -252,12 +252,14 @@ static bool verifyDagOpCount(CodeGenInstruction &Inst, DagInit *Dag,
// Source instructions are non compressed instructions and don't have tied
// operands.
if (IsSource)
- PrintFatalError("Input operands for Inst '" + Inst.TheDef->getName() +
- "' and input Dag operand count mismatch");
+ PrintFatalError(Inst.TheDef->getLoc(),
+ "Input operands for Inst '" + Inst.TheDef->getName() +
+ "' and input Dag operand count mismatch");
// The Dag can't have more arguments than the Instruction.
if (Dag->getNumArgs() > Inst.Operands.size())
- PrintFatalError("Inst '" + Inst.TheDef->getName() +
- "' and Dag operand count mismatch");
+ PrintFatalError(Inst.TheDef->getLoc(),
+ "Inst '" + Inst.TheDef->getName() +
+ "' and Dag operand count mismatch");
// The Instruction might have tied operands so the Dag might have
// a fewer operand count.
@@ -267,8 +269,9 @@ static bool verifyDagOpCount(CodeGenInstruction &Inst, DagInit *Dag,
--RealCount;
if (Dag->getNumArgs() != RealCount)
- PrintFatalError("Inst '" + Inst.TheDef->getName() +
- "' and Dag operand count mismatch");
+ PrintFatalError(Inst.TheDef->getLoc(),
+ "Inst '" + Inst.TheDef->getName() +
+ "' and Dag operand count mismatch");
return true;
}
@@ -529,7 +532,8 @@ void RISCVCompressInstEmitter::emitCompressInstEmitter(raw_ostream &o,
bool Compress) {
Record *AsmWriter = Target.getAsmWriter();
if (!AsmWriter->getValueAsInt("PassSubtarget"))
- PrintFatalError("'PassSubtarget' is false. SubTargetInfo object is needed "
+ PrintFatalError(AsmWriter->getLoc(),
+ "'PassSubtarget' is false. SubTargetInfo object is needed "
"for target features.\n");
std::string Namespace = Target.getName();
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