1 files changed, 70 insertions, 0 deletions
diff --git a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
index d746bfc756f..f8a7ccd6ebf 100644
--- a/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
+++ b/llvm/unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
@@ -25,6 +25,7 @@ using testing::ElementsAre;
 using testing::HasSubstr;
 using testing::Not;
 using testing::SizeIs;
+using testing::UnorderedElementsAre;
 
 MATCHER(IsInvalid, "") { return !arg.isValid(); }
 MATCHER(IsReg, "") { return arg.isReg(); }
@@ -214,5 +215,74 @@ TEST_F(UopsSnippetGeneratorTest, NoTiedVariables) {
   EXPECT_THAT(II.VariableValues[3], IsInvalid());
 }
 
+class FakeBenchmarkRunner : public BenchmarkRunner {
+public:
+  using BenchmarkRunner::BenchmarkRunner;
+
+  Instruction createInstruction(unsigned Opcode) {
+    return Instruction(MCInstrInfo.get(Opcode), RATC);
+  }
+
+private:
+  InstructionBenchmark::ModeE getMode() const override {
+    return InstructionBenchmark::Unknown;
+  }
+
+  llvm::Expected<SnippetPrototype>
+  generatePrototype(unsigned Opcode) const override {
+    return llvm::make_error<llvm::StringError>("not implemented",
+                                               llvm::inconvertibleErrorCode());
+  }
+
+  std::vector<BenchmarkMeasure>
+  runMeasurements(const ExecutableFunction &EF,
+                  const unsigned NumRepetitions) const override {
+    return {};
+  }
+};
+
+using FakeSnippetGeneratorTest = SnippetGeneratorTest<FakeBenchmarkRunner>;
+
+TEST_F(FakeSnippetGeneratorTest, ComputeRegsToDefAdd16ri) {
+  // ADD16ri:
+  // explicit def 0       : reg RegClass=GR16
+  // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
+  // explicit use 2       : imm
+  // implicit def         : EFLAGS
+  InstructionInstance II(Runner.createInstruction(llvm::X86::ADD16ri));
+  II.getValueFor(II.Instr.Variables[0]) =
+      llvm::MCOperand::createReg(llvm::X86::AX);
+  std::vector<InstructionInstance> Snippet;
+  Snippet.push_back(std::move(II));
+  const auto RegsToDef = Runner.computeRegsToDef(Snippet);
+  EXPECT_THAT(RegsToDef, UnorderedElementsAre(llvm::X86::AX));
+}
+
+TEST_F(FakeSnippetGeneratorTest, ComputeRegsToDefAdd64rr) {
+  // ADD64rr:
+  //  mov64ri rax, 42
+  //  add64rr rax, rax, rbx
+  // -> only rbx needs defining.
+  std::vector<InstructionInstance> Snippet;
+  {
+    InstructionInstance Mov(Runner.createInstruction(llvm::X86::MOV64ri));
+    Mov.getValueFor(Mov.Instr.Variables[0]) =
+        llvm::MCOperand::createReg(llvm::X86::RAX);
+    Mov.getValueFor(Mov.Instr.Variables[1]) = llvm::MCOperand::createImm(42);
+    Snippet.push_back(std::move(Mov));
+  }
+  {
+    InstructionInstance Add(Runner.createInstruction(llvm::X86::ADD64rr));
+    Add.getValueFor(Add.Instr.Variables[0]) =
+        llvm::MCOperand::createReg(llvm::X86::RAX);
+    Add.getValueFor(Add.Instr.Variables[1]) =
+        llvm::MCOperand::createReg(llvm::X86::RBX);
+    Snippet.push_back(std::move(Add));
+  }
+
+  const auto RegsToDef = Runner.computeRegsToDef(Snippet);
+  EXPECT_THAT(RegsToDef, UnorderedElementsAre(llvm::X86::RBX));
+}
+
 } // namespace
 } // namespace exegesis