diff options
Diffstat (limited to 'llvm/unittests/CodeGen/MachineOperandTest.cpp')
-rw-r--r-- | llvm/unittests/CodeGen/MachineOperandTest.cpp | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/llvm/unittests/CodeGen/MachineOperandTest.cpp b/llvm/unittests/CodeGen/MachineOperandTest.cpp index afbf4f4c368..5926b6767ff 100644 --- a/llvm/unittests/CodeGen/MachineOperandTest.cpp +++ b/llvm/unittests/CodeGen/MachineOperandTest.cpp @@ -9,6 +9,7 @@ #include "llvm/ADT/ilist_node.h" #include "llvm/CodeGen/MachineOperand.h" +#include "llvm/Support/raw_ostream.h" #include "gtest/gtest.h" using namespace llvm; @@ -37,4 +38,42 @@ TEST(MachineOperandTest, ChangeToTargetIndexTest) { ASSERT_TRUE(MO.getTargetFlags() == 12); } +TEST(MachineOperandTest, PrintRegisterMask) { + uint32_t Dummy; + MachineOperand MO = MachineOperand::CreateRegMask(&Dummy); + + // Checking some preconditions on the newly created + // MachineOperand. + ASSERT_TRUE(MO.isRegMask()); + ASSERT_TRUE(MO.getRegMask() == &Dummy); + + // Print a MachineOperand containing a RegMask. Here we check that without a + // TRI and IntrinsicInfo we still print a less detailed regmask. + std::string str; + raw_string_ostream OS(str); + MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr); + ASSERT_TRUE(OS.str() == "<regmask ...>"); +} + +TEST(MachineOperandTest, PrintSubReg) { + // Create a MachineOperand with RegNum=1 and SubReg=5. + MachineOperand MO = MachineOperand::CreateReg( + /*Reg=*/1, /*isDef=*/false, /*isImp=*/false, /*isKill=*/false, + /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/false, + /*SubReg=*/5, /*isDebug=*/false, /*isInternalRead=*/false); + + // Checking some preconditions on the newly created + // MachineOperand. + ASSERT_TRUE(MO.isReg()); + ASSERT_TRUE(MO.getReg() == 1); + ASSERT_TRUE(MO.getSubReg() == 5); + + // Print a MachineOperand containing a SubReg. Here we check that without a + // TRI and IntrinsicInfo we can still print the subreg index. + std::string str; + raw_string_ostream OS(str); + MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr); + ASSERT_TRUE(OS.str() == "%physreg1.subreg5"); +} + } // end namespace |