3 files changed, 7 insertions, 5 deletions
diff --git a/llvm/tools/llvm-mca/Backend.cpp b/llvm/tools/llvm-mca/Backend.cpp
index 96668294498..46c7a735e9e 100644
--- a/llvm/tools/llvm-mca/Backend.cpp
+++ b/llvm/tools/llvm-mca/Backend.cpp
@@ -36,7 +36,7 @@ void Backend::runCycle(unsigned Cycle) {
     std::unique_ptr<Instruction> NewIS(
         IB->createInstruction(STI, IR.first, *IR.second));
     const InstrDesc &Desc = NewIS->getDesc();
-    if (!DU->isAvailable(Desc.NumMicroOps) || !DU->canDispatch(Desc))
+    if (!DU->isAvailable(Desc.NumMicroOps) || !DU->canDispatch(*NewIS))
       break;
 
     Instruction *IS = NewIS.get();
diff --git a/llvm/tools/llvm-mca/Dispatch.cpp b/llvm/tools/llvm-mca/Dispatch.cpp
index 33b5f4926c9..50b118b310c 100644
--- a/llvm/tools/llvm-mca/Dispatch.cpp
+++ b/llvm/tools/llvm-mca/Dispatch.cpp
@@ -199,7 +199,8 @@ void RetireControlUnit::dump() const {
 }
 #endif
 
-bool DispatchUnit::checkRAT(const InstrDesc &Desc) {
+bool DispatchUnit::checkRAT(const Instruction &Instr) {
+  const InstrDesc &Desc = Instr.getDesc();
   unsigned NumWrites = Desc.Writes.size();
   if (RAT->isAvailable(NumWrites))
     return true;
diff --git a/llvm/tools/llvm-mca/Dispatch.h b/llvm/tools/llvm-mca/Dispatch.h
index 66ac2f7e64a..b342976db27 100644
--- a/llvm/tools/llvm-mca/Dispatch.h
+++ b/llvm/tools/llvm-mca/Dispatch.h
@@ -233,7 +233,7 @@ class DispatchUnit {
   // stored into a vector `DispatchStall` which is always of size DS_LAST.
   std::vector<unsigned> DispatchStalls;
 
-  bool checkRAT(const InstrDesc &Desc);
+  bool checkRAT(const Instruction &Desc);
   bool checkRCU(const InstrDesc &Desc);
   bool checkScheduler(const InstrDesc &Desc);
 
@@ -260,9 +260,10 @@ public:
 
   bool isRCUEmpty() const { return RCU->isEmpty(); }
 
-  bool canDispatch(const InstrDesc &Desc) {
+  bool canDispatch(const Instruction &Inst) {
+    const InstrDesc &Desc = Inst.getDesc();
     assert(isAvailable(Desc.NumMicroOps));
-    return checkRCU(Desc) && checkRAT(Desc) && checkScheduler(Desc);
+    return checkRCU(Desc) && checkRAT(Inst) && checkScheduler(Desc);
   }
 
   unsigned dispatch(unsigned IID, Instruction *NewInst,