diff options
Diffstat (limited to 'llvm/tools/llvm-mca')
| -rw-r--r-- | llvm/tools/llvm-mca/Backend.cpp | 5 | ||||
| -rw-r--r-- | llvm/tools/llvm-mca/Dispatch.cpp | 1 | ||||
| -rw-r--r-- | llvm/tools/llvm-mca/Scheduler.cpp | 1 |
3 files changed, 2 insertions, 5 deletions
diff --git a/llvm/tools/llvm-mca/Backend.cpp b/llvm/tools/llvm-mca/Backend.cpp index 62e239524dd..fab725aecf7 100644 --- a/llvm/tools/llvm-mca/Backend.cpp +++ b/llvm/tools/llvm-mca/Backend.cpp @@ -43,11 +43,6 @@ void Backend::runCycle(unsigned Cycle) { Instructions[IR.first] = std::unique_ptr<Instruction>(NewIS); NewIS->setRCUTokenID(DU->dispatch(IR.first, NewIS)); - // If this is a zero latency instruction, then we don't need to dispatch - // it. Instead, we can mark it as executed. - if (NewIS->isZeroLatency()) - notifyInstructionExecuted(IR.first); - // Check if we have dispatched all the instructions. SM.updateNext(); if (!SM.hasNext()) diff --git a/llvm/tools/llvm-mca/Dispatch.cpp b/llvm/tools/llvm-mca/Dispatch.cpp index c5c560ca2f3..8a08339265a 100644 --- a/llvm/tools/llvm-mca/Dispatch.cpp +++ b/llvm/tools/llvm-mca/Dispatch.cpp @@ -242,6 +242,7 @@ unsigned DispatchUnit::dispatch(unsigned IID, Instruction *NewInst) { // Reserve slots in the RCU. unsigned RCUTokenID = RCU->reserveSlot(IID, NumMicroOps); + NewInst->setRCUTokenID(RCUTokenID); Owner->notifyInstructionDispatched(IID); SC->scheduleInstruction(IID, NewInst); diff --git a/llvm/tools/llvm-mca/Scheduler.cpp b/llvm/tools/llvm-mca/Scheduler.cpp index 8608a06b8df..6c0c44bd4d7 100644 --- a/llvm/tools/llvm-mca/Scheduler.cpp +++ b/llvm/tools/llvm-mca/Scheduler.cpp @@ -264,6 +264,7 @@ Instruction *Scheduler::scheduleInstruction(unsigned Idx, Instruction *MCIS) { // eliminated at register renaming stage, since we know in advance that those // clear their output register. if (MCIS->isZeroLatency()) { + notifyInstructionReady(Idx); MCIS->forceExecuted(); notifyInstructionIssued(Idx, {}); notifyInstructionExecuted(Idx); |
