3 files changed, 24 insertions, 26 deletions

diff --git a/llvm/tools/llvm-mca/include/Instruction.h b/llvm/tools/llvm-mca/include/Instruction.h
index 9d1c91ad441..bbb40c42576 100644
--- a/llvm/tools/llvm-mca/include/Instruction.h
+++ b/llvm/tools/llvm-mca/include/Instruction.h
@@ -88,7 +88,7 @@ class ReadState;
 /// register write. It also tracks how many cycles are left before the write
 /// back stage.
 class WriteState {
-  const WriteDescriptor &WD;
+  const WriteDescriptor *WD;
   // On instruction issue, this field is set equal to the write latency.
   // Before instruction issue, this field defaults to -512, a special
   // value that represents an "unknown" number of cycles.
@@ -133,14 +133,17 @@ class WriteState {
 public:
   WriteState(const WriteDescriptor &Desc, unsigned RegID,
              bool clearsSuperRegs = false, bool writesZero = false)
-      : WD(Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID),
+      : WD(&Desc), CyclesLeft(UNKNOWN_CYCLES), RegisterID(RegID),
         ClearsSuperRegs(clearsSuperRegs), WritesZero(writesZero),
         IsEliminated(false), DependentWrite(nullptr), NumWriteUsers(0U) {}
 
+  WriteState(const WriteState &Other) = default;
+  WriteState &operator=(const WriteState &Other) = default;
+
   int getCyclesLeft() const { return CyclesLeft; }
-  unsigned getWriteResourceID() const { return WD.SClassOrWriteResourceID; }
+  unsigned getWriteResourceID() const { return WD->SClassOrWriteResourceID; }
   unsigned getRegisterID() const { return RegisterID; }
-  unsigned getLatency() const { return WD.Latency; }
+  unsigned getLatency() const { return WD->Latency; }
 
   void addUser(ReadState *Use, int ReadAdvance);
 
@@ -178,7 +181,7 @@ public:
 /// A read may be dependent on more than one write. This occurs when some
 /// writes only partially update the register associated to this read.
 class ReadState {
-  const ReadDescriptor &RD;
+  const ReadDescriptor *RD;
   // Physical register identified associated to this read.
   unsigned RegisterID;
   // Number of writes that contribute to the definition of RegisterID.
@@ -202,16 +205,16 @@ class ReadState {
 
 public:
   ReadState(const ReadDescriptor &Desc, unsigned RegID)
-      : RD(Desc), RegisterID(RegID), DependentWrites(0),
+      : RD(&Desc), RegisterID(RegID), DependentWrites(0),
         CyclesLeft(UNKNOWN_CYCLES), TotalCycles(0), IsReady(true),
         IndependentFromDef(false) {}
 
-  const ReadDescriptor &getDescriptor() const { return RD; }
-  unsigned getSchedClass() const { return RD.SchedClassID; }
+  const ReadDescriptor &getDescriptor() const { return *RD; }
+  unsigned getSchedClass() const { return RD->SchedClassID; }
   unsigned getRegisterID() const { return RegisterID; }
 
   bool isReady() const { return IsReady; }
-  bool isImplicitRead() const { return RD.isImplicitRead(); }
+  bool isImplicitRead() const { return RD->isImplicitRead(); }
 
   bool isIndependentFromDef() const { return IndependentFromDef; }
   void setIndependentFromDef() { IndependentFromDef = true; }
@@ -387,8 +390,6 @@ public:
   Instruction(const InstrDesc &D)
       : InstructionBase(D), Stage(IS_INVALID), CyclesLeft(UNKNOWN_CYCLES),
         RCUTokenID(0) {}
-  Instruction(const Instruction &Other) = delete;
-  Instruction &operator=(const Instruction &Other) = delete;
 
   unsigned getRCUTokenID() const { return RCUTokenID; }
   int getCyclesLeft() const { return CyclesLeft; }
diff --git a/llvm/tools/llvm-mca/include/SourceMgr.h b/llvm/tools/llvm-mca/include/SourceMgr.h
index 12713588246..54b1a2c31ce 100644
--- a/llvm/tools/llvm-mca/include/SourceMgr.h
+++ b/llvm/tools/llvm-mca/include/SourceMgr.h
@@ -17,35 +17,35 @@
 #define LLVM_TOOLS_LLVM_MCA_SOURCEMGR_H
 
 #include "llvm/ADT/ArrayRef.h"
-#include "llvm/MC/MCInst.h"
-#include <vector>
 
 namespace mca {
 
-typedef std::pair<unsigned, const llvm::MCInst &> SourceRef;
+class Instruction;
+
+typedef std::pair<unsigned, const Instruction &> SourceRef;
 
 class SourceMgr {
-  llvm::ArrayRef<llvm::MCInst> Sequence;
+  using UniqueInst = std::unique_ptr<Instruction>;
+  llvm::ArrayRef<UniqueInst> Sequence;
   unsigned Current;
   const unsigned Iterations;
   static const unsigned DefaultIterations = 100;
 
 public:
-  SourceMgr(llvm::ArrayRef<llvm::MCInst> MCInstSequence, unsigned NumIterations)
-      : Sequence(MCInstSequence), Current(0),
-        Iterations(NumIterations ? NumIterations : DefaultIterations) {}
+  SourceMgr(llvm::ArrayRef<UniqueInst> S, unsigned Iter)
+      : Sequence(S), Current(0), Iterations(Iter ? Iter : DefaultIterations) {}
 
   unsigned getNumIterations() const { return Iterations; }
   unsigned size() const { return Sequence.size(); }
   bool hasNext() const { return Current < (Iterations * Sequence.size()); }
   void updateNext() { ++Current; }
 
-  const SourceRef peekNext() const {
+  SourceRef peekNext() const {
     assert(hasNext() && "Already at end of sequence!");
-    return SourceRef(Current, Sequence[Current % Sequence.size()]);
+    return SourceRef(Current, *Sequence[Current % Sequence.size()]);
   }
 
-  using const_iterator = llvm::ArrayRef<llvm::MCInst>::const_iterator;
+  using const_iterator = llvm::ArrayRef<UniqueInst>::const_iterator;
   const_iterator begin() const { return Sequence.begin(); }
   const_iterator end() const { return Sequence.end(); }
 };
diff --git a/llvm/tools/llvm-mca/include/Stages/FetchStage.h b/llvm/tools/llvm-mca/include/Stages/FetchStage.h
index 45e30e17b4d..a7aba2276d9 100644
--- a/llvm/tools/llvm-mca/include/Stages/FetchStage.h
+++ b/llvm/tools/llvm-mca/include/Stages/FetchStage.h
@@ -16,7 +16,6 @@
 #ifndef LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
 #define LLVM_TOOLS_LLVM_MCA_FETCH_STAGE_H
 
-#include "InstrBuilder.h"
 #include "SourceMgr.h"
 #include "Stages/Stage.h"
 #include <map>
@@ -27,18 +26,16 @@ class FetchStage final : public Stage {
   InstRef CurrentInstruction;
   using InstMap = std::map<unsigned, std::unique_ptr<Instruction>>;
   InstMap Instructions;
-  InstrBuilder &IB;
   SourceMgr &SM;
 
   // Updates the program counter, and sets 'CurrentInstruction'.
-  llvm::Error getNextInstruction();
+  void getNextInstruction();
 
   FetchStage(const FetchStage &Other) = delete;
   FetchStage &operator=(const FetchStage &Other) = delete;
 
 public:
-  FetchStage(InstrBuilder &IB, SourceMgr &SM)
-      : CurrentInstruction(), IB(IB), SM(SM) {}
+  FetchStage(SourceMgr &SM) : CurrentInstruction(), SM(SM) {}
 
   bool isAvailable(const InstRef &IR) const override;
   bool hasWorkToComplete() const override;