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-rw-r--r--llvm/tools/llvm-mca/Scheduler.cpp13
1 files changed, 3 insertions, 10 deletions
diff --git a/llvm/tools/llvm-mca/Scheduler.cpp b/llvm/tools/llvm-mca/Scheduler.cpp
index 70b073b46e7..08ddf6ebe7d 100644
--- a/llvm/tools/llvm-mca/Scheduler.cpp
+++ b/llvm/tools/llvm-mca/Scheduler.cpp
@@ -260,16 +260,9 @@ void Scheduler::scheduleInstruction(unsigned Idx, Instruction &MCIS) {
notifyReservedBuffers(Desc.Buffers);
}
- bool MayLoad = Desc.MayLoad;
- bool MayStore = Desc.MayStore;
- if (MayLoad || MayStore)
- LSU->reserve(Idx, MayLoad, MayStore, Desc.HasSideEffects);
-
- bool IsReady = MCIS.isReady();
- if (IsReady && (MayLoad || MayStore))
- IsReady &= LSU->isReady(Idx);
-
- if (!IsReady) {
+ // If necessary, reserve queue entries in the load-store unit (LSU).
+ bool Reserved = LSU->reserve(Idx, Desc);
+ if (!MCIS.isReady() || (Reserved && !LSU->isReady(Idx))) {
DEBUG(dbgs() << "[SCHEDULER] Adding " << Idx << " to the Wait Queue\n");
WaitQueue[Idx] = &MCIS;
return;
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