1 files changed, 13 insertions, 17 deletions

diff --git a/llvm/tools/llvm-mca/InstrBuilder.cpp b/llvm/tools/llvm-mca/InstrBuilder.cpp
index 1bf2b36be52..82b5f16d246 100644
--- a/llvm/tools/llvm-mca/InstrBuilder.cpp
+++ b/llvm/tools/llvm-mca/InstrBuilder.cpp
@@ -112,12 +112,12 @@ initializeUsedResources(InstrDesc &ID, const MCSchedClassDesc &SCDesc,
     }
   }
 
-  DEBUG(
+  DEBUG({
     for (const std::pair<uint64_t, ResourceUsage> &R : ID.Resources)
       dbgs() << "\t\tMask=" << R.first << ", cy=" << R.second.size() << '\n';
     for (const uint64_t R : ID.Buffers)
       dbgs() << "\t\tBuffer Mask=" << R << '\n';
-  );
+  });
 }
 
 static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc,
@@ -260,11 +260,10 @@ static void populateWrites(InstrDesc &ID, const MCInst &MCI,
     }
     Write.FullyUpdatesSuperRegs = FullyUpdatesSuperRegisters;
     Write.IsOptionalDef = false;
-    DEBUG(
-      dbgs() << "\t\tOpIdx=" << Write.OpIndex
-             << ", Latency=" << Write.Latency << ", WriteResourceID="
-             << Write.SClassOrWriteResourceID << '\n';
-    );
+    DEBUG({
+      dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", Latency=" << Write.Latency
+             << ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
+    });
     CurrentDef++;
   }
 
@@ -371,7 +370,7 @@ void InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
       *SM.getSchedClassDesc(MCDesc.getSchedClass());
 
   // Create a new empty descriptor.
-  InstrDesc *ID = new InstrDesc();
+  std::unique_ptr<InstrDesc> ID = llvm::make_unique<InstrDesc>();
 
   if (SCDesc.isVariant()) {
     errs() << "warning: don't know how to model variant opcodes.\n"
@@ -406,7 +405,7 @@ void InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
   DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n');
 
   // Now add the new descriptor.
-  Descriptors[Opcode] = std::unique_ptr<const InstrDesc>(ID);
+  Descriptors[Opcode] = std::move(ID);
 }
 
 const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
@@ -416,9 +415,10 @@ const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
   return *Descriptors[MCI.getOpcode()].get();
 }
 
-Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
+std::unique_ptr<Instruction>
+InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
   const InstrDesc &D = getOrCreateInstrDesc(MCI);
-  Instruction *NewIS = new Instruction(D);
+  std::unique_ptr<Instruction> NewIS = llvm::make_unique<Instruction>(D);
 
   // Populate Reads first.
   for (const ReadDescriptor &RD : D.Reads) {
@@ -441,8 +441,7 @@ Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
 
     // Okay, this is a register operand. Create a ReadState for it.
     assert(RegID > 0 && "Invalid register ID found!");
-    ReadState *NewRDS = new ReadState(RD, RegID);
-    NewIS->getUses().emplace_back(std::unique_ptr<ReadState>(NewRDS));
+    NewIS->getUses().emplace_back(llvm::make_unique<ReadState>(RD, RegID));
   }
 
   // Now populate writes.
@@ -455,12 +454,9 @@ Instruction *InstrBuilder::createInstruction(unsigned Idx, const MCInst &MCI) {
     if (WD.IsOptionalDef && !RegID)
       continue;
 
-    WriteState *NewWS = new WriteState(WD);
-    NewIS->getDefs().emplace_back(std::unique_ptr<WriteState>(NewWS));
-    NewWS->setRegisterID(RegID);
+    NewIS->getDefs().emplace_back(llvm::make_unique<WriteState>(WD, RegID));
   }
 
   return NewIS;
 }
-
 } // namespace mca