diff options
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll | 5226 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/dpp_combine.ll | 53 |
2 files changed, 5008 insertions, 271 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll index 84a1172d1c4..de89224c1aa 100644 --- a/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll +++ b/llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX7LESS %s -; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,DPPCOMB %s -; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,DPPCOMB %s -; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN64,GFX8MORE,GFX8MORE64,GFX1064 %s -; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GCN32,GFX8MORE,GFX8MORE32,GFX1032 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX7LESS %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX8 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1064 %s +; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -mattr=-flat-for-global -amdgpu-atomic-optimizations=true -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX1032 %s declare i32 @llvm.amdgcn.workitem.id.x() @@ -12,53 +12,596 @@ declare i32 @llvm.amdgcn.workitem.id.x() ; Show that what the atomic optimization pass will do for local pointers. -; GCN-LABEL: add_i32_constant: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] -; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} -; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]], 5 -; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @add_i32_constant(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: add_i32_constant: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr1 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX7LESS-NEXT: ; mask branch BB0_2 +; GFX7LESS-NEXT: s_cbranch_execz BB0_2 +; GFX7LESS-NEXT: BB0_1: +; GFX7LESS-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: v_mul_u32_u24_e64 v2, s4, 5 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB0_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: add_i32_constant: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr1 +; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: ; mask branch BB0_2 +; GFX8-NEXT: s_cbranch_execz BB0_2 +; GFX8-NEXT: BB0_1: +; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX8-NEXT: v_mul_u32_u24_e64 v1, s4, 5 +; GFX8-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_add_rtn_u32 v1, v2, v1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB0_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX8-NEXT: v_readfirstlane_b32 s2, v1 +; GFX8-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: add_i32_constant: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: ; mask branch BB0_2 +; GFX9-NEXT: s_cbranch_execz BB0_2 +; GFX9-NEXT: BB0_1: +; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX9-NEXT: v_mul_u32_u24_e64 v1, s4, 5 +; GFX9-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_add_rtn_u32 v1, v2, v1 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB0_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: v_readfirstlane_b32 s2, v1 +; GFX9-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: add_i32_constant: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: ; implicit-def: $vgpr1 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB0_2 +; GFX1064-NEXT: s_cbranch_execz BB0_2 +; GFX1064-NEXT: BB0_1: +; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1064-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo +; GFX1064-NEXT: v_mul_u32_u24_e64 v1, s2, 5 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_add_rtn_u32 v1, v2, v1 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB0_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: add_i32_constant: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s3, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: ; implicit-def: $vgpr1 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s3, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX1032-NEXT: ; mask branch BB0_2 +; GFX1032-NEXT: s_cbranch_execz BB0_2 +; GFX1032-NEXT: BB0_1: +; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1032-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo +; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s3, 5 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_add_rtn_u32 v1, v2, v1 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB0_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX1032-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: v_mad_u32_u24 v0, v0, 5, s2 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 5 acq_rel store i32 %old, i32 addrspace(1)* %out ret void } -; GCN-LABEL: add_i32_uniform: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] -; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} -; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]] -; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] -; GCN: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @add_i32_uniform(i32 addrspace(1)* %out, i32 %additive) { +; +; +; GFX7LESS-LABEL: add_i32_uniform: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GFX7LESS-NEXT: s_load_dword s2, s[0:1], 0xb +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr1 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX7LESS-NEXT: ; mask branch BB1_2 +; GFX7LESS-NEXT: s_cbranch_execz BB1_2 +; GFX7LESS-NEXT: BB1_1: +; GFX7LESS-NEXT: s_bcnt1_i32_b64 s3, s[6:7] +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: s_mul_i32 s3, s2, s3 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s3 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB1_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 +; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s0, v0 +; GFX7LESS-NEXT: s_mov_b32 s6, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: add_i32_uniform: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX8-NEXT: s_load_dword s0, s[0:1], 0x2c +; GFX8-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr1 +; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: ; mask branch BB1_2 +; GFX8-NEXT: s_cbranch_execz BB1_2 +; GFX8-NEXT: BB1_1: +; GFX8-NEXT: s_bcnt1_i32_b64 s1, s[6:7] +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_mul_i32 s1, s0, s1 +; GFX8-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB1_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mul_lo_u32 v0, s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v1 +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 +; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: add_i32_uniform: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX9-NEXT: s_load_dword s0, s[0:1], 0x2c +; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: ; mask branch BB1_2 +; GFX9-NEXT: s_cbranch_execz BB1_2 +; GFX9-NEXT: BB1_1: +; GFX9-NEXT: s_bcnt1_i32_b64 s1, s[6:7] +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_mul_i32 s1, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB1_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mul_lo_u32 v0, s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v1 +; GFX9-NEXT: s_mov_b32 s7, 0xf000 +; GFX9-NEXT: s_mov_b32 s6, -1 +; GFX9-NEXT: v_add_u32_e32 v0, s0, v0 +; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: add_i32_uniform: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: s_load_dword s0, s[0:1], 0x2c +; GFX1064-NEXT: ; implicit-def: $vgpr1 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GFX1064-NEXT: ; mask branch BB1_2 +; GFX1064-NEXT: s_cbranch_execz BB1_2 +; GFX1064-NEXT: BB1_1: +; GFX1064-NEXT: s_bcnt1_i32_b64 s1, s[2:3] +; GFX1064-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: s_mul_i32 s1, s0, s1 +; GFX1064-NEXT: v_mov_b32_e32 v2, s1 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB1_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[6:7] +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: v_mul_lo_u32 v0, s0, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s0, v1 +; GFX1064-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1064-NEXT: s_mov_b32 s6, -1 +; GFX1064-NEXT: v_add_nc_u32_e32 v0, s0, v0 +; GFX1064-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: add_i32_uniform: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX1032-NEXT: s_load_dword s0, s[0:1], 0x2c +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: ; implicit-def: $vgpr1 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX1032-NEXT: ; mask branch BB1_2 +; GFX1032-NEXT: s_cbranch_execz BB1_2 +; GFX1032-NEXT: BB1_1: +; GFX1032-NEXT: s_bcnt1_i32_b32 s2, s2 +; GFX1032-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: s_mul_i32 s2, s0, s2 +; GFX1032-NEXT: v_mov_b32_e32 v2, s2 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_add_rtn_u32 v1, v1, v2 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB1_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: v_mul_lo_u32 v0, s0, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s0, v1 +; GFX1032-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1032-NEXT: s_mov_b32 s6, -1 +; GFX1032-NEXT: v_add_nc_u32_e32 v0, s0, v0 +; GFX1032-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 %additive acq_rel store i32 %old, i32 addrspace(1)* %out ret void } -; GCN-LABEL: add_i32_varying: ; GFX7LESS-NOT: v_mbcnt_lo_u32_b32 ; GFX7LESS-NOT: v_mbcnt_hi_u32_b32 ; GFX7LESS-NOT: s_bcnt1_i32_b64 -; GFX7LESS: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; DPPCOMB: v_add_u32_dpp ; DPPCOMB: v_add_u32_dpp ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 -; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 ; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GFX8MORE: ds_add_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @add_i32_varying(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: add_i32_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_add_rtn_u32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: add_i32_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, 0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB2_2 +; GFX8-NEXT: s_cbranch_execz BB2_2 +; GFX8-NEXT: BB2_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_add_rtn_u32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB2_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: add_i32_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB2_2 +; GFX9-NEXT: s_cbranch_execz BB2_2 +; GFX9-NEXT: BB2_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_add_rtn_u32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB2_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_add_u32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: add_i32_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, 0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB2_2 +; GFX1064-NEXT: s_cbranch_execz BB2_2 +; GFX1064-NEXT: BB2_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_add_rtn_u32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB2_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_add_nc_u32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: add_i32_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB2_2 +; GFX1032-NEXT: s_cbranch_execz BB2_2 +; GFX1032-NEXT: BB2_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_add_rtn_u32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB2_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_add_nc_u32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -67,64 +610,241 @@ entry: } define amdgpu_kernel void @add_i32_varying_gfx1032(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: add_i32_varying_gfx1032: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_add_rtn_u32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: add_i32_varying_gfx1032: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, 0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB3_2 +; GFX8-NEXT: s_cbranch_execz BB3_2 +; GFX8-NEXT: BB3_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_add_rtn_u32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB3_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: add_i32_varying_gfx1032: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB3_2 +; GFX9-NEXT: s_cbranch_execz BB3_2 +; GFX9-NEXT: BB3_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_add_rtn_u32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB3_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_add_u32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: add_i32_varying_gfx1032: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, 0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB3_2 +; GFX1064-NEXT: s_cbranch_execz BB3_2 +; GFX1064-NEXT: BB3_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_add_rtn_u32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB3_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_add_nc_u32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; ; GFX1032-LABEL: add_i32_varying_gfx1032: -; GFX1032: v_mov_b32_e32 v2, v0 -; GFX1032: s_or_saveexec_b32 s2, -1 -; GFX1032: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX1032: v_mov_b32_e32 v1, 0 -; GFX1032: s_mov_b32 exec_lo, s2 -; GFX1032: v_cmp_ne_u32_e64 s2, 1, 0 -; GFX1032: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 -; GFX1032: s_not_b32 exec_lo, exec_lo -; GFX1032: v_mov_b32_e32 v2, 0 -; GFX1032: s_not_b32 exec_lo, exec_lo -; GFX1032: s_or_saveexec_b32 s4, -1 -; GFX1032: v_mov_b32_e32 v3, v1 -; GFX1032: v_mov_b32_e32 v4, v1 -; GFX1032: s_mov_b32 s2, -1 -; GFX1032: v_mov_b32_dpp v3, v2 row_shr:1 row_mask:0xf bank_mask:0xf -; GFX1032: v_add_nc_u32_e32 v2, v2, v3 -; GFX1032: v_mov_b32_e32 v3, v1 -; GFX1032: v_mov_b32_dpp v3, v2 row_shr:2 row_mask:0xf bank_mask:0xf -; GFX1032: v_add_nc_u32_e32 v2, v2, v3 -; GFX1032: v_mov_b32_e32 v3, v1 -; GFX1032: v_mov_b32_dpp v3, v2 row_shr:4 row_mask:0xf bank_mask:0xf -; GFX1032: v_add_nc_u32_e32 v2, v2, v3 -; GFX1032: v_mov_b32_e32 v3, v1 -; GFX1032: v_mov_b32_dpp v3, v2 row_shr:8 row_mask:0xf bank_mask:0xf -; GFX1032: v_add_nc_u32_e32 v2, v2, v3 -; GFX1032: v_mov_b32_e32 v3, v2 -; GFX1032: v_permlanex16_b32 v3, v3, -1, -1 -; GFX1032: v_mov_b32_dpp v4, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf -; GFX1032: v_add_nc_u32_e32 v2, v2, v4 -; GFX1032: v_readlane_b32 s3, v2, 31 -; GFX1032: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf -; GFX1032: v_readlane_b32 s5, v2, 15 -; GFX1032: v_writelane_b32 v1, s5, 16 -; GFX1032: s_mov_b32 exec_lo, s4 -; GFX1032: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX1032: s_and_saveexec_b32 s4, vcc_lo -; GFX1032: s_cbranch_execz BB3_2 -; GFX1032: BB3_1: -; GFX1032: v_mov_b32_e32 v0, local_var32@abs32@lo -; GFX1032: v_mov_b32_e32 v5, s3 -; GFX1032: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1032: s_waitcnt_vscnt null, 0x0 -; GFX1032: ds_add_rtn_u32 v0, v0, v5 -; GFX1032: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1032: buffer_gl0_inv -; GFX1032: buffer_gl1_inv -; GFX1032: BB3_2: -; GFX1032: v_nop -; GFX1032: s_or_b32 exec_lo, exec_lo, s4 -; GFX1032: v_readfirstlane_b32 s3, v0 -; GFX1032: v_mov_b32_e32 v0, v1 -; GFX1032: v_add_nc_u32_e32 v0, s3, v0 -; GFX1032: s_mov_b32 s3, 0x31016000 -; GFX1032: s_nop 1 -; GFX1032: s_waitcnt lgkmcnt(0) -; GFX1032: buffer_store_dword v0, off, s[0:3], 0 -; GFX1032: s_endpgm +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB3_2 +; GFX1032-NEXT: s_cbranch_execz BB3_2 +; GFX1032-NEXT: BB3_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_add_rtn_u32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB3_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_add_nc_u32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -133,74 +853,241 @@ entry: } define amdgpu_kernel void @add_i32_varying_gfx1064(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: add_i32_varying_gfx1064: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_add_rtn_u32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: add_i32_varying_gfx1064: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, 0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB4_2 +; GFX8-NEXT: s_cbranch_execz BB4_2 +; GFX8-NEXT: BB4_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_add_rtn_u32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB4_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: add_i32_varying_gfx1064: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB4_2 +; GFX9-NEXT: s_cbranch_execz BB4_2 +; GFX9-NEXT: BB4_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_add_rtn_u32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB4_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_add_u32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; ; GFX1064-LABEL: add_i32_varying_gfx1064: -; GFX1064: v_mov_b32_e32 v2, v0 -; GFX1064: s_or_saveexec_b64 s[2:3], -1 -; GFX1064: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX1064: v_mov_b32_e32 v1, 0 -; GFX1064: s_mov_b64 exec, s[2:3] -; GFX1064: v_cmp_ne_u32_e64 s[2:3], 1, 0 -; GFX1064: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 -; GFX1064: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 -; GFX1064: s_not_b64 exec, exec -; GFX1064: v_mov_b32_e32 v2, 0 -; GFX1064: s_not_b64 exec, exec -; GFX1064: s_or_saveexec_b64 s[4:5], -1 -; GFX1064: v_mov_b32_e32 v3, v1 -; GFX1064: v_mov_b32_e32 v4, v1 -; GFX1064: s_mov_b32 s2, -1 -; GFX1064: v_mov_b32_dpp v3, v2 row_shr:1 row_mask:0xf bank_mask:0xf -; GFX1064: v_add_nc_u32_e32 v2, v2, v3 -; GFX1064: v_mov_b32_e32 v3, v1 -; GFX1064: v_mov_b32_dpp v3, v2 row_shr:2 row_mask:0xf bank_mask:0xf -; GFX1064: v_add_nc_u32_e32 v2, v2, v3 -; GFX1064: v_mov_b32_e32 v3, v1 -; GFX1064: v_mov_b32_dpp v3, v2 row_shr:4 row_mask:0xf bank_mask:0xf -; GFX1064: v_add_nc_u32_e32 v2, v2, v3 -; GFX1064: v_mov_b32_e32 v3, v1 -; GFX1064: v_mov_b32_dpp v3, v2 row_shr:8 row_mask:0xf bank_mask:0xf -; GFX1064: v_add_nc_u32_e32 v2, v2, v3 -; GFX1064: v_mov_b32_e32 v3, v2 -; GFX1064: v_permlanex16_b32 v3, v3, -1, -1 -; GFX1064: v_mov_b32_dpp v4, v3 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf -; GFX1064: v_add_nc_u32_e32 v2, v2, v4 -; GFX1064: v_mov_b32_e32 v4, v1 -; GFX1064: v_readlane_b32 s3, v2, 31 -; GFX1064: v_mov_b32_e32 v3, s3 -; GFX1064: v_mov_b32_dpp v4, v3 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf -; GFX1064: v_add_nc_u32_e32 v2, v2, v4 -; GFX1064: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf -; GFX1064: v_readlane_b32 s3, v2, 15 -; GFX1064: v_readlane_b32 s6, v2, 31 -; GFX1064: v_writelane_b32 v1, s3, 16 -; GFX1064: v_readlane_b32 s3, v2, 63 -; GFX1064: v_writelane_b32 v1, s6, 32 -; GFX1064: v_readlane_b32 s6, v2, 47 -; GFX1064: v_writelane_b32 v1, s6, 48 -; GFX1064: s_mov_b64 exec, s[4:5] -; GFX1064: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX1064: s_and_saveexec_b64 s[4:5], vcc -; GFX1064: s_cbranch_execz BB4_2 -; GFX1064: BB4_1: -; GFX1064: v_mov_b32_e32 v0, local_var32@abs32@lo -; GFX1064: v_mov_b32_e32 v5, s3 -; GFX1064: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1064: s_waitcnt_vscnt null, 0x0 -; GFX1064: ds_add_rtn_u32 v0, v0, v5 -; GFX1064: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX1064: buffer_gl0_inv -; GFX1064: buffer_gl1_inv -; GFX1064: BB4_2: -; GFX1064: v_nop -; GFX1064: s_or_b64 exec, exec, s[4:5] -; GFX1064: v_readfirstlane_b32 s3, v0 -; GFX1064: v_mov_b32_e32 v0, v1 -; GFX1064: v_add_nc_u32_e32 v0, s3, v0 -; GFX1064: s_mov_b32 s3, 0x31016000 -; GFX1064: s_nop 1 -; GFX1064: s_waitcnt lgkmcnt(0) -; GFX1064: buffer_store_dword v0, off, s[0:3], 0 -; GFX1064: s_endpgm +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, 0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB4_2 +; GFX1064-NEXT: s_cbranch_execz BB4_2 +; GFX1064-NEXT: BB4_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_add_rtn_u32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB4_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_add_nc_u32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: add_i32_varying_gfx1064: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB4_2 +; GFX1032-NEXT: s_cbranch_execz BB4_2 +; GFX1032-NEXT: BB4_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_add_rtn_u32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB4_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_add_nc_u32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw add i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -208,46 +1095,495 @@ entry: ret void } -; GCN-LABEL: add_i64_constant: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] -; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} -; GCN: v_mul_hi_u32_u24{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], s[[popcount]], 5 -; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], s[[popcount]], 5 -; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} define amdgpu_kernel void @add_i64_constant(i64 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: add_i64_constant: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX7LESS-NEXT: ; mask branch BB5_2 +; GFX7LESS-NEXT: s_cbranch_execz BB5_2 +; GFX7LESS-NEXT: BB5_1: +; GFX7LESS-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX7LESS-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX7LESS-NEXT: v_mul_hi_u32_u24_e64 v2, s4, 5 +; GFX7LESS-NEXT: v_mul_u32_u24_e64 v1, s4, 5 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2] +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB5_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v1 +; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v2 +; GFX7LESS-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v0 +; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v0 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4 +; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s2, v0 +; GFX7LESS-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: add_i64_constant: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: ; mask branch BB5_2 +; GFX8-NEXT: s_cbranch_execz BB5_2 +; GFX8-NEXT: BB5_1: +; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX8-NEXT: v_mul_hi_u32_u24_e64 v2, s4, 5 +; GFX8-NEXT: v_mul_u32_u24_e64 v1, s4, 5 +; GFX8-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2] +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB5_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX8-NEXT: v_readfirstlane_b32 s2, v1 +; GFX8-NEXT: v_readfirstlane_b32 s3, v2 +; GFX8-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v0, 5, s[2:3] +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 2 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: add_i64_constant: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: ; mask branch BB5_2 +; GFX9-NEXT: s_cbranch_execz BB5_2 +; GFX9-NEXT: BB5_1: +; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX9-NEXT: v_mul_hi_u32_u24_e64 v2, s4, 5 +; GFX9-NEXT: v_mul_u32_u24_e64 v1, s4, 5 +; GFX9-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB5_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: v_readfirstlane_b32 s2, v1 +; GFX9-NEXT: v_readfirstlane_b32 s3, v2 +; GFX9-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v0, 5, s[2:3] +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 2 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: add_i64_constant: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB5_2 +; GFX1064-NEXT: s_cbranch_execz BB5_2 +; GFX1064-NEXT: BB5_1: +; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1064-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX1064-NEXT: v_mul_hi_u32_u24_e64 v2, s2, 5 +; GFX1064-NEXT: v_mul_u32_u24_e64 v1, s2, 5 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2] +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB5_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1064-NEXT: v_readfirstlane_b32 s3, v2 +; GFX1064-NEXT: v_mad_u64_u32 v[0:1], s[2:3], v0, 5, s[2:3] +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: s_nop 2 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: add_i64_constant: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s3, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s3, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX1032-NEXT: ; mask branch BB5_2 +; GFX1032-NEXT: s_cbranch_execz BB5_2 +; GFX1032-NEXT: BB5_1: +; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX1032-NEXT: v_mul_hi_u32_u24_e64 v2, s3, 5 +; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s3, 5 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2] +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB5_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX1032-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v2 +; GFX1032-NEXT: v_mad_u64_u32 v[0:1], s2, v0, 5, s[2:3] +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: s_nop 2 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw add i64 addrspace(3)* @local_var64, i64 5 acq_rel store i64 %old, i64 addrspace(1)* %out ret void } -; GCN-LABEL: add_i64_uniform: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN32: s_bcnt1_i32_b32 s{{[0-9]+}}, s[[exec_lo]] -; GCN64: s_bcnt1_i32_b64 s{{[0-9]+}}, s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} -; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}} define amdgpu_kernel void @add_i64_uniform(i64 addrspace(1)* %out, i64 %additive) { +; +; +; GFX7LESS-LABEL: add_i64_uniform: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX7LESS-NEXT: ; mask branch BB6_2 +; GFX7LESS-NEXT: s_cbranch_execz BB6_2 +; GFX7LESS-NEXT: BB6_1: +; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7] +; GFX7LESS-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: s_mul_i32 s7, s3, s6 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, s6 +; GFX7LESS-NEXT: v_mul_hi_u32 v1, s2, v1 +; GFX7LESS-NEXT: s_mul_i32 s6, s2, s6 +; GFX7LESS-NEXT: v_add_i32_e32 v2, vcc, s7, v1 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, s6 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2] +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB6_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s6, -1 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: s_mov_b32 s4, s0 +; GFX7LESS-NEXT: s_mov_b32 s5, s1 +; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1 +; GFX7LESS-NEXT: v_readfirstlane_b32 s1, v2 +; GFX7LESS-NEXT: v_mul_lo_u32 v1, s3, v0 +; GFX7LESS-NEXT: v_mul_hi_u32 v2, s2, v0 +; GFX7LESS-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX7LESS-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s1 +; GFX7LESS-NEXT: v_add_i32_e32 v0, vcc, s0, v0 +; GFX7LESS-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: add_i64_uniform: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB6_2 +; GFX8-NEXT: s_cbranch_execz BB6_2 +; GFX8-NEXT: BB6_1: +; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7] +; GFX8-NEXT: v_mov_b32_e32 v1, s6 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mul_hi_u32 v1, s2, v1 +; GFX8-NEXT: s_mul_i32 s7, s3, s6 +; GFX8-NEXT: s_mul_i32 s6, s2, s6 +; GFX8-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX8-NEXT: v_add_u32_e32 v2, vcc, s7, v1 +; GFX8-NEXT: v_mov_b32_e32 v1, s6 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2] +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB6_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_mov_b32 s4, s0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v1 +; GFX8-NEXT: v_mul_lo_u32 v1, s3, v0 +; GFX8-NEXT: v_mul_hi_u32 v3, s2, v0 +; GFX8-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX8-NEXT: s_mov_b32 s5, s1 +; GFX8-NEXT: v_readfirstlane_b32 s1, v2 +; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v1 +; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, v2, v1, vcc +; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: add_i64_uniform: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB6_2 +; GFX9-NEXT: s_cbranch_execz BB6_2 +; GFX9-NEXT: BB6_1: +; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[6:7] +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mul_hi_u32 v2, s2, v1 +; GFX9-NEXT: s_mul_i32 s7, s3, s6 +; GFX9-NEXT: s_mul_i32 s6, s2, s6 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: v_add_u32_e32 v2, s7, v2 +; GFX9-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB6_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mul_lo_u32 v3, s3, v0 +; GFX9-NEXT: v_mul_hi_u32 v4, s2, v0 +; GFX9-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s4, s0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v1 +; GFX9-NEXT: s_mov_b32 s5, s1 +; GFX9-NEXT: v_readfirstlane_b32 s1, v2 +; GFX9-NEXT: v_add_u32_e32 v1, v4, v3 +; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, s0, v0 +; GFX9-NEXT: s_mov_b32 s7, 0xf000 +; GFX9-NEXT: s_mov_b32 s6, -1 +; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: add_i64_uniform: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s7, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB6_2 +; GFX1064-NEXT: s_cbranch_execz BB6_2 +; GFX1064-NEXT: BB6_1: +; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7] +; GFX1064-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: v_mul_hi_u32 v2, s2, s6 +; GFX1064-NEXT: s_mul_i32 s7, s2, s6 +; GFX1064-NEXT: s_mul_i32 s6, s3, s6 +; GFX1064-NEXT: v_mov_b32_e32 v1, s7 +; GFX1064-NEXT: v_add_nc_u32_e32 v2, s6, v2 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2] +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB6_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v0 +; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v0 +; GFX1064-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s4, v1 +; GFX1064-NEXT: v_readfirstlane_b32 s5, v2 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3 +; GFX1064-NEXT: v_add_co_u32_e64 v0, vcc, s4, v0 +; GFX1064-NEXT: v_add_co_ci_u32_e32 v1, vcc, s5, v1, vcc +; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: add_i64_uniform: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s5, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s5, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB6_2 +; GFX1032-NEXT: s_cbranch_execz BB6_2 +; GFX1032-NEXT: BB6_1: +; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5 +; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: v_mul_hi_u32 v2, s2, s5 +; GFX1032-NEXT: s_mul_i32 s6, s2, s5 +; GFX1032-NEXT: s_mul_i32 s5, s3, s5 +; GFX1032-NEXT: v_mov_b32_e32 v1, s6 +; GFX1032-NEXT: v_add_nc_u32_e32 v2, s5, v2 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_add_rtn_u64 v[1:2], v3, v[1:2] +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB6_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v0 +; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v0 +; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s4, v1 +; GFX1032-NEXT: v_readfirstlane_b32 s5, v2 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3 +; GFX1032-NEXT: v_add_co_u32_e64 v0, vcc_lo, s4, v0 +; GFX1032-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo +; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw add i64 addrspace(3)* @local_var64, i64 %additive acq_rel store i64 %old, i64 addrspace(1)* %out ret void } -; GCN-LABEL: add_i64_varying: ; GCN-NOT: v_mbcnt_lo_u32_b32 ; GCN-NOT: v_mbcnt_hi_u32_b32 ; GCN-NOT: s_bcnt1_i32_b64 -; GCN: ds_add_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}} define amdgpu_kernel void @add_i64_varying(i64 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: add_i64_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 +; GFX7LESS-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_add_rtn_u64 v[0:1], v2, v[0:1] +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: add_i64_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_add_rtn_u64 v[0:1], v2, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: add_i64_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_add_rtn_u64 v[0:1], v2, v[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: add_i64_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_add_rtn_u64 v[0:1], v2, v[0:1] +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: add_i64_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_add_rtn_u64 v[0:1], v2, v[0:1] +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %zext = zext i32 %lane to i64 @@ -256,53 +1592,601 @@ entry: ret void } -; GCN-LABEL: sub_i32_constant: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] -; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} -; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[popcount]], 5 -; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @sub_i32_constant(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: sub_i32_constant: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr1 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX7LESS-NEXT: ; mask branch BB8_2 +; GFX7LESS-NEXT: s_cbranch_execz BB8_2 +; GFX7LESS-NEXT: BB8_1: +; GFX7LESS-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: v_mul_u32_u24_e64 v2, s4, 5 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_sub_rtn_u32 v1, v1, v2 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB8_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v1 +; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v0 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: sub_i32_constant: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr1 +; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: ; mask branch BB8_2 +; GFX8-NEXT: s_cbranch_execz BB8_2 +; GFX8-NEXT: BB8_1: +; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX8-NEXT: v_mul_u32_u24_e64 v1, s4, 5 +; GFX8-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_sub_rtn_u32 v1, v2, v1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB8_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX8-NEXT: v_readfirstlane_b32 s2, v1 +; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v0 +; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: sub_i32_constant: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: ; mask branch BB8_2 +; GFX9-NEXT: s_cbranch_execz BB8_2 +; GFX9-NEXT: BB8_1: +; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX9-NEXT: v_mul_u32_u24_e64 v1, s4, 5 +; GFX9-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_sub_rtn_u32 v1, v2, v1 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB8_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: v_readfirstlane_b32 s2, v1 +; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v0 +; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: sub_i32_constant: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: ; implicit-def: $vgpr1 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB8_2 +; GFX1064-NEXT: s_cbranch_execz BB8_2 +; GFX1064-NEXT: BB8_1: +; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1064-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo +; GFX1064-NEXT: v_mul_u32_u24_e64 v1, s2, 5 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_sub_rtn_u32 v1, v2, v1 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB8_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1064-NEXT: v_mul_u32_u24_e32 v0, 5, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s2, v0 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: s_nop 0 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: sub_i32_constant: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s3, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: ; implicit-def: $vgpr1 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s3, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX1032-NEXT: ; mask branch BB8_2 +; GFX1032-NEXT: s_cbranch_execz BB8_2 +; GFX1032-NEXT: BB8_1: +; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1032-NEXT: v_mov_b32_e32 v2, local_var32@abs32@lo +; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s3, 5 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_sub_rtn_u32 v1, v2, v1 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB8_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX1032-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1032-NEXT: v_mul_u32_u24_e32 v0, 5, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s2, v0 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: s_nop 0 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw sub i32 addrspace(3)* @local_var32, i32 5 acq_rel store i32 %old, i32 addrspace(1)* %out ret void } -; GCN-LABEL: sub_i32_uniform: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] -; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} -; GCN: s_mul_i32 s[[scalar_value:[0-9]+]], s{{[0-9]+}}, s[[popcount]] -; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] -; GCN: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @sub_i32_uniform(i32 addrspace(1)* %out, i32 %subitive) { +; +; +; GFX7LESS-LABEL: sub_i32_uniform: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GFX7LESS-NEXT: s_load_dword s2, s[0:1], 0xb +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr1 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[0:1], vcc +; GFX7LESS-NEXT: ; mask branch BB9_2 +; GFX7LESS-NEXT: s_cbranch_execz BB9_2 +; GFX7LESS-NEXT: BB9_1: +; GFX7LESS-NEXT: s_bcnt1_i32_b64 s3, s[6:7] +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: s_mul_i32 s3, s2, s3 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s3 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_sub_rtn_u32 v1, v1, v2 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB9_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1] +; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 +; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GFX7LESS-NEXT: s_mov_b32 s6, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: sub_i32_uniform: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX8-NEXT: s_load_dword s0, s[0:1], 0x2c +; GFX8-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr1 +; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: ; mask branch BB9_2 +; GFX8-NEXT: s_cbranch_execz BB9_2 +; GFX8-NEXT: BB9_1: +; GFX8-NEXT: s_bcnt1_i32_b64 s1, s[6:7] +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_mul_i32 s1, s0, s1 +; GFX8-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_sub_rtn_u32 v1, v1, v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB9_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mul_lo_u32 v0, s0, v0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v1 +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0 +; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: sub_i32_uniform: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX9-NEXT: s_load_dword s0, s[0:1], 0x2c +; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: ; mask branch BB9_2 +; GFX9-NEXT: s_cbranch_execz BB9_2 +; GFX9-NEXT: BB9_1: +; GFX9-NEXT: s_bcnt1_i32_b64 s1, s[6:7] +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: s_mul_i32 s1, s0, s1 +; GFX9-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_sub_rtn_u32 v1, v1, v2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB9_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mul_lo_u32 v0, s0, v0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v1 +; GFX9-NEXT: s_mov_b32 s7, 0xf000 +; GFX9-NEXT: s_mov_b32 s6, -1 +; GFX9-NEXT: v_sub_u32_e32 v0, s0, v0 +; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: sub_i32_uniform: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: s_load_dword s0, s[0:1], 0x2c +; GFX1064-NEXT: ; implicit-def: $vgpr1 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: s_and_saveexec_b64 s[6:7], vcc +; GFX1064-NEXT: ; mask branch BB9_2 +; GFX1064-NEXT: s_cbranch_execz BB9_2 +; GFX1064-NEXT: BB9_1: +; GFX1064-NEXT: s_bcnt1_i32_b64 s1, s[2:3] +; GFX1064-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: s_mul_i32 s1, s0, s1 +; GFX1064-NEXT: v_mov_b32_e32 v2, s1 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_sub_rtn_u32 v1, v1, v2 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB9_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[6:7] +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: v_mul_lo_u32 v0, s0, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s0, v1 +; GFX1064-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1064-NEXT: s_mov_b32 s6, -1 +; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s0, v0 +; GFX1064-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: sub_i32_uniform: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 +; GFX1032-NEXT: s_load_dword s0, s[0:1], 0x2c +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: ; implicit-def: $vgpr1 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: s_and_saveexec_b32 s1, vcc_lo +; GFX1032-NEXT: ; mask branch BB9_2 +; GFX1032-NEXT: s_cbranch_execz BB9_2 +; GFX1032-NEXT: BB9_1: +; GFX1032-NEXT: s_bcnt1_i32_b32 s2, s2 +; GFX1032-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: s_mul_i32 s2, s0, s2 +; GFX1032-NEXT: v_mov_b32_e32 v2, s2 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_sub_rtn_u32 v1, v1, v2 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB9_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: v_mul_lo_u32 v0, s0, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s0, v1 +; GFX1032-NEXT: s_mov_b32 s7, 0x31016000 +; GFX1032-NEXT: s_mov_b32 s6, -1 +; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s0, v0 +; GFX1032-NEXT: buffer_store_dword v0, off, s[4:7], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw sub i32 addrspace(3)* @local_var32, i32 %subitive acq_rel store i32 %old, i32 addrspace(1)* %out ret void } -; GCN-LABEL: sub_i32_varying: ; GFX7LESS-NOT: v_mbcnt_lo_u32_b32 ; GFX7LESS-NOT: v_mbcnt_hi_u32_b32 ; GFX7LESS-NOT: s_bcnt1_i32_b64 -; GFX7LESS: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; DPPCOMB: v_add_u32_dpp ; DPPCOMB: v_add_u32_dpp ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 -; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 ; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GFX8MORE: ds_sub_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @sub_i32_varying(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: sub_i32_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_sub_rtn_u32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: sub_i32_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, 0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_add_u32_dpp v2, vcc, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB10_2 +; GFX8-NEXT: s_cbranch_execz BB10_2 +; GFX8-NEXT: BB10_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_sub_rtn_u32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB10_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: sub_i32_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_add_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB10_2 +; GFX9-NEXT: s_cbranch_execz BB10_2 +; GFX9-NEXT: BB10_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_sub_rtn_u32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB10_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_sub_u32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: sub_i32_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, 0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB10_2 +; GFX1064-NEXT: s_cbranch_execz BB10_2 +; GFX1064-NEXT: BB10_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_sub_rtn_u32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB10_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_sub_nc_u32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: sub_i32_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_add_nc_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB10_2 +; GFX1032-NEXT: s_cbranch_execz BB10_2 +; GFX1032-NEXT: BB10_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_sub_rtn_u32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB10_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_sub_nc_u32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw sub i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -310,46 +2194,505 @@ entry: ret void } -; GCN-LABEL: sub_i64_constant: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN32: s_bcnt1_i32_b32 s[[popcount:[0-9]+]], s[[exec_lo]] -; GCN64: s_bcnt1_i32_b64 s[[popcount:[0-9]+]], s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} -; GCN: v_mul_hi_u32_u24{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], s[[popcount]], 5 -; GCN: v_mul_u32_u24{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], s[[popcount]], 5 -; GCN: ds_sub_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} define amdgpu_kernel void @sub_i64_constant(i64 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: sub_i64_constant: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s4, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s5, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX7LESS-NEXT: ; mask branch BB11_2 +; GFX7LESS-NEXT: s_cbranch_execz BB11_2 +; GFX7LESS-NEXT: BB11_1: +; GFX7LESS-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX7LESS-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX7LESS-NEXT: v_mul_hi_u32_u24_e64 v2, s4, 5 +; GFX7LESS-NEXT: v_mul_u32_u24_e64 v1, s4, 5 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2] +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB11_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX7LESS-NEXT: v_readfirstlane_b32 s2, v1 +; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v2 +; GFX7LESS-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v0 +; GFX7LESS-NEXT: v_mul_u32_u24_e32 v0, 5, v0 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4 +; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s2, v0 +; GFX7LESS-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: sub_i64_constant: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: ; mask branch BB11_2 +; GFX8-NEXT: s_cbranch_execz BB11_2 +; GFX8-NEXT: BB11_1: +; GFX8-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX8-NEXT: v_mul_hi_u32_u24_e64 v2, s4, 5 +; GFX8-NEXT: v_mul_u32_u24_e64 v1, s4, 5 +; GFX8-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2] +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB11_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX8-NEXT: v_readfirstlane_b32 s3, v2 +; GFX8-NEXT: v_readfirstlane_b32 s2, v1 +; GFX8-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v0 +; GFX8-NEXT: v_mul_u32_u24_e32 v0, 5, v0 +; GFX8-NEXT: v_mov_b32_e32 v2, s3 +; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s2, v0 +; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: sub_i64_constant: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s4, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s5, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: ; mask branch BB11_2 +; GFX9-NEXT: s_cbranch_execz BB11_2 +; GFX9-NEXT: BB11_1: +; GFX9-NEXT: s_bcnt1_i32_b64 s4, s[4:5] +; GFX9-NEXT: v_mul_hi_u32_u24_e64 v2, s4, 5 +; GFX9-NEXT: v_mul_u32_u24_e64 v1, s4, 5 +; GFX9-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB11_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: v_readfirstlane_b32 s3, v2 +; GFX9-NEXT: v_readfirstlane_b32 s2, v1 +; GFX9-NEXT: v_mul_hi_u32_u24_e32 v1, 5, v0 +; GFX9-NEXT: v_mul_u32_u24_e32 v0, 5, v0 +; GFX9-NEXT: v_mov_b32_e32 v2, s3 +; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s2, v0 +; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: sub_i64_constant: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB11_2 +; GFX1064-NEXT: s_cbranch_execz BB11_2 +; GFX1064-NEXT: BB11_1: +; GFX1064-NEXT: s_bcnt1_i32_b64 s2, s[2:3] +; GFX1064-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX1064-NEXT: v_mul_hi_u32_u24_e64 v2, s2, 5 +; GFX1064-NEXT: v_mul_u32_u24_e64 v1, s2, 5 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2] +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB11_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1064-NEXT: v_mul_u32_u24_e32 v1, 5, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s3, v2 +; GFX1064-NEXT: v_mul_hi_u32_u24_e32 v2, 5, v0 +; GFX1064-NEXT: v_sub_co_u32_e64 v0, vcc, s2, v1 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s3, v2, vcc +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: sub_i64_constant: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s3, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s3, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX1032-NEXT: ; mask branch BB11_2 +; GFX1032-NEXT: s_cbranch_execz BB11_2 +; GFX1032-NEXT: BB11_1: +; GFX1032-NEXT: s_bcnt1_i32_b32 s3, s3 +; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX1032-NEXT: v_mul_hi_u32_u24_e64 v2, s3, 5 +; GFX1032-NEXT: v_mul_u32_u24_e64 v1, s3, 5 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2] +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB11_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX1032-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1032-NEXT: v_mul_u32_u24_e32 v1, 5, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v2 +; GFX1032-NEXT: v_mul_hi_u32_u24_e32 v2, 5, v0 +; GFX1032-NEXT: v_sub_co_u32_e64 v0, vcc_lo, s2, v1 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw sub i64 addrspace(3)* @local_var64, i64 5 acq_rel store i64 %old, i64 addrspace(1)* %out ret void } -; GCN-LABEL: sub_i64_uniform: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN32: s_bcnt1_i32_b32 s{{[0-9]+}}, s[[exec_lo]] -; GCN64: s_bcnt1_i32_b64 s{{[0-9]+}}, s{{\[}}[[exec_lo]]:[[exec_hi]]{{\]}} -; GCN: ds_sub_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}} define amdgpu_kernel void @sub_i64_uniform(i64 addrspace(1)* %out, i64 %subitive) { +; +; +; GFX7LESS-LABEL: sub_i64_uniform: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s7, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX7LESS-NEXT: ; mask branch BB12_2 +; GFX7LESS-NEXT: s_cbranch_execz BB12_2 +; GFX7LESS-NEXT: BB12_1: +; GFX7LESS-NEXT: s_bcnt1_i32_b64 s6, s[6:7] +; GFX7LESS-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: s_mul_i32 s7, s3, s6 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, s6 +; GFX7LESS-NEXT: v_mul_hi_u32 v1, s2, v1 +; GFX7LESS-NEXT: s_mul_i32 s6, s2, s6 +; GFX7LESS-NEXT: v_add_i32_e32 v2, vcc, s7, v1 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, s6 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2] +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB12_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX7LESS-NEXT: s_mov_b32 s7, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s6, -1 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: s_mov_b32 s4, s0 +; GFX7LESS-NEXT: s_mov_b32 s5, s1 +; GFX7LESS-NEXT: v_readfirstlane_b32 s0, v1 +; GFX7LESS-NEXT: v_readfirstlane_b32 s1, v2 +; GFX7LESS-NEXT: v_mul_lo_u32 v1, s3, v0 +; GFX7LESS-NEXT: v_mul_hi_u32 v2, s2, v0 +; GFX7LESS-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX7LESS-NEXT: v_add_i32_e32 v1, vcc, v2, v1 +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s1 +; GFX7LESS-NEXT: v_sub_i32_e32 v0, vcc, s0, v0 +; GFX7LESS-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc +; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: sub_i64_uniform: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB12_2 +; GFX8-NEXT: s_cbranch_execz BB12_2 +; GFX8-NEXT: BB12_1: +; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7] +; GFX8-NEXT: v_mov_b32_e32 v1, s6 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mul_hi_u32 v1, s2, v1 +; GFX8-NEXT: s_mul_i32 s7, s3, s6 +; GFX8-NEXT: s_mul_i32 s6, s2, s6 +; GFX8-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX8-NEXT: v_add_u32_e32 v2, vcc, s7, v1 +; GFX8-NEXT: v_mov_b32_e32 v1, s6 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2] +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB12_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: s_mov_b32 s4, s0 +; GFX8-NEXT: v_readfirstlane_b32 s0, v1 +; GFX8-NEXT: v_mul_lo_u32 v1, s3, v0 +; GFX8-NEXT: v_mul_hi_u32 v3, s2, v0 +; GFX8-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX8-NEXT: s_mov_b32 s5, s1 +; GFX8-NEXT: v_readfirstlane_b32 s1, v2 +; GFX8-NEXT: v_add_u32_e32 v1, vcc, v3, v1 +; GFX8-NEXT: v_mov_b32_e32 v2, s1 +; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0 +; GFX8-NEXT: s_mov_b32 s7, 0xf000 +; GFX8-NEXT: s_mov_b32 s6, -1 +; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc +; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: sub_i64_uniform: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB12_2 +; GFX9-NEXT: s_cbranch_execz BB12_2 +; GFX9-NEXT: BB12_1: +; GFX9-NEXT: s_bcnt1_i32_b64 s6, s[6:7] +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mul_hi_u32 v2, s2, v1 +; GFX9-NEXT: s_mul_i32 s7, s3, s6 +; GFX9-NEXT: s_mul_i32 s6, s2, s6 +; GFX9-NEXT: v_mov_b32_e32 v1, s6 +; GFX9-NEXT: v_add_u32_e32 v2, s7, v2 +; GFX9-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB12_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_mul_lo_u32 v3, s3, v0 +; GFX9-NEXT: v_mul_hi_u32 v4, s2, v0 +; GFX9-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s4, s0 +; GFX9-NEXT: v_readfirstlane_b32 s0, v1 +; GFX9-NEXT: s_mov_b32 s5, s1 +; GFX9-NEXT: v_readfirstlane_b32 s1, v2 +; GFX9-NEXT: v_add_u32_e32 v1, v4, v3 +; GFX9-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v0 +; GFX9-NEXT: s_mov_b32 s7, 0xf000 +; GFX9-NEXT: s_mov_b32 s6, -1 +; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: sub_i64_uniform: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[6:7], 1, 0 +; GFX1064-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX1064-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s6, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s7, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB12_2 +; GFX1064-NEXT: s_cbranch_execz BB12_2 +; GFX1064-NEXT: BB12_1: +; GFX1064-NEXT: s_bcnt1_i32_b64 s6, s[6:7] +; GFX1064-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: v_mul_hi_u32 v2, s2, s6 +; GFX1064-NEXT: s_mul_i32 s7, s2, s6 +; GFX1064-NEXT: s_mul_i32 s6, s3, s6 +; GFX1064-NEXT: v_mov_b32_e32 v1, s7 +; GFX1064-NEXT: v_add_nc_u32_e32 v2, s6, v2 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2] +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB12_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: v_mul_lo_u32 v3, s3, v0 +; GFX1064-NEXT: v_mul_hi_u32 v4, s2, v0 +; GFX1064-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s4, v1 +; GFX1064-NEXT: v_readfirstlane_b32 s5, v2 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_add_nc_u32_e32 v1, v4, v3 +; GFX1064-NEXT: v_sub_co_u32_e64 v0, vcc, s4, v0 +; GFX1064-NEXT: v_sub_co_ci_u32_e32 v1, vcc, s5, v1, vcc +; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: sub_i64_uniform: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s5, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: ; implicit-def: $vgpr1_vgpr2 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s5, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB12_2 +; GFX1032-NEXT: s_cbranch_execz BB12_2 +; GFX1032-NEXT: BB12_1: +; GFX1032-NEXT: s_bcnt1_i32_b32 s5, s5 +; GFX1032-NEXT: v_mov_b32_e32 v3, local_var64@abs32@lo +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: v_mul_hi_u32 v2, s2, s5 +; GFX1032-NEXT: s_mul_i32 s6, s2, s5 +; GFX1032-NEXT: s_mul_i32 s5, s3, s5 +; GFX1032-NEXT: v_mov_b32_e32 v1, s6 +; GFX1032-NEXT: v_add_nc_u32_e32 v2, s5, v2 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_sub_rtn_u64 v[1:2], v3, v[1:2] +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB12_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: v_mul_lo_u32 v3, s3, v0 +; GFX1032-NEXT: v_mul_hi_u32 v4, s2, v0 +; GFX1032-NEXT: v_mul_lo_u32 v0, s2, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s4, v1 +; GFX1032-NEXT: v_readfirstlane_b32 s5, v2 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_add_nc_u32_e32 v1, v4, v3 +; GFX1032-NEXT: v_sub_co_u32_e64 v0, vcc_lo, s4, v0 +; GFX1032-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s5, v1, vcc_lo +; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw sub i64 addrspace(3)* @local_var64, i64 %subitive acq_rel store i64 %old, i64 addrspace(1)* %out ret void } -; GCN-LABEL: sub_i64_varying: ; GCN-NOT: v_mbcnt_lo_u32_b32 ; GCN-NOT: v_mbcnt_hi_u32_b32 ; GCN-NOT: s_bcnt1_i32_b64 -; GCN: ds_sub_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}} define amdgpu_kernel void @sub_i64_varying(i64 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: sub_i64_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 +; GFX7LESS-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_sub_rtn_u64 v[0:1], v2, v[0:1] +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: sub_i64_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_sub_rtn_u64 v[0:1], v2, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: sub_i64_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_sub_rtn_u64 v[0:1], v2, v[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: sub_i64_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_sub_rtn_u64 v[0:1], v2, v[0:1] +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: sub_i64_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_sub_rtn_u64 v[0:1], v2, v[0:1] +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %zext = zext i32 %lane to i64 @@ -358,12 +2701,245 @@ entry: ret void } -; GCN-LABEL: and_i32_varying: ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 -; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 ; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GFX8MORE: ds_and_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @and_i32_varying(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: and_i32_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_and_rtn_b32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: and_i32_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v3, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v3, s3, v3 +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: v_mov_b32_e32 v1, -1 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, -1 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_and_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_and_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB14_2 +; GFX8-NEXT: s_cbranch_execz BB14_2 +; GFX8-NEXT: BB14_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_and_rtn_b32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB14_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_and_b32_e32 v0, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: and_i32_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v3, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v3, s3, v3 +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: v_mov_b32_e32 v1, -1 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, -1 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_and_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_and_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB14_2 +; GFX9-NEXT: s_cbranch_execz BB14_2 +; GFX9-NEXT: BB14_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_and_rtn_b32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB14_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_and_b32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: and_i32_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v4, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v4, s3, v4 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: v_mov_b32_e32 v1, -1 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, -1 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_and_b32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_and_b32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB14_2 +; GFX1064-NEXT: s_cbranch_execz BB14_2 +; GFX1064-NEXT: BB14_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_and_rtn_b32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB14_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_and_b32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: and_i32_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v4, s2, 0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: v_mov_b32_e32 v1, -1 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, -1 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_and_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_and_b32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB14_2 +; GFX1032-NEXT: s_cbranch_execz BB14_2 +; GFX1032-NEXT: BB14_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_and_rtn_b32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB14_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_and_b32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw and i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -371,12 +2947,245 @@ entry: ret void } -; GCN-LABEL: or_i32_varying: ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 -; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 ; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GFX8MORE: ds_or_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @or_i32_varying(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: or_i32_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_or_rtn_b32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: or_i32_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, 0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB15_2 +; GFX8-NEXT: s_cbranch_execz BB15_2 +; GFX8-NEXT: BB15_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_or_rtn_b32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB15_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_or_b32_e32 v0, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: or_i32_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_or_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB15_2 +; GFX9-NEXT: s_cbranch_execz BB15_2 +; GFX9-NEXT: BB15_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_or_rtn_b32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB15_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_or_b32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: or_i32_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, 0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_or_b32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_or_b32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB15_2 +; GFX1064-NEXT: s_cbranch_execz BB15_2 +; GFX1064-NEXT: BB15_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_or_rtn_b32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB15_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_or_b32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: or_i32_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_or_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_or_b32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB15_2 +; GFX1032-NEXT: s_cbranch_execz BB15_2 +; GFX1032-NEXT: BB15_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_or_rtn_b32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB15_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_or_b32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw or i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -384,12 +3193,245 @@ entry: ret void } -; GCN-LABEL: xor_i32_varying: ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 -; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 ; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GFX8MORE: ds_xor_rtn_b32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @xor_i32_varying(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: xor_i32_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_xor_rtn_b32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: xor_i32_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, 0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB16_2 +; GFX8-NEXT: s_cbranch_execz BB16_2 +; GFX8-NEXT: BB16_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_xor_rtn_b32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB16_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_xor_b32_e32 v0, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: xor_i32_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_xor_b32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB16_2 +; GFX9-NEXT: s_cbranch_execz BB16_2 +; GFX9-NEXT: BB16_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_xor_rtn_b32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB16_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_xor_b32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: xor_i32_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, 0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_xor_b32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_xor_b32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB16_2 +; GFX1064-NEXT: s_cbranch_execz BB16_2 +; GFX1064-NEXT: BB16_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_xor_rtn_b32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB16_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_xor_b32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: xor_i32_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_xor_b32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_xor_b32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB16_2 +; GFX1032-NEXT: s_cbranch_execz BB16_2 +; GFX1032-NEXT: BB16_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_xor_rtn_b32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB16_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_xor_b32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw xor i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -397,12 +3439,245 @@ entry: ret void } -; GCN-LABEL: max_i32_varying: ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 -; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 ; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GFX8MORE: ds_max_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @max_i32_varying(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: max_i32_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_max_rtn_i32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: max_i32_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v3, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v3, s3, v3 +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, v1 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_max_i32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_max_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB17_2 +; GFX8-NEXT: s_cbranch_execz BB17_2 +; GFX8-NEXT: BB17_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_max_rtn_i32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB17_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_max_i32_e32 v0, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: max_i32_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v3, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v3, s3, v3 +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, v1 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_max_i32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_max_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB17_2 +; GFX9-NEXT: s_cbranch_execz BB17_2 +; GFX9-NEXT: BB17_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_max_rtn_i32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB17_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_max_i32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: max_i32_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v4, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v4, s3, v4 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, v1 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_max_i32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_max_i32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB17_2 +; GFX1064-NEXT: s_cbranch_execz BB17_2 +; GFX1064-NEXT: BB17_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_max_rtn_i32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB17_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_max_i32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: max_i32_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v4, s2, 0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, v1 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_max_i32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_max_i32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB17_2 +; GFX1032-NEXT: s_cbranch_execz BB17_2 +; GFX1032-NEXT: BB17_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_max_rtn_i32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB17_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_max_i32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw max i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -410,28 +3685,440 @@ entry: ret void } -; GCN-LABEL: max_i64_constant: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], 5 -; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], 0 -; GCN: ds_max_rtn_i64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} define amdgpu_kernel void @max_i64_constant(i64 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: max_i64_constant: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX7LESS-NEXT: ; mask branch BB18_2 +; GFX7LESS-NEXT: s_cbranch_execz BB18_2 +; GFX7LESS-NEXT: BB18_1: +; GFX7LESS-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB18_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0 +; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1 +; GFX7LESS-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s5 +; GFX7LESS-NEXT: v_mov_b32_e32 v3, s4 +; GFX7LESS-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[0:1] +; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX7LESS-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: max_i64_constant: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: ; mask branch BB18_2 +; GFX8-NEXT: s_cbranch_execz BB18_2 +; GFX8-NEXT: BB18_1: +; GFX8-NEXT: v_mov_b32_e32 v0, 5 +; GFX8-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB18_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_bfrev_b32_e32 v0, 1 +; GFX8-NEXT: v_readfirstlane_b32 s3, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v2, s3 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX8-NEXT: v_mov_b32_e32 v2, s2 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: max_i64_constant: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: ; mask branch BB18_2 +; GFX9-NEXT: s_cbranch_execz BB18_2 +; GFX9-NEXT: BB18_1: +; GFX9-NEXT: v_mov_b32_e32 v0, 5 +; GFX9-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB18_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_bfrev_b32_e32 v0, 1 +; GFX9-NEXT: v_readfirstlane_b32 s3, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[0:1] +; GFX9-NEXT: v_mov_b32_e32 v2, s3 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX9-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: max_i64_constant: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX1064-NEXT: ; mask branch BB18_2 +; GFX1064-NEXT: s_cbranch_execz BB18_2 +; GFX1064-NEXT: BB18_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, 5 +; GFX1064-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB18_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_cmp_gt_i64_e32 vcc, s[4:5], v[0:1] +; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: max_i64_constant: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX1032-NEXT: ; mask branch BB18_2 +; GFX1032-NEXT: s_cbranch_execz BB18_2 +; GFX1032-NEXT: BB18_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, 5 +; GFX1032-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_max_rtn_i64 v[0:1], v2, v[0:1] +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB18_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x80000000, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[4:5], v[0:1] +; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw max i64 addrspace(3)* @local_var64, i64 5 acq_rel store i64 %old, i64 addrspace(1)* %out ret void } -; GCN-LABEL: min_i32_varying: ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 -; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 ; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GFX8MORE: ds_min_rtn_i32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @min_i32_varying(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: min_i32_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_min_rtn_i32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: min_i32_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v3, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v3, s3, v3 +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: v_bfrev_b32_e32 v1, -2 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, v1 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_min_i32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_min_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB19_2 +; GFX8-NEXT: s_cbranch_execz BB19_2 +; GFX8-NEXT: BB19_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_min_rtn_i32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB19_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_min_i32_e32 v0, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: min_i32_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v3, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v3, s3, v3 +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: v_bfrev_b32_e32 v1, -2 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, v1 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_min_i32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_min_i32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB19_2 +; GFX9-NEXT: s_cbranch_execz BB19_2 +; GFX9-NEXT: BB19_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_min_rtn_i32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB19_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_min_i32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: min_i32_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v4, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v4, s3, v4 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: v_bfrev_b32_e32 v1, -2 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, v1 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_min_i32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_min_i32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB19_2 +; GFX1064-NEXT: s_cbranch_execz BB19_2 +; GFX1064-NEXT: BB19_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_min_rtn_i32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB19_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_min_i32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: min_i32_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v4, s2, 0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: v_bfrev_b32_e32 v1, -2 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, v1 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_min_i32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_min_i32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB19_2 +; GFX1032-NEXT: s_cbranch_execz BB19_2 +; GFX1032-NEXT: BB19_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_min_rtn_i32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB19_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_min_i32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw min i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -439,28 +4126,440 @@ entry: ret void } -; GCN-LABEL: min_i64_constant: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], 5 -; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], 0 -; GCN: ds_min_rtn_i64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} define amdgpu_kernel void @min_i64_constant(i64 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: min_i64_constant: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX7LESS-NEXT: ; mask branch BB20_2 +; GFX7LESS-NEXT: s_cbranch_execz BB20_2 +; GFX7LESS-NEXT: BB20_1: +; GFX7LESS-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB20_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0 +; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1 +; GFX7LESS-NEXT: v_bfrev_b32_e32 v1, -2 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s5 +; GFX7LESS-NEXT: v_mov_b32_e32 v3, s4 +; GFX7LESS-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1] +; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX7LESS-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: min_i64_constant: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: ; mask branch BB20_2 +; GFX8-NEXT: s_cbranch_execz BB20_2 +; GFX8-NEXT: BB20_1: +; GFX8-NEXT: v_mov_b32_e32 v0, 5 +; GFX8-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB20_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX8-NEXT: v_readfirstlane_b32 s4, v0 +; GFX8-NEXT: v_bfrev_b32_e32 v0, -2 +; GFX8-NEXT: v_readfirstlane_b32 s5, v1 +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v2, s5 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX8-NEXT: v_mov_b32_e32 v2, s4 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: min_i64_constant: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: ; mask branch BB20_2 +; GFX9-NEXT: s_cbranch_execz BB20_2 +; GFX9-NEXT: BB20_1: +; GFX9-NEXT: v_mov_b32_e32 v0, 5 +; GFX9-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB20_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: v_readfirstlane_b32 s4, v0 +; GFX9-NEXT: v_bfrev_b32_e32 v0, -2 +; GFX9-NEXT: v_readfirstlane_b32 s5, v1 +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v0, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1] +; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX9-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: min_i64_constant: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX1064-NEXT: ; mask branch BB20_2 +; GFX1064-NEXT: s_cbranch_execz BB20_2 +; GFX1064-NEXT: BB20_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, 5 +; GFX1064-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB20_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1] +; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: min_i64_constant: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX1032-NEXT: ; mask branch BB20_2 +; GFX1032-NEXT: s_cbranch_execz BB20_2 +; GFX1032-NEXT: BB20_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, 5 +; GFX1032-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_min_rtn_i64 v[0:1], v2, v[0:1] +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB20_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, 0x7fffffff, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: v_cmp_lt_i64_e32 vcc_lo, s[4:5], v[0:1] +; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw min i64 addrspace(3)* @local_var64, i64 5 acq_rel store i64 %old, i64 addrspace(1)* %out ret void } -; GCN-LABEL: umax_i32_varying: ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 -; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 ; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GFX8MORE: ds_max_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @umax_i32_varying(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: umax_i32_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_max_rtn_u32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: umax_i32_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, 0 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB21_2 +; GFX8-NEXT: s_cbranch_execz BB21_2 +; GFX8-NEXT: BB21_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_max_rtn_u32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB21_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_max_u32_e32 v0, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: umax_i32_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_max_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB21_2 +; GFX9-NEXT: s_cbranch_execz BB21_2 +; GFX9-NEXT: BB21_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_max_rtn_u32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB21_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_max_u32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: umax_i32_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, 0 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_max_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_max_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB21_2 +; GFX1064-NEXT: s_cbranch_execz BB21_2 +; GFX1064-NEXT: BB21_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_max_rtn_u32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB21_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_max_u32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: umax_i32_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, 0 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_max_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:0 +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_max_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB21_2 +; GFX1032-NEXT: s_cbranch_execz BB21_2 +; GFX1032-NEXT: BB21_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_max_rtn_u32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB21_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_max_u32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw umax i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -468,28 +4567,437 @@ entry: ret void } -; GCN-LABEL: umax_i64_constant: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], 5 -; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], 0 -; GCN: ds_max_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} define amdgpu_kernel void @umax_i64_constant(i64 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: umax_i64_constant: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX7LESS-NEXT: ; mask branch BB22_2 +; GFX7LESS-NEXT: s_cbranch_execz BB22_2 +; GFX7LESS-NEXT: BB22_1: +; GFX7LESS-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB22_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0 +; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 +; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4 +; GFX7LESS-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1] +; GFX7LESS-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX7LESS-NEXT: v_mov_b32_e32 v1, s5 +; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: umax_i64_constant: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: ; mask branch BB22_2 +; GFX8-NEXT: s_cbranch_execz BB22_2 +; GFX8-NEXT: BB22_1: +; GFX8-NEXT: v_mov_b32_e32 v0, 5 +; GFX8-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB22_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_readfirstlane_b32 s3, v1 +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_mov_b32_e32 v2, s2 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: umax_i64_constant: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: ; mask branch BB22_2 +; GFX9-NEXT: s_cbranch_execz BB22_2 +; GFX9-NEXT: BB22_1: +; GFX9-NEXT: v_mov_b32_e32 v0, 5 +; GFX9-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB22_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_readfirstlane_b32 s3, v1 +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[2:3], v[0:1] +; GFX9-NEXT: v_mov_b32_e32 v1, s3 +; GFX9-NEXT: v_mov_b32_e32 v2, s2 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: umax_i64_constant: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX1064-NEXT: ; mask branch BB22_2 +; GFX1064-NEXT: s_cbranch_execz BB22_2 +; GFX1064-NEXT: BB22_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, 5 +; GFX1064-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB22_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_cmp_gt_u64_e32 vcc, s[4:5], v[0:1] +; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, s5, vcc +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: umax_i64_constant: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX1032-NEXT: ; mask branch BB22_2 +; GFX1032-NEXT: s_cbranch_execz BB22_2 +; GFX1032-NEXT: BB22_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, 5 +; GFX1032-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_max_rtn_u64 v[0:1], v2, v[0:1] +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB22_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, 0, vcc_lo +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[4:5], v[0:1] +; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, s5, vcc_lo +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw umax i64 addrspace(3)* @local_var64, i64 5 acq_rel store i64 %old, i64 addrspace(1)* %out ret void } -; GCN-LABEL: umin_i32_varying: ; GFX8MORE32: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 31 -; GFX8MORE64: v_readlane_b32 s[[scalar_value:[0-9]+]], v{{[0-9]+}}, 63 ; GFX8MORE: v_mov_b32{{(_e[0-9]+)?}} v[[value:[0-9]+]], s[[scalar_value]] ; GFX8MORE: ds_min_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, v[[value]] define amdgpu_kernel void @umin_i32_varying(i32 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: umin_i32_varying: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, local_var32@abs32@lo +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_min_rtn_u32 v0, v1, v0 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: umin_i32_varying: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v3, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v3, s3, v3 +; GFX8-NEXT: v_mov_b32_e32 v2, v0 +; GFX8-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX8-NEXT: v_mov_b32_e32 v1, -1 +; GFX8-NEXT: s_mov_b64 exec, s[2:3] +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: v_mov_b32_e32 v2, -1 +; GFX8-NEXT: s_not_b64 exec, exec +; GFX8-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX8-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_min_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX8-NEXT: s_nop 1 +; GFX8-NEXT: v_min_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX8-NEXT: v_readlane_b32 s2, v2, 63 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX8-NEXT: s_mov_b64 exec, s[4:5] +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GFX8-NEXT: ; implicit-def: $vgpr0 +; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX8-NEXT: ; mask branch BB23_2 +; GFX8-NEXT: s_cbranch_execz BB23_2 +; GFX8-NEXT: BB23_1: +; GFX8-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v3, s2 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_min_rtn_u32 v0, v0, v3 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB23_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX8-NEXT: v_readfirstlane_b32 s2, v0 +; GFX8-NEXT: v_mov_b32_e32 v0, v1 +; GFX8-NEXT: v_min_u32_e32 v0, s2, v0 +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: s_nop 0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: umin_i32_varying: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v3, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v3, s3, v3 +; GFX9-NEXT: v_mov_b32_e32 v2, v0 +; GFX9-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX9-NEXT: v_mov_b32_e32 v1, -1 +; GFX9-NEXT: s_mov_b64 exec, s[2:3] +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: v_mov_b32_e32 v2, -1 +; GFX9-NEXT: s_not_b64 exec, exec +; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX9-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_min_u32_dpp v2, v2, v2 row_bcast:15 row_mask:0xa bank_mask:0xf +; GFX9-NEXT: s_nop 1 +; GFX9-NEXT: v_min_u32_dpp v2, v2, v2 row_bcast:31 row_mask:0xc bank_mask:0xf +; GFX9-NEXT: v_readlane_b32 s2, v2, 63 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: v_mov_b32_dpp v1, v2 wave_shr:1 row_mask:0xf bank_mask:0xf +; GFX9-NEXT: s_mov_b64 exec, s[4:5] +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 +; GFX9-NEXT: ; implicit-def: $vgpr0 +; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX9-NEXT: ; mask branch BB23_2 +; GFX9-NEXT: s_cbranch_execz BB23_2 +; GFX9-NEXT: BB23_1: +; GFX9-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v3, s2 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_min_rtn_u32 v0, v0, v3 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB23_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX9-NEXT: v_readfirstlane_b32 s2, v0 +; GFX9-NEXT: v_mov_b32_e32 v0, v1 +; GFX9-NEXT: v_min_u32_e32 v0, s2, v0 +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: s_nop 0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: umin_i32_varying: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: v_mov_b32_e32 v2, v0 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v4, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v4, s3, v4 +; GFX1064-NEXT: s_or_saveexec_b64 s[2:3], -1 +; GFX1064-NEXT: v_mov_b32_e32 v1, -1 +; GFX1064-NEXT: s_mov_b64 exec, s[2:3] +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: v_mov_b32_e32 v2, -1 +; GFX1064-NEXT: s_not_b64 exec, exec +; GFX1064-NEXT: s_or_saveexec_b64 s[4:5], -1 +; GFX1064-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_mov_b32_e32 v3, v2 +; GFX1064-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1064-NEXT: v_min_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 31 +; GFX1064-NEXT: v_mov_b32_e32 v3, s2 +; GFX1064-NEXT: v_min_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s2, v2, 15 +; GFX1064-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1064-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1064-NEXT: v_readlane_b32 s6, v2, 47 +; GFX1064-NEXT: v_writelane_b32 v1, s2, 16 +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: v_writelane_b32 v1, s3, 32 +; GFX1064-NEXT: v_readlane_b32 s3, v2, 63 +; GFX1064-NEXT: v_writelane_b32 v1, s6, 48 +; GFX1064-NEXT: s_mov_b64 exec, s[4:5] +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v4 +; GFX1064-NEXT: ; implicit-def: $vgpr0 +; GFX1064-NEXT: s_and_saveexec_b64 s[4:5], vcc +; GFX1064-NEXT: ; mask branch BB23_2 +; GFX1064-NEXT: s_cbranch_execz BB23_2 +; GFX1064-NEXT: BB23_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v7, s3 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_min_rtn_u32 v0, v0, v7 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB23_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5] +; GFX1064-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1064-NEXT: v_mov_b32_e32 v0, v1 +; GFX1064-NEXT: v_min_u32_e32 v0, s3, v0 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: s_nop 1 +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: umin_i32_varying: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mov_b32_e32 v2, v0 +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v4, s2, 0 +; GFX1032-NEXT: s_or_saveexec_b32 s2, -1 +; GFX1032-NEXT: v_mov_b32_e32 v1, -1 +; GFX1032-NEXT: s_mov_b32 exec_lo, s2 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: v_mov_b32_e32 v2, -1 +; GFX1032-NEXT: s_not_b32 exec_lo, exec_lo +; GFX1032-NEXT: s_or_saveexec_b32 s4, -1 +; GFX1032-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:2 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:4 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_min_u32_dpp v2, v2, v2 row_shr:8 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_mov_b32_e32 v3, v2 +; GFX1032-NEXT: v_permlanex16_b32 v3, v3, -1, -1 +; GFX1032-NEXT: v_min_u32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s3, v2, 31 +; GFX1032-NEXT: v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf +; GFX1032-NEXT: v_readlane_b32 s5, v2, 15 +; GFX1032-NEXT: v_writelane_b32 v1, s5, 16 +; GFX1032-NEXT: s_mov_b32 exec_lo, s4 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v4 +; GFX1032-NEXT: ; implicit-def: $vgpr0 +; GFX1032-NEXT: s_and_saveexec_b32 s4, vcc_lo +; GFX1032-NEXT: ; mask branch BB23_2 +; GFX1032-NEXT: s_cbranch_execz BB23_2 +; GFX1032-NEXT: BB23_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, local_var32@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v7, s3 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_min_rtn_u32 v0, v0, v7 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB23_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s4 +; GFX1032-NEXT: v_readfirstlane_b32 s3, v0 +; GFX1032-NEXT: v_mov_b32_e32 v0, v1 +; GFX1032-NEXT: v_min_u32_e32 v0, s3, v0 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: s_nop 1 +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %lane = call i32 @llvm.amdgcn.workitem.id.x() %old = atomicrmw umin i32 addrspace(3)* @local_var32, i32 %lane acq_rel @@ -497,16 +5005,192 @@ entry: ret void } -; GCN-LABEL: umin_i64_constant: -; GCN32: v_cmp_ne_u32_e64 s[[exec_lo:[0-9]+]], 1, 0 -; GCN64: v_cmp_ne_u32_e64 s{{\[}}[[exec_lo:[0-9]+]]:[[exec_hi:[0-9]+]]{{\]}}, 1, 0 -; GCN: v_mbcnt_lo_u32_b32{{(_e[0-9]+)?}} v[[mbcnt:[0-9]+]], s[[exec_lo]], 0 -; GCN64: v_mbcnt_hi_u32_b32{{(_e[0-9]+)?}} v[[mbcnt]], s[[exec_hi]], v[[mbcnt]] -; GCN: v_cmp_eq_u32{{(_e[0-9]+)?}} vcc{{(_lo)?}}, 0, v[[mbcnt]] -; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_lo:[0-9]+]], 5 -; GCN: v_mov_b32{{(_e[0-9]+)?}} v[[value_hi:[0-9]+]], 0 -; GCN: ds_min_rtn_u64 v{{\[}}{{[0-9]+}}:{{[0-9]+}}{{\]}}, v{{[0-9]+}}, v{{\[}}[[value_lo]]:[[value_hi]]{{\]}} define amdgpu_kernel void @umin_i64_constant(i64 addrspace(1)* %out) { +; +; +; GFX7LESS-LABEL: umin_i64_constant: +; GFX7LESS: ; %bb.0: ; %entry +; GFX7LESS-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 +; GFX7LESS-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX7LESS-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX7LESS-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0 +; GFX7LESS-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX7LESS-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX7LESS-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX7LESS-NEXT: ; mask branch BB24_2 +; GFX7LESS-NEXT: s_cbranch_execz BB24_2 +; GFX7LESS-NEXT: BB24_1: +; GFX7LESS-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX7LESS-NEXT: v_mov_b32_e32 v0, 5 +; GFX7LESS-NEXT: v_mov_b32_e32 v1, 0 +; GFX7LESS-NEXT: s_mov_b32 m0, -1 +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] +; GFX7LESS-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX7LESS-NEXT: buffer_wbinvl1 +; GFX7LESS-NEXT: BB24_2: +; GFX7LESS-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX7LESS-NEXT: v_readfirstlane_b32 s4, v0 +; GFX7LESS-NEXT: v_readfirstlane_b32 s5, v1 +; GFX7LESS-NEXT: s_mov_b32 s2, -1 +; GFX7LESS-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX7LESS-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s5 +; GFX7LESS-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1] +; GFX7LESS-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX7LESS-NEXT: v_mov_b32_e32 v2, s4 +; GFX7LESS-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX7LESS-NEXT: s_mov_b32 s3, 0xf000 +; GFX7LESS-NEXT: s_waitcnt lgkmcnt(0) +; GFX7LESS-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX7LESS-NEXT: s_endpgm +; +; GFX8-LABEL: umin_i64_constant: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX8-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX8-NEXT: ; mask branch BB24_2 +; GFX8-NEXT: s_cbranch_execz BB24_2 +; GFX8-NEXT: BB24_1: +; GFX8-NEXT: v_mov_b32_e32 v0, 5 +; GFX8-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX8-NEXT: v_mov_b32_e32 v1, 0 +; GFX8-NEXT: s_mov_b32 m0, -1 +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX8-NEXT: buffer_wbinvl1_vol +; GFX8-NEXT: BB24_2: +; GFX8-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX8-NEXT: v_readfirstlane_b32 s5, v1 +; GFX8-NEXT: v_readfirstlane_b32 s4, v0 +; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX8-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v2, s5 +; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX8-NEXT: v_mov_b32_e32 v2, s4 +; GFX8-NEXT: s_mov_b32 s2, -1 +; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX8-NEXT: s_mov_b32 s3, 0xf000 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX8-NEXT: s_endpgm +; +; GFX9-LABEL: umin_i64_constant: +; GFX9: ; %bb.0: ; %entry +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX9-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0 +; GFX9-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0 +; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX9-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX9-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX9-NEXT: ; mask branch BB24_2 +; GFX9-NEXT: s_cbranch_execz BB24_2 +; GFX9-NEXT: BB24_1: +; GFX9-NEXT: v_mov_b32_e32 v0, 5 +; GFX9-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX9-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-NEXT: buffer_wbinvl1_vol +; GFX9-NEXT: BB24_2: +; GFX9-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX9-NEXT: v_readfirstlane_b32 s5, v1 +; GFX9-NEXT: v_readfirstlane_b32 s4, v0 +; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX9-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1] +; GFX9-NEXT: v_mov_b32_e32 v2, s5 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX9-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-NEXT: s_mov_b32 s2, -1 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; GFX9-NEXT: s_mov_b32 s3, 0xf000 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX9-NEXT: s_endpgm +; +; GFX1064-LABEL: umin_i64_constant: +; GFX1064: ; %bb.0: ; %entry +; GFX1064-NEXT: v_cmp_ne_u32_e64 s[2:3], 1, 0 +; GFX1064-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1064-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1064-NEXT: v_mbcnt_hi_u32_b32_e64 v0, s3, v0 +; GFX1064-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 +; GFX1064-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1064-NEXT: s_and_saveexec_b64 s[2:3], vcc +; GFX1064-NEXT: ; mask branch BB24_2 +; GFX1064-NEXT: s_cbranch_execz BB24_2 +; GFX1064-NEXT: BB24_1: +; GFX1064-NEXT: v_mov_b32_e32 v0, 5 +; GFX1064-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1064-NEXT: v_mov_b32_e32 v1, 0 +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1064-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] +; GFX1064-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1064-NEXT: buffer_gl0_inv +; GFX1064-NEXT: buffer_gl1_inv +; GFX1064-NEXT: BB24_2: +; GFX1064-NEXT: v_nop +; GFX1064-NEXT: s_or_b64 exec, exec, s[2:3] +; GFX1064-NEXT: v_readfirstlane_b32 s4, v0 +; GFX1064-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1064-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc +; GFX1064-NEXT: s_mov_b32 s2, -1 +; GFX1064-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1064-NEXT: v_cmp_lt_u64_e32 vcc, s[4:5], v[0:1] +; GFX1064-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc +; GFX1064-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc +; GFX1064-NEXT: s_waitcnt lgkmcnt(0) +; GFX1064-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1064-NEXT: s_endpgm +; +; GFX1032-LABEL: umin_i64_constant: +; GFX1032: ; %bb.0: ; %entry +; GFX1032-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX1032-NEXT: v_cmp_ne_u32_e64 s2, 1, 0 +; GFX1032-NEXT: ; implicit-def: $vcc_hi +; GFX1032-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0 +; GFX1032-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 +; GFX1032-NEXT: ; implicit-def: $vgpr0_vgpr1 +; GFX1032-NEXT: s_and_saveexec_b32 s2, vcc_lo +; GFX1032-NEXT: ; mask branch BB24_2 +; GFX1032-NEXT: s_cbranch_execz BB24_2 +; GFX1032-NEXT: BB24_1: +; GFX1032-NEXT: v_mov_b32_e32 v0, 5 +; GFX1032-NEXT: v_mov_b32_e32 v2, local_var64@abs32@lo +; GFX1032-NEXT: v_mov_b32_e32 v1, 0 +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX1032-NEXT: ds_min_rtn_u64 v[0:1], v2, v[0:1] +; GFX1032-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX1032-NEXT: buffer_gl0_inv +; GFX1032-NEXT: buffer_gl1_inv +; GFX1032-NEXT: BB24_2: +; GFX1032-NEXT: v_nop +; GFX1032-NEXT: s_or_b32 exec_lo, exec_lo, s2 +; GFX1032-NEXT: v_readfirstlane_b32 s4, v0 +; GFX1032-NEXT: v_readfirstlane_b32 s5, v1 +; GFX1032-NEXT: v_cndmask_b32_e64 v1, 0, -1, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v0, 5, -1, vcc_lo +; GFX1032-NEXT: s_mov_b32 s2, -1 +; GFX1032-NEXT: s_mov_b32 s3, 0x31016000 +; GFX1032-NEXT: v_cmp_lt_u64_e32 vcc_lo, s[4:5], v[0:1] +; GFX1032-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo +; GFX1032-NEXT: v_cndmask_b32_e64 v0, v0, s4, vcc_lo +; GFX1032-NEXT: s_waitcnt lgkmcnt(0) +; GFX1032-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GFX1032-NEXT: s_endpgm entry: %old = atomicrmw umin i64 addrspace(3)* @local_var64, i64 5 acq_rel store i64 %old, i64 addrspace(1)* %out diff --git a/llvm/test/CodeGen/AMDGPU/dpp_combine.ll b/llvm/test/CodeGen/AMDGPU/dpp_combine.ll new file mode 100644 index 00000000000..2afc5388872 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/dpp_combine.ll @@ -0,0 +1,53 @@ +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN +; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefix=GCN + +; GCN-LABEL: {{^}}dpp_add: +; GCN: global_load_dword [[V:v[0-9]+]], +; GCN: v_add_{{(nc_)?}}u32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}} +define amdgpu_kernel void @dpp_add(i32 addrspace(1)* %arg) { + %id = tail call i32 @llvm.amdgcn.workitem.id.x() + %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id + %load = load i32, i32 addrspace(1)* %gep + %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0 + %add = add i32 %tmp0, %load + store i32 %add, i32 addrspace(1)* %gep + ret void +} + +; GCN-LABEL: {{^}}dpp_ceil: +; GCN: global_load_dword [[V:v[0-9]+]], +; GCN: v_ceil_f32_dpp [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}} +define amdgpu_kernel void @dpp_ceil(i32 addrspace(1)* %arg) { + %id = tail call i32 @llvm.amdgcn.workitem.id.x() + %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id + %load = load i32, i32 addrspace(1)* %gep + %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0 + %tmp1 = bitcast i32 %tmp0 to float + %round = tail call float @llvm.ceil.f32(float %tmp1) + %tmp2 = bitcast float %round to i32 + store i32 %tmp2, i32 addrspace(1)* %gep + ret void +} + +; GCN-LABEL: {{^}}dpp_fadd: +; GCN: global_load_dword [[V:v[0-9]+]], +; GCN: v_add_f32_dpp [[V]], [[V]], [[V]] quad_perm:[1,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}} +define amdgpu_kernel void @dpp_fadd(i32 addrspace(1)* %arg) { + %id = tail call i32 @llvm.amdgcn.workitem.id.x() + %gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i32 %id + %load = load i32, i32 addrspace(1)* %gep + %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %load, i32 %load, i32 1, i32 15, i32 15, i1 1) #0 + %tmp1 = bitcast i32 %tmp0 to float + %t = bitcast i32 %load to float + %add = fadd float %tmp1, %t + %tmp2 = bitcast float %add to i32 + store i32 %tmp2, i32 addrspace(1)* %gep + ret void +} + + +declare i32 @llvm.amdgcn.workitem.id.x() +declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0 +declare float @llvm.ceil.f32(float) + +attributes #0 = { nounwind readnone convergent } |
