diff options
Diffstat (limited to 'llvm/test')
103 files changed, 132 insertions, 131 deletions
diff --git a/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll b/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll index 9df178f9907..badab1686fc 100644 --- a/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll +++ b/llvm/test/CodeGen/Hexagon/SUnit-boundary-prob.ll @@ -187,7 +187,7 @@ entry: } attributes #0 = { nounwind readnone } -attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #2 = { nounwind } !llvm.module.flags = !{!0} diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll index 87d535fd0f2..30d18b7724e 100644 --- a/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll +++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit-at.ll @@ -30,4 +30,4 @@ b9: ; preds = %b6, %b4 ret i32 %v10 } -attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind optsize "target-cpu"="hexagonv60" "target-features"="-hvxv60,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll index 2d1c71c709f..edac4cb34b6 100644 --- a/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll +++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit-src.ll @@ -32,4 +32,4 @@ b0: ; Function Attrs: nounwind declare void @printf(i8* nocapture readonly, ...) local_unnamed_addr #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll b/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll index 4ae2e4e6650..52ae69af994 100644 --- a/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll +++ b/llvm/test/CodeGen/Hexagon/bit-bitsplit.ll @@ -14,4 +14,4 @@ entry: ret i32 %and2 } -attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } +attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx" } diff --git a/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll b/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll index 47c49c2364b..713e3988457 100644 --- a/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll +++ b/llvm/test/CodeGen/Hexagon/bit-ext-sat.ll @@ -53,5 +53,5 @@ declare i32 @llvm.hexagon.A2.sath(i32) #1 declare i32 @llvm.hexagon.A2.satub(i32) #1 declare i32 @llvm.hexagon.A2.satuh(i32) #1 -attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll index 183435ab7b2..4086ca34bbb 100644 --- a/llvm/test/CodeGen/Hexagon/bit-extract-off.ll +++ b/llvm/test/CodeGen/Hexagon/bit-extract-off.ll @@ -19,5 +19,5 @@ b5: ; preds = %b5, %b4 declare double @fabs(double) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/bit-extract.ll b/llvm/test/CodeGen/Hexagon/bit-extract.ll index ad7d05d2c23..33fa50c14f3 100644 --- a/llvm/test/CodeGen/Hexagon/bit-extract.ll +++ b/llvm/test/CodeGen/Hexagon/bit-extract.ll @@ -72,4 +72,4 @@ entry: ret i32 %bf.ashr } -attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { noinline norecurse nounwind readnone "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/bit-has.ll b/llvm/test/CodeGen/Hexagon/bit-has.ll index 9022de39186..5bb0f2f60b0 100644 --- a/llvm/test/CodeGen/Hexagon/bit-has.ll +++ b/llvm/test/CodeGen/Hexagon/bit-has.ll @@ -60,5 +60,5 @@ b23: ; preds = %b21 declare i32 @llvm.hexagon.A2.sath(i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll b/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll index db57998aeb6..e7dd87c1da1 100644 --- a/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll +++ b/llvm/test/CodeGen/Hexagon/bit-loop-rc-mismatch.ll @@ -24,7 +24,7 @@ for.end: ; preds = %for.body, %entry declare hidden i64 @danny(i32*, i32* nocapture readonly dereferenceable(4)) #1 align 2 declare hidden i32 @sammy(i32* nocapture, i32) #0 align 2 -attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind optsize "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind optsize readonly "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { optsize } diff --git a/llvm/test/CodeGen/Hexagon/bit-rie.ll b/llvm/test/CodeGen/Hexagon/bit-rie.ll index 302382a1ade..a090a668d9f 100644 --- a/llvm/test/CodeGen/Hexagon/bit-rie.ll +++ b/llvm/test/CodeGen/Hexagon/bit-rie.ll @@ -190,7 +190,7 @@ declare i64 @llvm.hexagon.M2.mpyd.ll.s1(i32, i32) #2 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } attributes #2 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll b/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll index c090721b8ff..a89a15c22d2 100644 --- a/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll +++ b/llvm/test/CodeGen/Hexagon/bitconvert-vector.ll @@ -24,4 +24,4 @@ entry: attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll b/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll index 1d06953ddf3..7efc38f15b3 100644 --- a/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll +++ b/llvm/test/CodeGen/Hexagon/build-vector-shuffle.ll @@ -17,5 +17,5 @@ entry: ; Function Attrs: nounwind readnone declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/builtin-expect.ll b/llvm/test/CodeGen/Hexagon/builtin-expect.ll index 9945da1782b..9fed28760ad 100644 --- a/llvm/test/CodeGen/Hexagon/builtin-expect.ll +++ b/llvm/test/CodeGen/Hexagon/builtin-expect.ll @@ -39,6 +39,6 @@ b14: ; preds = %b13, %b10 declare i32 @bar(i32) local_unnamed_addr #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b,-long-calls" } !0 = !{!"branch_weights", i32 1, i32 2000} diff --git a/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll b/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll index be234aafc0b..2d65a5c5848 100644 --- a/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll +++ b/llvm/test/CodeGen/Hexagon/cfgopt-fall-through.ll @@ -68,4 +68,4 @@ b19: ; preds = %b4 unreachable } -attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/cfi-offset.ll b/llvm/test/CodeGen/Hexagon/cfi-offset.ll index 100034a0c6c..c7d447d168c 100644 --- a/llvm/test/CodeGen/Hexagon/cfi-offset.ll +++ b/llvm/test/CodeGen/Hexagon/cfi-offset.ll @@ -39,5 +39,5 @@ declare i8* @__cxa_begin_catch(i8*) declare void @__cxa_end_catch() -attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll b/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll index a8b75725a0b..ddc73c284bc 100644 --- a/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll +++ b/llvm/test/CodeGen/Hexagon/common-gep-inbounds.ll @@ -17,4 +17,4 @@ entry: ret i16 %a } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll index 9a4569b1e4d..e67892537ef 100644 --- a/llvm/test/CodeGen/Hexagon/const-pool-tf.ll +++ b/llvm/test/CodeGen/Hexagon/const-pool-tf.ll @@ -1,6 +1,6 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic < %s | FileCheck %s +; RUN: opt -relocation-model pic -march=hexagon -mcpu=hexagonv60 -O2 -S < %s | llc -march=hexagon -mcpu=hexagonv60 -relocation-model pic -; CHECK: @PCREL +; CHECK: jumpr target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048" target triple = "hexagon-unknown--elf" diff --git a/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll b/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll index b793fa0c22c..c4e67f3db61 100644 --- a/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll +++ b/llvm/test/CodeGen/Hexagon/convert-to-dot-old.ll @@ -103,8 +103,8 @@ declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2 declare i32 @llvm.hexagon.A2.aslh(i32) #2 declare void @foo(i16*, i32*, i16*, i16 signext, i16 signext, i16 signext) local_unnamed_addr #3 -attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } attributes #1 = { argmemonly nounwind } attributes #2 = { nounwind readnone } -attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #3 = { optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } attributes #4 = { nounwind optsize } diff --git a/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll b/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll index 35c12f1d88b..62beeee19ff 100644 --- a/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll +++ b/llvm/test/CodeGen/Hexagon/convert_const_i1_to_i8.ll @@ -14,4 +14,4 @@ entry: declare <32 x i32> @llvm.hexagon.V6.vrdelta.128B(<32 x i32>, <32 x i32>) declare <32 x i32> @llvm.hexagon.V6.vmux.128B(<1024 x i1>, <32 x i32>, <32 x i32>) -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/dead-store-stack.ll b/llvm/test/CodeGen/Hexagon/dead-store-stack.ll index 0d8124e76b9..532c2b2ee8c 100644 --- a/llvm/test/CodeGen/Hexagon/dead-store-stack.ll +++ b/llvm/test/CodeGen/Hexagon/dead-store-stack.ll @@ -1,4 +1,4 @@ -; RUN: llc -O2 -march=hexagon < %s | FileCheck %s +; RUN: llc -O2 -march=hexagon -mcpu=hexagonv62< %s | FileCheck %s ; CHECK: ParseFunc: ; CHECK: r[[ARG0:[0-9]+]] = memuh(r[[ARG1:[0-9]+]]+#[[OFFSET:[0-9]+]]) ; CHECK: memw(r[[ARG1]]+#[[OFFSET]]) = r[[ARG0]] @@ -126,6 +126,7 @@ sw.epilog: ; Function Attrs: nounwind declare void @snprintf(i8* nocapture, i32, i8* nocapture readonly, ...) local_unnamed_addr #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv62" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind } + diff --git a/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll b/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll index f45058f029d..ab8b00d6c90 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-merge-loop.ll @@ -82,7 +82,7 @@ declare i64 @llvm.hexagon.A2.addp(i64, i64) #1 declare i64 @llvm.hexagon.A2.subp(i64, i64) #1 declare i64 @llvm.hexagon.A2.combinew(i32, i32) #1 -attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } attributes #1 = { nounwind readnone } !0 = !{!1, !1, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll b/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll index 6f3ec2d5a51..6fd2aa13480 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-vecpi.ll @@ -66,4 +66,4 @@ for.end: ; preds = %if.end ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } diff --git a/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll b/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll index ca119e1d1de..05074338cff 100644 --- a/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll +++ b/llvm/test/CodeGen/Hexagon/early-if-vecpred.ll @@ -31,7 +31,7 @@ b5: ; preds = %b3, %b1 declare <1024 x i1> @llvm.hexagon.V6.pred.scalar2.128B(i32) #1 declare <1024 x i1> @llvm.hexagon.V6.pred.not.128B(<1024 x i1>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll index b3a4a2f4252..4c93ab201e3 100644 --- a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll +++ b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll @@ -139,5 +139,5 @@ declare <64 x i32> @llvm.hexagon.V6.vmpyuh.acc.128B(<64 x i32>, <32 x i32>, i32) declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll index ce7f5e0ce12..350b0edec85 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-bad.ll @@ -51,4 +51,4 @@ b23: ; preds = %b0 ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll index ecec83625e1..dbcba1aa7d0 100644 --- a/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll +++ b/llvm/test/CodeGen/Hexagon/expand-condsets-dead-pred.ll @@ -42,4 +42,4 @@ b20: ; preds = %b2 br label %b1 } -attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll b/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll index 1d07859665c..a5769dbddd6 100644 --- a/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll +++ b/llvm/test/CodeGen/Hexagon/expand-vselect-kill.ll @@ -48,6 +48,6 @@ declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #2 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #2 declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #2 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #2 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll index 8524bf33de1..88eaec938fd 100644 --- a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll +++ b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef.ll @@ -91,5 +91,5 @@ b22: ; preds = %b22, %b18 attributes #0 = { nounwind } attributes #1 = { nounwind readnone } -attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #2 = { nounwind "reciprocal-estimates"="none" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #3 = { nobuiltin nounwind } diff --git a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll index 4f2bb86f084..641d53c8783 100644 --- a/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll +++ b/llvm/test/CodeGen/Hexagon/expand-vstorerw-undef2.ll @@ -210,7 +210,7 @@ b34: ; preds = %b34, %b24 br i1 %v146, label %b33, label %b34 } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } attributes #3 = { nobuiltin nounwind } diff --git a/llvm/test/CodeGen/Hexagon/find-loop-instr.ll b/llvm/test/CodeGen/Hexagon/find-loop-instr.ll index 1234baf17f5..b9743ad33aa 100644 --- a/llvm/test/CodeGen/Hexagon/find-loop-instr.ll +++ b/llvm/test/CodeGen/Hexagon/find-loop-instr.ll @@ -76,4 +76,4 @@ b21: ; preds = %b20, %b19, %b16, %b br i1 %v23, label %b13, label %b10 } -attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { norecurse "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/fminmax.ll b/llvm/test/CodeGen/Hexagon/fminmax.ll index 7c1a9fb42f2..cf1dc6cdf61 100644 --- a/llvm/test/CodeGen/Hexagon/fminmax.ll +++ b/llvm/test/CodeGen/Hexagon/fminmax.ll @@ -22,6 +22,6 @@ entry: declare float @fminf(float, float) #0 declare float @fmaxf(float, float) #0 -attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll b/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll index 43d5fd5ad0f..88d4e287fc0 100644 --- a/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll +++ b/llvm/test/CodeGen/Hexagon/frame-offset-overflow.ll @@ -156,7 +156,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmpahb.acc(<32 x i32>, <32 x i32>, i32) #0 declare <32 x i32> @llvm.hexagon.V6.vmpyhsat.acc(<32 x i32>, <16 x i32>, i32) #0 attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !1 = !{!2, !2, i64 0} !2 = !{!"omnipotent char", !3, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll b/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll index 1154a7117a7..f96eafe1502 100644 --- a/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll +++ b/llvm/test/CodeGen/Hexagon/hasfp-crash1.ll @@ -18,7 +18,7 @@ entry: ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" } attributes #1 = { nounwind readnone speculatable } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll b/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll index c8b49948ce7..c454a9fcd9b 100644 --- a/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll +++ b/llvm/test/CodeGen/Hexagon/hasfp-crash2.ll @@ -19,7 +19,7 @@ entry: ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { nounwind "disable-tail-calls"="true" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"=",-hvx,-long-calls" } attributes #1 = { nounwind readnone speculatable } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll index 1719003bb80..ca1ba2fe1a2 100644 --- a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll +++ b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse.ll @@ -73,7 +73,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32>, <32 x i32>) #1 ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll index 3808364d41a..8fb62b3fa5a 100644 --- a/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll +++ b/llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_constant.ll @@ -73,7 +73,7 @@ declare <32 x i32> @llvm.hexagon.V6.vmaxub.128B(<32 x i32>, <32 x i32>) #1 ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll b/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll index 98c5ef4809b..38e597df1ba 100644 --- a/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll +++ b/llvm/test/CodeGen/Hexagon/hvx-nontemporal.ll @@ -20,7 +20,7 @@ entry: ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } !1 = !{!2, !2, i64 0} !2 = !{!"omnipotent char", !3, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll b/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll index 1045e2ed80a..accf6fd83c6 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-noreturn-call.ll @@ -58,6 +58,6 @@ noret: declare void @trap() #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } attributes #1 = { nounwind noreturn } diff --git a/llvm/test/CodeGen/Hexagon/hwloop-preh.ll b/llvm/test/CodeGen/Hexagon/hwloop-preh.ll index e92461f43da..fb7e7684866 100644 --- a/llvm/test/CodeGen/Hexagon/hwloop-preh.ll +++ b/llvm/test/CodeGen/Hexagon/hwloop-preh.ll @@ -41,4 +41,4 @@ return: ; preds = %return.loopexit, %f !1 = !{!"omnipotent char", !2} !2 = !{!"Simple C/C++ TBAA"} -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx" } diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll index 25634217031..d540c09c1dd 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-qv.ll @@ -15,5 +15,5 @@ entry: ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll b/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll index 234f5a0b792..7d2f50ed58a 100644 --- a/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll +++ b/llvm/test/CodeGen/Hexagon/inline-asm-vecpred128.ll @@ -12,4 +12,4 @@ define void @fred() #0 { ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll index 2a54bfef0ad..3b853ebb444 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store-double.ll @@ -1,4 +1,4 @@ -; RUN: llc -mattr=+hvx-double -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mattr=+hvxv60,hvx-length128b -march=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vmaskedstoreq_128B ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll index 208c15fec98..5ff67222452 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/byte-store.ll @@ -1,4 +1,4 @@ -; RUN: llc -mattr=+hvx -march=hexagon -O2 < %s | FileCheck %s +; RUN: llc -mattr=+hvxv60,hvx-length64b -march=hexagon -O2 < %s | FileCheck %s ; CHECK-LABEL: V6_vmaskedstoreq ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}} diff --git a/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll b/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll index 23473c92da9..1a5fd138e0f 100644 --- a/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll +++ b/llvm/test/CodeGen/Hexagon/intrinsics/system_user.ll @@ -65,7 +65,7 @@ declare void @llvm.hexagon.Y2.dczeroa(i8* nocapture) #3 declare void @llvm.hexagon.Y4.l2fetch(i8* nocapture readonly, i32) #2 declare void @llvm.hexagon.Y5.l2fetch(i8* nocapture readonly, i64) #2 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } attributes #1 = { inaccessiblemem_or_argmemonly nounwind } attributes #2 = { nounwind } attributes #3 = { argmemonly nounwind writeonly } diff --git a/llvm/test/CodeGen/Hexagon/jt-in-text.ll b/llvm/test/CodeGen/Hexagon/jt-in-text.ll index 62b5caef6aa..7389c960b9e 100644 --- a/llvm/test/CodeGen/Hexagon/jt-in-text.ll +++ b/llvm/test/CodeGen/Hexagon/jt-in-text.ll @@ -54,4 +54,4 @@ sw.epilog: ; preds = %entry, %sw.bb4, %sw ret void } -attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll index f738282c0f1..92f3b6048bf 100644 --- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll +++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-infinite-loop.ll @@ -80,4 +80,4 @@ if.end437: ; preds = %if.then409, %for.bo br label %for.body405 } -attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" } +attributes #0 = { noinline nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll index 9907ae71c99..3e1e39b9d09 100644 --- a/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll +++ b/llvm/test/CodeGen/Hexagon/loop-idiom/pmpy-mod.ll @@ -81,4 +81,4 @@ b46: ; preds = %b3 ret i16 %v5 } -attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { noinline nounwind "target-cpu"="hexagonv5" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/loop-prefetch.ll b/llvm/test/CodeGen/Hexagon/loop-prefetch.ll index 0c6e4581a71..24518421c44 100644 --- a/llvm/test/CodeGen/Hexagon/loop-prefetch.ll +++ b/llvm/test/CodeGen/Hexagon/loop-prefetch.ll @@ -24,4 +24,4 @@ while.end: ; preds = %while.body, %entry ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx" } diff --git a/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll b/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll index ba67de9e00a..09ca465c671 100644 --- a/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll +++ b/llvm/test/CodeGen/Hexagon/lower-extract-subvector.ll @@ -43,5 +43,5 @@ if.then.i164: ; preds = %"consume denoised" ; Function Attrs: nounwind readnone declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/memops-stack.ll b/llvm/test/CodeGen/Hexagon/memops-stack.ll index 1aa2e30ea25..9da319f443b 100644 --- a/llvm/test/CodeGen/Hexagon/memops-stack.ll +++ b/llvm/test/CodeGen/Hexagon/memops-stack.ll @@ -136,9 +136,9 @@ declare void @foo(i32*) #2 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } -attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #3 = { nounwind } !1 = !{!2, !2, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll b/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll index 25cb14e8514..c1472824074 100644 --- a/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll +++ b/llvm/test/CodeGen/Hexagon/misaligned_double_vector_store_not_fast.ll @@ -42,6 +42,6 @@ entry: declare <64 x i32> @llvm.hexagon.V6.vshuffvdd.128B(<32 x i32>, <32 x i32>, i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/multi-cycle.ll b/llvm/test/CodeGen/Hexagon/multi-cycle.ll index fc021821af3..b8caef90397 100644 --- a/llvm/test/CodeGen/Hexagon/multi-cycle.ll +++ b/llvm/test/CodeGen/Hexagon/multi-cycle.ll @@ -95,7 +95,7 @@ declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.vabsdiffh(<16 x i32>, <16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vabsh(<16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } !1 = !{!2, !2, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/newify-crash.ll b/llvm/test/CodeGen/Hexagon/newify-crash.ll index 705170b13a5..bb299542912 100644 --- a/llvm/test/CodeGen/Hexagon/newify-crash.ll +++ b/llvm/test/CodeGen/Hexagon/newify-crash.ll @@ -40,5 +40,5 @@ b18: ; preds = %b7 declare <32 x i32> @llvm.hexagon.V6.vaddhsat.128B(<32 x i32>, <32 x i32>) #1 declare void @f0() #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/newvaluejump3.ll b/llvm/test/CodeGen/Hexagon/newvaluejump3.ll index 1e2e6c28c84..93479666ad5 100644 --- a/llvm/test/CodeGen/Hexagon/newvaluejump3.ll +++ b/llvm/test/CodeGen/Hexagon/newvaluejump3.ll @@ -74,6 +74,6 @@ b24: ; preds = %b20, %b16, %b9, %b2 } attributes #0 = { argmemonly nounwind } -attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } -attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double,-long-calls" } +attributes #1 = { nounwind readonly "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" } +attributes #2 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll b/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll index 03de1532352..4a24ea62af4 100644 --- a/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll +++ b/llvm/test/CodeGen/Hexagon/peephole-kill-flags.ll @@ -23,5 +23,5 @@ for.end13: ; preds = %for.cond ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } diff --git a/llvm/test/CodeGen/Hexagon/plt-rel.ll b/llvm/test/CodeGen/Hexagon/plt-rel.ll index 1d38cf32b88..d1d97a62263 100644 --- a/llvm/test/CodeGen/Hexagon/plt-rel.ll +++ b/llvm/test/CodeGen/Hexagon/plt-rel.ll @@ -34,4 +34,4 @@ return: ; preds = %entry, %if.then ret i1 %.sink } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } diff --git a/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll b/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll index fb2f038e6e5..673a9b41ff2 100644 --- a/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll +++ b/llvm/test/CodeGen/Hexagon/post-inc-aa-metadata.ll @@ -29,7 +29,7 @@ while.end: ; preds = %while.body, %entry ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } !1 = !{!2, !2, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll b/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll index 4948a89b73e..989322a0fea 100644 --- a/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll +++ b/llvm/test/CodeGen/Hexagon/propagate-vcombine.ll @@ -42,7 +42,7 @@ declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #3 declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #3 declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #3 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } -attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx" } -attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } +attributes #2 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #3 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll b/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll index 3d65968911e..91aec7750db 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-def-mask.ll @@ -48,5 +48,5 @@ declare i32 @llvm.hexagon.S2.clb(i32) #1 declare i32 @llvm.hexagon.S2.asl.r.r(i32, i32) #1 declare i32 @llvm.hexagon.M2.mpyu.nac.ll.s0(i32, i32, i32) #1 -attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { nounwind readnone "target-cpu"="hexagonv55" "target-features"="-hvx,-long-calls" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll index 222d8a2b2e1..d06da934678 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm-fixed.ll @@ -26,7 +26,7 @@ declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 ; Function Attrs: argmemonly nounwind declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv5" "target-features"="-hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll b/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll index ae09062638d..2661f8c0d0d 100644 --- a/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll +++ b/llvm/test/CodeGen/Hexagon/rdf-inline-asm.ll @@ -24,7 +24,7 @@ if.end: ; preds = %if.then, %entry ret i32 %retval1.0 } -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } !1 = !{i32 155} diff --git a/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll b/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll index db9ed55d2da..c73d4c7bc01 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scavengebug-3.ll @@ -1,4 +1,4 @@ -; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 < %s | FileCheck %s +; RUN: llc -O0 -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vmem diff --git a/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll b/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll index 78c4b989b7a..bc878e09ef9 100644 --- a/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll +++ b/llvm/test/CodeGen/Hexagon/reg-scavenger-valid-slot.ll @@ -95,6 +95,6 @@ entry: ret void } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir index a541e766f59..7e18011a523 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir +++ b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir @@ -58,7 +58,7 @@ declare i32 @lrand48() #0 declare i64 @llvm.hexagon.S2.extractup(i64, i32, i32) #1 - attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx,-hvx-double" } + attributes #0 = { nounwind optsize "target-cpu"="hexagonv55" "target-features"="-hvx" } attributes #1 = { nounwind readnone } ... diff --git a/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll b/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll index c98fcb6a9f0..2dc9a7a5153 100644 --- a/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll +++ b/llvm/test/CodeGen/Hexagon/regalloc-block-overlap.ll @@ -138,6 +138,6 @@ b42: ; preds = %b40 br label %b39 } -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } attributes #1 = { nounwind readnone } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/Hexagon/select-instr-align.ll b/llvm/test/CodeGen/Hexagon/select-instr-align.ll index e3b2929d52f..368ee3c5726 100644 --- a/llvm/test/CodeGen/Hexagon/select-instr-align.ll +++ b/llvm/test/CodeGen/Hexagon/select-instr-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -enable-hexagon-hvx < %s | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK-LABEL: aligned_load: ; CHECK: = vmem({{.*}}) ; CHECK-LABEL: aligned_store: diff --git a/llvm/test/CodeGen/Hexagon/stack-align-reset.ll b/llvm/test/CodeGen/Hexagon/stack-align-reset.ll index 0d028fb95b2..f7639c72862 100644 --- a/llvm/test/CodeGen/Hexagon/stack-align-reset.ll +++ b/llvm/test/CodeGen/Hexagon/stack-align-reset.ll @@ -47,5 +47,5 @@ b11: ; preds = %b11, %b7 declare i32 @llvm.hexagon.V6.extractw(<16 x i32>, i32) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/store-shift.ll b/llvm/test/CodeGen/Hexagon/store-shift.ll index 981071a0181..f7bed980b65 100644 --- a/llvm/test/CodeGen/Hexagon/store-shift.ll +++ b/llvm/test/CodeGen/Hexagon/store-shift.ll @@ -42,7 +42,7 @@ entry: ret void } -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" } !1 = !{!2, !2, i64 0} !2 = !{!"int", !3, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll index 6c67a0dab1a..b80e8e33bf8 100644 --- a/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll +++ b/llvm/test/CodeGen/Hexagon/switch-lut-explicit-section.ll @@ -29,4 +29,4 @@ return: ; preds = %entry ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll index bb2b1e798c8..542bfbb6d66 100644 --- a/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll +++ b/llvm/test/CodeGen/Hexagon/switch-lut-function-section.ll @@ -27,4 +27,4 @@ return: ; preds = %entry ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll b/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll index 57fdfbf33ab..22b61f0c92b 100644 --- a/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll +++ b/llvm/test/CodeGen/Hexagon/switch-lut-multiple-functions.ll @@ -39,4 +39,4 @@ return: ; preds = %entry ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll b/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll index b4d3e898d10..203ea4abd94 100644 --- a/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll +++ b/llvm/test/CodeGen/Hexagon/switch-lut-text-section.ll @@ -24,4 +24,4 @@ return: ; preds = %entry ret i32 19 } -attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll b/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll index c1ab5d73f5c..5aa7f39121d 100644 --- a/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll +++ b/llvm/test/CodeGen/Hexagon/undo-dag-shift.ll @@ -54,6 +54,6 @@ entry: ret void } -attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } -attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double,-long-calls" } +attributes #0 = { norecurse nounwind readonly "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } +attributes #1 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" } diff --git a/llvm/test/CodeGen/Hexagon/v60-cur.ll b/llvm/test/CodeGen/Hexagon/v60-cur.ll index a7d4f6d310e..26d40c9a697 100644 --- a/llvm/test/CodeGen/Hexagon/v60-cur.ll +++ b/llvm/test/CodeGen/Hexagon/v60-cur.ll @@ -54,7 +54,7 @@ declare <16 x i32> @llvm.hexagon.V6.vasrwh(<16 x i32>, <16 x i32>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.hi(<32 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32>, <16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } !1 = !{!2, !2, i64 0} diff --git a/llvm/test/CodeGen/Hexagon/v60-vsel1.ll b/llvm/test/CodeGen/Hexagon/v60-vsel1.ll index e673145c9d1..71d112cc735 100644 --- a/llvm/test/CodeGen/Hexagon/v60-vsel1.ll +++ b/llvm/test/CodeGen/Hexagon/v60-vsel1.ll @@ -65,5 +65,5 @@ declare <16 x i32> @llvm.hexagon.V6.vandqrt(<512 x i1>, i32) #1 declare <16 x i32> @llvm.hexagon.V6.vnot(<16 x i32>) #1 declare <16 x i32> @llvm.hexagon.V6.vand(<16 x i32>, <16 x i32>) #1 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/v60Intrins.ll b/llvm/test/CodeGen/Hexagon/v60Intrins.ll index d0064c50e71..980d8701382 100644 --- a/llvm/test/CodeGen/Hexagon/v60Intrins.ll +++ b/llvm/test/CodeGen/Hexagon/v60Intrins.ll @@ -2555,5 +2555,5 @@ declare <32 x i32> @llvm.hexagon.V6.vunpackh(<16 x i32>) #1 ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.vunpackoh(<32 x i32>, <16 x i32>) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/v60Vasr.ll b/llvm/test/CodeGen/Hexagon/v60Vasr.ll index fb177f614f7..dd309f67646 100644 --- a/llvm/test/CodeGen/Hexagon/v60Vasr.ll +++ b/llvm/test/CodeGen/Hexagon/v60Vasr.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s +; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vasr(v{{[0-9]+}}.h,v{{[0-9]+}}.h,r{{[0-7]+}}):sat diff --git a/llvm/test/CodeGen/Hexagon/v60small.ll b/llvm/test/CodeGen/Hexagon/v60small.ll index 8a6a6155a39..efa726e2c6b 100644 --- a/llvm/test/CodeGen/Hexagon/v60small.ll +++ b/llvm/test/CodeGen/Hexagon/v60small.ll @@ -47,5 +47,5 @@ declare <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1>, <512 x i1>) #1 ; Function Attrs: nounwind readnone declare <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1>, <512 x i1>) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll index 24daeac3fb5..18c2cf65f72 100644 --- a/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll +++ b/llvm/test/CodeGen/Hexagon/v6vec-vprint.ll @@ -1,5 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck %s -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print < %s | FileCheck --check-prefix=CHECK %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b -disable-hexagon-shuffle=0 -O2 -enable-hexagon-vector-print -trace-hex-vector-stores-only < %s | FileCheck --check-prefix=VSTPRINT %s ; generate .long XXXX which is a vector debug print instruction. ; CHECK: .long 0x1dffe0 ; CHECK: .long 0x1dffe0 diff --git a/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll b/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll index a9a0d51e43b..0facdc33555 100644 --- a/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll +++ b/llvm/test/CodeGen/Hexagon/vassign-to-combine.ll @@ -52,5 +52,5 @@ b2: ; preds = %b1 } attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll b/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll index 7e41bd4d20d..352398e7bbe 100644 --- a/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll +++ b/llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll @@ -155,8 +155,8 @@ destructor_block: ; preds = %"for testOne.s0.x.x ; Function Attrs: nounwind readnone declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !5 = !{!6, !6, i64 0} !6 = !{!"inputOne", !7} diff --git a/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll b/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll index d120295fa52..40b4a819ad6 100644 --- a/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll +++ b/llvm/test/CodeGen/Hexagon/vec-pred-spill1.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -enable-hexagon-hvx < %s | FileCheck %s +; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -mattr=+hvxv60,hvx-length64b < %s | FileCheck %s ; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}} ; CHECK: call puts diff --git a/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll b/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll index d4c6bd3ef61..0101c1ffa8a 100644 --- a/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll +++ b/llvm/test/CodeGen/Hexagon/vec-vararg-align.ll @@ -27,4 +27,4 @@ b0: declare i32 @printf(i8*, ...) #0 declare void @VarVec1(i8*, i32, ...) #0 -attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" } +attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } diff --git a/llvm/test/CodeGen/Hexagon/vector-align.ll b/llvm/test/CodeGen/Hexagon/vector-align.ll index 557ee3f97f2..043839c704a 100644 --- a/llvm/test/CodeGen/Hexagon/vector-align.ll +++ b/llvm/test/CodeGen/Hexagon/vector-align.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx < %s \ +; RUN: llc -march=hexagon -mcpu=hexagonv60 -mattr=+hvxv60,hvx-length64b < %s \ ; RUN: | FileCheck %s ; Check that the store to Q6VecPredResult does not get expanded into multiple diff --git a/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll b/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll index 70ed3a9b1e8..a3bed31071d 100644 --- a/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll +++ b/llvm/test/CodeGen/Hexagon/vload-postinc-sel.ll @@ -49,4 +49,4 @@ call_destructor.exit: ; preds = %entry declare <32 x i32> @llvm.hexagon.V6.valignbi.128B(<32 x i32>, <32 x i32>, i32) #0 attributes #0 = { nounwind readnone } -attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-double" } +attributes #1 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" } diff --git a/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll b/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll index 9c359900ba4..8b207ba4f23 100644 --- a/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll +++ b/llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll @@ -133,8 +133,8 @@ destructor_block: ; preds = %"for testOne.s0.x.x ; Function Attrs: nounwind readnone declare <32 x i32> @llvm.hexagon.V6.vmpabuuv(<32 x i32>, <32 x i32>) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !5 = !{!6, !6, i64 0} !6 = !{!"inputOne", !7} diff --git a/llvm/test/CodeGen/Hexagon/vpack_eo.ll b/llvm/test/CodeGen/Hexagon/vpack_eo.ll index 7238ca84a42..cf8619c0f0a 100644 --- a/llvm/test/CodeGen/Hexagon/vpack_eo.ll +++ b/llvm/test/CodeGen/Hexagon/vpack_eo.ll @@ -61,8 +61,8 @@ entry: ; Function Attrs: nounwind readnone declare <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32>, <16 x i32>) #1 -attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } -attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" } +attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } +attributes #1 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" } !4 = !{!5, !5, i64 0} !5 = !{!"InputOne", !6} diff --git a/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll b/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll index ef86e47e395..e6be3ee69c0 100644 --- a/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll +++ b/llvm/test/CodeGen/Hexagon/vselect-pseudo.ll @@ -1,4 +1,4 @@ -; RUN: llc -march=hexagon < %s +; RUN: llc -march=hexagon -mattr="+hvxv60,+hvx-length64b" < %s ; REQUIRES: asserts target triple = "hexagon" diff --git a/llvm/test/MC/Hexagon/align.s b/llvm/test/MC/Hexagon/align.s index 80cebf125ce..e85534def21 100644 --- a/llvm/test/MC/Hexagon/align.s +++ b/llvm/test/MC/Hexagon/align.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -triple=hexagon -filetype=obj %s | llvm-objdump -d - | FileCheck %s +# RUN: llvm-mc -triple=hexagon -filetype=obj -mhvx %s | llvm-objdump -mhvx -d - | FileCheck %s # Verify that the .align directive emits the proper insn packets. diff --git a/llvm/test/MC/Hexagon/double-vector-producer.s b/llvm/test/MC/Hexagon/double-vector-producer.s index 5421653b5b4..e10917b06fb 100644 --- a/llvm/test/MC/Hexagon/double-vector-producer.s +++ b/llvm/test/MC/Hexagon/double-vector-producer.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -filetype=obj %s | llvm-objdump -d - | FileCheck %s +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mhvx -filetype=obj %s | llvm-objdump -d - | FileCheck %s { v1:0 = vshuff(v1,v0,r7) v2.w = vadd(v13.w,v15.w) diff --git a/llvm/test/MC/Hexagon/test.s b/llvm/test/MC/Hexagon/test.s index 73b6d0a96c7..35a395a3ac4 100644 --- a/llvm/test/MC/Hexagon/test.s +++ b/llvm/test/MC/Hexagon/test.s @@ -1,4 +1,4 @@ -#RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 %s +#RUN: llvm-mc -filetype=obj -triple=hexagon -mcpu=hexagonv60 -mhvx %s { vmem (r0 + #0) = v0 - r0 = memw(r0) }
\ No newline at end of file + r0 = memw(r0) } diff --git a/llvm/test/MC/Hexagon/v60-alu.s b/llvm/test/MC/Hexagon/v60-alu.s index 1583c3da2cb..856a9fec91a 100644 --- a/llvm/test/MC/Hexagon/v60-alu.s +++ b/llvm/test/MC/Hexagon/v60-alu.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1ce2cbd7 { v23.w = vavg(v11.w,{{ *}}v2.w):rnd } diff --git a/llvm/test/MC/Hexagon/v60-misc.s b/llvm/test/MC/Hexagon/v60-misc.s index b278447ab10..53872d64dcf 100644 --- a/llvm/test/MC/Hexagon/v60-misc.s +++ b/llvm/test/MC/Hexagon/v60-misc.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -d - | FileCheck %s +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv60 -mattr=+hvx -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv60 -mhvx -d - | FileCheck %s .L0: diff --git a/llvm/test/MC/Hexagon/v60-permute.s b/llvm/test/MC/Hexagon/v60-permute.s index b3544bd0a57..0b0697a9e2f 100644 --- a/llvm/test/MC/Hexagon/v60-permute.s +++ b/llvm/test/MC/Hexagon/v60-permute.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1fd2d5cf { v15.b = vpack(v21.h{{ *}},{{ *}}v18.h):sat } diff --git a/llvm/test/MC/Hexagon/v60-shift.s b/llvm/test/MC/Hexagon/v60-shift.s index 3d0c334debb..0002714cab4 100644 --- a/llvm/test/MC/Hexagon/v60-shift.s +++ b/llvm/test/MC/Hexagon/v60-shift.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 198fd829 { v9.uw = vlsr(v24.uw,{{ *}}r15) } diff --git a/llvm/test/MC/Hexagon/v60-vcmp.s b/llvm/test/MC/Hexagon/v60-vcmp.s index c7f4e128be6..712f570f99e 100644 --- a/llvm/test/MC/Hexagon/v60-vcmp.s +++ b/llvm/test/MC/Hexagon/v60-vcmp.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1c81f142 { q2 |= vcmp.eq(v17.b{{ *}},{{ *}}v1.b) } diff --git a/llvm/test/MC/Hexagon/v60-vmem.s b/llvm/test/MC/Hexagon/v60-vmem.s index 0580a1e6244..bf549c893a1 100644 --- a/llvm/test/MC/Hexagon/v60-vmem.s +++ b/llvm/test/MC/Hexagon/v60-vmem.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 292cc11b { vmem(r12++#1) = v27 } diff --git a/llvm/test/MC/Hexagon/v60-vmpy-acc.s b/llvm/test/MC/Hexagon/v60-vmpy-acc.s index c39a9252b56..a582a5f740c 100644 --- a/llvm/test/MC/Hexagon/v60-vmpy-acc.s +++ b/llvm/test/MC/Hexagon/v60-vmpy-acc.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1936ee37 { v23.w += vdmpy(v15:14.h,r22.uh,#1):sat } diff --git a/llvm/test/MC/Hexagon/v60-vmpy1.s b/llvm/test/MC/Hexagon/v60-vmpy1.s index 1f36a5e95dd..dd86a084d1f 100644 --- a/llvm/test/MC/Hexagon/v60-vmpy1.s +++ b/llvm/test/MC/Hexagon/v60-vmpy1.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s #CHECK: 1939c223 { v3.w = vdmpy(v3:2.h,{{ *}}r25.uh,{{ *}}#1):sat } diff --git a/llvm/test/MC/Hexagon/v60lookup.s b/llvm/test/MC/Hexagon/v60lookup.s index b92a2d3c6eb..d4c520210a0 100644 --- a/llvm/test/MC/Hexagon/v60lookup.s +++ b/llvm/test/MC/Hexagon/v60lookup.s @@ -1,5 +1,5 @@ -#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj %s | \ -#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -d - | \ +#RUN: llvm-mc -triple=hexagon -mcpu=hexagonv60 -filetype=obj -mhvx %s | \ +#RUN: llvm-objdump -triple=hexagon -mcpu=hexagonv60 -mhvx -d - | \ #RUN: FileCheck %s V31.b = vlut32(V29.b, V15.b, R1) diff --git a/llvm/test/MC/Hexagon/v62_all.s b/llvm/test/MC/Hexagon/v62_all.s index 6effdc0caba..79e30982e96 100644 --- a/llvm/test/MC/Hexagon/v62_all.s +++ b/llvm/test/MC/Hexagon/v62_all.s @@ -1,4 +1,4 @@ -# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj %s | llvm-objdump -arch=hexagon -mcpu=hexagonv62 -d - | FileCheck %s +# RUN: llvm-mc -arch=hexagon -mcpu=hexagonv62 -filetype=obj -mhvx %s | llvm-objdump -arch=hexagon -mcpu=hexagonv62 -mhvx -d - | FileCheck %s // V6_lvsplatb // Vd32.b=vsplat(Rt32) diff --git a/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll b/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll index 4bc1251572a..a81737a7979 100644 --- a/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll +++ b/llvm/test/Transforms/SimplifyCFG/Hexagon/switch-to-lookup-table.ll @@ -59,4 +59,4 @@ return: ; preds = %sw.default, %sw.bb5 ret i32 %1 } -attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll b/llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll index b14eb2a85ed..fd3537209ca 100644 --- a/llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll +++ b/llvm/test/tools/llvm-objdump/Hexagon/source-interleave-hexagon.ll @@ -34,7 +34,7 @@ entry: ; Function Attrs: nounwind readnone declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx,-hvx-double" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx" "unsafe-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!0} |
