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-rw-r--r--llvm/test/CodeGen/Hexagon/alu64.ll599
-rw-r--r--llvm/test/CodeGen/Hexagon/remove-endloop.ll56
2 files changed, 655 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/alu64.ll b/llvm/test/CodeGen/Hexagon/alu64.ll
new file mode 100644
index 00000000000..d0824a4ecad
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/alu64.ll
@@ -0,0 +1,599 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: @test00
+; CHECK: p0 = cmp.eq(r1:0, r3:2)
+define i32 @test00(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.C2.cmpeqp(i64 %Rs, i64 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test01
+; CHECK: p0 = cmp.gt(r1:0, r3:2)
+define i32 @test01(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.C2.cmpgtp(i64 %Rs, i64 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test02
+; CHECK: p0 = cmp.gtu(r1:0, r3:2)
+define i32 @test02(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.C2.cmpgtup(i64 %Rs, i64 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test10
+; CHECK: r0 = cmp.eq(r0, r1)
+define i32 @test10(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.rcmpeq(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test11
+; CHECK: r0 = !cmp.eq(r0, r1)
+define i32 @test11(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.rcmpneq(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test12
+; CHECK: r0 = cmp.eq(r0, #23)
+define i32 @test12(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.rcmpeqi(i32 %Rs, i32 23)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test13
+; CHECK: r0 = !cmp.eq(r0, #47)
+define i32 @test13(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.rcmpneqi(i32 %Rs, i32 47)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test20
+; CHECK: p0 = cmpb.eq(r0, r1)
+define i32 @test20(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmpbeq(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test21
+; CHECK: p0 = cmpb.gt(r0, r1)
+define i32 @test21(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmpbgt(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test22
+; CHECK: p0 = cmpb.gtu(r0, r1)
+define i32 @test22(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmpbgtu(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test23
+; CHECK: p0 = cmpb.eq(r0, #56)
+define i32 @test23(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmpbeqi(i32 %Rs, i32 56)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test24
+; CHECK: p0 = cmpb.gt(r0, #29)
+define i32 @test24(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmpbgti(i32 %Rs, i32 29)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test25
+; CHECK: p0 = cmpb.gtu(r0, #111)
+define i32 @test25(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmpbgtui(i32 %Rs, i32 111)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test30
+; CHECK: p0 = cmph.eq(r0, r1)
+define i32 @test30(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmpheq(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test31
+; CHECK: p0 = cmph.gt(r0, r1)
+define i32 @test31(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmphgt(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test32
+; CHECK: p0 = cmph.gtu(r0, r1)
+define i32 @test32(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmphgtu(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test33
+; CHECK: p0 = cmph.eq(r0, #-123)
+define i32 @test33(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmpheqi(i32 %Rs, i32 -123)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test34
+; CHECK: p0 = cmph.gt(r0, #-3)
+define i32 @test34(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmphgti(i32 %Rs, i32 -3)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test35
+; CHECK: p0 = cmph.gtu(r0, #13)
+define i32 @test35(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.cmphgtui(i32 %Rs, i32 13)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test40
+; CHECK: r1:0 = vmux(p0, r3:2, r5:4)
+define i64 @test40(i32 %Pu, i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.C2.vmux(i32 %Pu, i64 %Rs, i64 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test41
+; CHECK: p0 = any8(vcmpb.eq(r1:0, r3:2))
+define i32 @test41(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.vcmpbeq.any(i64 %Rs, i64 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test50
+; CHECK: r1:0 = add(r1:0, r3:2)
+define i64 @test50(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.A2.addp(i64 %Rs, i64 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test51
+; CHECK: r1:0 = add(r1:0, r3:2):sat
+define i64 @test51(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.A2.addpsat(i64 %Rs, i64 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test52
+; CHECK: r1:0 = sub(r1:0, r3:2)
+define i64 @test52(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.A2.subp(i64 %Rs, i64 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test53
+; CHECK: r1:0 = add(r0, r3:2)
+define i64 @test53(i32 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.A2.addsp(i32 %Rs, i64 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test54
+; CHECK: r1:0 = and(r1:0, r3:2)
+define i64 @test54(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.A2.andp(i64 %Rs, i64 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test55
+; CHECK: r1:0 = or(r1:0, r3:2)
+define i64 @test55(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.A2.orp(i64 %Rs, i64 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test56
+; CHECK: r1:0 = xor(r1:0, r3:2)
+define i64 @test56(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.A2.xorp(i64 %Rs, i64 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test57
+; CHECK: r1:0 = and(r1:0, ~r3:2)
+define i64 @test57(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.A4.andnp(i64 %Rs, i64 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test58
+; CHECK: r1:0 = or(r1:0, ~r3:2)
+define i64 @test58(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.A4.ornp(i64 %Rs, i64 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test60
+; CHECK: r0 = add(r0.l, r1.l)
+define i32 @test60(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.l16.ll(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test61
+; CHECK: r0 = add(r0.l, r1.h)
+define i32 @test61(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.l16.hl(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test62
+; CHECK: r0 = add(r0.l, r1.l):sat
+define i32 @test62(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test63
+; CHECK: r0 = add(r0.l, r1.h):sat
+define i32 @test63(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test64
+; CHECK: r0 = add(r0.l, r1.l):<<16
+define i32 @test64(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.h16.ll(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test65
+; CHECK: r0 = add(r0.l, r1.h):<<16
+define i32 @test65(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.h16.lh(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test66
+; CHECK: r0 = add(r0.h, r1.l):<<16
+define i32 @test66(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hl(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test67
+; CHECK: r0 = add(r0.h, r1.h):<<16
+define i32 @test67(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.h16.hh(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test68
+; CHECK: r0 = add(r0.l, r1.l):sat:<<16
+define i32 @test68(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test69
+; CHECK: r0 = add(r0.l, r1.h):sat:<<16
+define i32 @test69(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test6A
+; CHECK: r0 = add(r0.h, r1.l):sat:<<16
+define i32 @test6A(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test6B
+; CHECK: r0 = add(r0.h, r1.h):sat:<<16
+define i32 @test6B(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test70
+; CHECK: r0 = sub(r0.l, r1.l)
+define i32 @test70(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.l16.ll(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test71
+; CHECK: r0 = sub(r0.l, r1.h)
+define i32 @test71(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.l16.hl(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test72
+; CHECK: r0 = sub(r0.l, r1.l):sat
+define i32 @test72(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test73
+; CHECK: r0 = sub(r0.l, r1.h):sat
+define i32 @test73(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test74
+; CHECK: r0 = sub(r0.l, r1.l):<<16
+define i32 @test74(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.h16.ll(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test75
+; CHECK: r0 = sub(r0.l, r1.h):<<16
+define i32 @test75(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.h16.lh(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test76
+; CHECK: r0 = sub(r0.h, r1.l):<<16
+define i32 @test76(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.h16.hl(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test77
+; CHECK: r0 = sub(r0.h, r1.h):<<16
+define i32 @test77(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.h16.hh(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test78
+; CHECK: r0 = sub(r0.l, r1.l):sat:<<16
+define i32 @test78(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test79
+; CHECK: r0 = sub(r0.l, r1.h):sat:<<16
+define i32 @test79(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test7A
+; CHECK: r0 = sub(r0.h, r1.l):sat:<<16
+define i32 @test7A(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test7B
+; CHECK: r0 = sub(r0.h, r1.h):sat:<<16
+define i32 @test7B(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test90
+; CHECK: r0 = and(#1, asl(r0, #2))
+define i32 @test90(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.S4.andi.asl.ri(i32 1, i32 %Rs, i32 2)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test91
+; CHECK: r0 = or(#1, asl(r0, #2))
+define i32 @test91(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.S4.ori.asl.ri(i32 1, i32 %Rs, i32 2)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test92
+; CHECK: r0 = add(#1, asl(r0, #2))
+define i32 @test92(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.S4.addi.asl.ri(i32 1, i32 %Rs, i32 2)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test93
+; CHECK: r0 = sub(#1, asl(r0, #2))
+define i32 @test93(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.S4.subi.asl.ri(i32 1, i32 %Rs, i32 2)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test94
+; CHECK: r0 = and(#1, lsr(r0, #2))
+define i32 @test94(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.S4.andi.lsr.ri(i32 1, i32 %Rs, i32 2)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test95
+; CHECK: r0 = or(#1, lsr(r0, #2))
+define i32 @test95(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.S4.ori.lsr.ri(i32 1, i32 %Rs, i32 2)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test96
+; CHECK: r0 = add(#1, lsr(r0, #2))
+define i32 @test96(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.S4.addi.lsr.ri(i32 1, i32 %Rs, i32 2)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test97
+; CHECK: r0 = sub(#1, lsr(r0, #2))
+define i32 @test97(i32 %Rs) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.S4.subi.lsr.ri(i32 1, i32 %Rs, i32 2)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test100
+; CHECK: r1:0 = bitsplit(r0, r1)
+define i64 @test100(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i64 @llvm.hexagon.A4.bitsplit(i32 %Rs, i32 %Rt)
+ ret i64 %0
+}
+
+; CHECK-LABEL: @test101
+; CHECK: r0 = modwrap(r0, r1)
+define i32 @test101(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.A4.modwrapu(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test102
+; CHECK: r0 = parity(r1:0, r3:2)
+define i32 @test102(i64 %Rs, i64 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.S2.parityp(i64 %Rs, i64 %Rt)
+ ret i32 %0
+}
+
+; CHECK-LABEL: @test103
+; CHECK: r0 = parity(r0, r1)
+define i32 @test103(i32 %Rs, i32 %Rt) #0 {
+entry:
+ %0 = tail call i32 @llvm.hexagon.S4.parity(i32 %Rs, i32 %Rt)
+ ret i32 %0
+}
+
+declare i32 @llvm.hexagon.C2.cmpeqp(i64, i64) #1
+declare i32 @llvm.hexagon.C2.cmpgtp(i64, i64) #1
+declare i32 @llvm.hexagon.C2.cmpgtup(i64, i64) #1
+declare i32 @llvm.hexagon.A4.rcmpeq(i32, i32) #1
+declare i32 @llvm.hexagon.A4.rcmpneq(i32, i32) #1
+declare i32 @llvm.hexagon.A4.rcmpeqi(i32, i32) #1
+declare i32 @llvm.hexagon.A4.rcmpneqi(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbeq(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbgt(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbgtu(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbeqi(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbgti(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpbgtui(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpheq(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmphgt(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmphgtu(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmpheqi(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmphgti(i32, i32) #1
+declare i32 @llvm.hexagon.A4.cmphgtui(i32, i32) #1
+declare i64 @llvm.hexagon.C2.vmux(i32, i64, i64) #1
+declare i32 @llvm.hexagon.A4.vcmpbeq.any(i64, i64) #1
+declare i64 @llvm.hexagon.A2.addp(i64, i64) #1
+declare i64 @llvm.hexagon.A2.addpsat(i64, i64) #1
+declare i64 @llvm.hexagon.A2.subp(i64, i64) #1
+declare i64 @llvm.hexagon.A2.addsp(i32, i64) #1
+declare i64 @llvm.hexagon.A2.andp(i64, i64) #1
+declare i64 @llvm.hexagon.A2.orp(i64, i64) #1
+declare i64 @llvm.hexagon.A2.xorp(i64, i64) #1
+declare i64 @llvm.hexagon.A4.ornp(i64, i64) #1
+declare i64 @llvm.hexagon.A4.andnp(i64, i64) #1
+declare i32 @llvm.hexagon.A2.addh.l16.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.l16.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.lh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.hh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.sat.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.addh.h16.sat.hh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.l16.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.l16.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.l16.sat.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.l16.sat.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.lh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.hh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.sat.ll(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.sat.lh(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.sat.hl(i32, i32) #1
+declare i32 @llvm.hexagon.A2.subh.h16.sat.hh(i32, i32) #1
+declare i64 @llvm.hexagon.A4.bitsplit(i32, i32) #1
+declare i32 @llvm.hexagon.A4.modwrapu(i32, i32) #1
+declare i32 @llvm.hexagon.S2.parityp(i64, i64) #1
+declare i32 @llvm.hexagon.S4.parity(i32, i32) #1
+declare i32 @llvm.hexagon.S4.andi.asl.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.ori.asl.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.addi.asl.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.subi.asl.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.andi.lsr.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.ori.lsr.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.addi.lsr.ri(i32, i32, i32) #1
+declare i32 @llvm.hexagon.S4.subi.lsr.ri(i32, i32, i32) #1
+
+attributes #0 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { nounwind readnone }
diff --git a/llvm/test/CodeGen/Hexagon/remove-endloop.ll b/llvm/test/CodeGen/Hexagon/remove-endloop.ll
new file mode 100644
index 00000000000..73e1ad02cd8
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/remove-endloop.ll
@@ -0,0 +1,56 @@
+; RUN: llc -march=hexagon -O2 < %s | FileCheck %s
+
+define void @foo(i32 %n, i32* nocapture %A, i32* nocapture %B) nounwind optsize {
+entry:
+ %cmp = icmp sgt i32 %n, 100
+ br i1 %cmp, label %for.body.preheader, label %for.cond4.preheader
+
+; CHECK: endloop0
+; CHECK: endloop0
+; CHECK-NOT: endloop0
+
+for.body.preheader:
+ br label %for.body
+
+for.cond4.preheader:
+ %cmp113 = icmp sgt i32 %n, 0
+ br i1 %cmp113, label %for.body7.preheader, label %if.end
+
+for.body7.preheader:
+ br label %for.body7
+
+for.body:
+ %arrayidx.phi = phi i32* [ %arrayidx.inc, %for.body ], [ %B, %for.body.preheader ]
+ %arrayidx3.phi = phi i32* [ %arrayidx3.inc, %for.body ], [ %A, %for.body.preheader ]
+ %i.014 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
+ %0 = load i32, i32* %arrayidx.phi, align 4
+ %sub = add nsw i32 %0, -1
+ store i32 %sub, i32* %arrayidx3.phi, align 4
+ %inc = add nsw i32 %i.014, 1
+ %exitcond = icmp eq i32 %inc, %n
+ %arrayidx.inc = getelementptr i32, i32* %arrayidx.phi, i32 1
+ %arrayidx3.inc = getelementptr i32, i32* %arrayidx3.phi, i32 1
+ br i1 %exitcond, label %if.end.loopexit, label %for.body
+
+for.body7:
+ %arrayidx8.phi = phi i32* [ %arrayidx8.inc, %for.body7 ], [ %B, %for.body7.preheader ]
+ %arrayidx9.phi = phi i32* [ %arrayidx9.inc, %for.body7 ], [ %A, %for.body7.preheader ]
+ %i.117 = phi i32 [ %inc11, %for.body7 ], [ 0, %for.body7.preheader ]
+ %1 = load i32, i32* %arrayidx8.phi, align 4
+ %add = add nsw i32 %1, 1
+ store i32 %add, i32* %arrayidx9.phi, align 4
+ %inc11 = add nsw i32 %i.117, 1
+ %exitcond18 = icmp eq i32 %inc11, %n
+ %arrayidx8.inc = getelementptr i32, i32* %arrayidx8.phi, i32 1
+ %arrayidx9.inc = getelementptr i32, i32* %arrayidx9.phi, i32 1
+ br i1 %exitcond18, label %if.end.loopexit21, label %for.body7
+
+if.end.loopexit:
+ br label %if.end
+
+if.end.loopexit21:
+ br label %if.end
+
+if.end:
+ ret void
+}
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