diff options
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll | 18 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/vsx.ll | 8 |
3 files changed, 14 insertions, 20 deletions
diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll index 979dd4b5d02..1f317992a3b 100644 --- a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll +++ b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll @@ -46,10 +46,10 @@ entry: %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer ret <4 x i32> %splat.splat -; CHECK: sldi [[REG1:[0-9]+]], 3, 32 -; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] -; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 -; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] +; CHECK: mtvsrwz [[REG1:[0-9]+]], 3 +; CHECK: xxspltw 34, [[REG1]] +; CHECK-LE: mtvsrwz [[REG1:[0-9]+]], 3 +; CHECK-LE: xxspltw 34, [[REG1]] } ; Function Attrs: nounwind diff --git a/llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll b/llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll index fa4f0320c92..68995de702c 100644 --- a/llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll +++ b/llvm/test/CodeGen/PowerPC/power9-moves-and-splats.ll @@ -10,15 +10,9 @@ entry: ; The FIXME below is due to the lowering for BUILD_VECTOR needing a re-vamp ; which will happen in a subsequent patch. ; CHECK-LABEL: test1 -; FIXME: mtvsrdd 34, 4, 3 -; CHECK: mtvsrd {{[0-9]+}}, 3 -; CHECK: mtvsrd {{[0-9]+}}, 4 -; CHECK: xxmrgld +; CHECK: mtvsrdd 34, 4, 3 ; CHECK-BE-LABEL: test1 -; FIXME-BE: mtvsrdd 34, 3, 4 -; CHECK-BE: mtvsrd {{[0-9]+}}, 4 -; CHECK-BE: mtvsrd {{[0-9]+}}, 3 -; CHECK-BE: xxmrghd +; CHECK-BE: mtvsrdd 34, 3, 4 %vecins = insertelement <2 x i64> undef, i64 %a, i32 0 %vecins1 = insertelement <2 x i64> %vecins, i64 %b, i32 1 ret <2 x i64> %vecins1 @@ -162,10 +156,14 @@ define <4 x i32> @test14(<4 x i32> %a, i32* nocapture readonly %b) { entry: ; CHECK-LABEL: test14 ; CHECK: lwz [[LD:[0-9]+]], -; CHECK: mtvsrws 34, [[LD]] +; FIXME: mtvsrws 34, [[LD]] +; CHECK: mtvsrws [[SPLT:[0-9]+]], [[LD]] +; CHECK: xxspltw 34, [[SPLT]], 3 ; CHECK-BE-LABEL: test14 ; CHECK-BE: lwz [[LD:[0-9]+]], -; CHECK-BE: mtvsrws 34, [[LD]] +; FIXME: mtvsrws 34, [[LD]] +; CHECK-BE: mtvsrws [[SPLT:[0-9]+]], [[LD]] +; CHECK-BE: xxspltw 34, [[SPLT]], 0 %0 = load i32, i32* %b, align 4 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer diff --git a/llvm/test/CodeGen/PowerPC/vsx.ll b/llvm/test/CodeGen/PowerPC/vsx.ll index b15dc4bede1..f1a165c3358 100644 --- a/llvm/test/CodeGen/PowerPC/vsx.ll +++ b/llvm/test/CodeGen/PowerPC/vsx.ll @@ -1096,9 +1096,7 @@ define <2 x double> @test69(<2 x i16> %a) { ; CHECK-LE: mtvsrwa ; CHECK-LE: xscvsxddp ; CHECK-LE: xscvsxddp -; CHECK-LE: xxspltd -; CHECK-LE: xxspltd -; CHECK-LE: xxmrgld +; CHECK-LE: xxmrghd ; CHECK-LE: blr } @@ -1121,9 +1119,7 @@ define <2 x double> @test70(<2 x i8> %a) { ; CHECK-LE: mtvsrwa ; CHECK-LE: xscvsxddp ; CHECK-LE: xscvsxddp -; CHECK-LE: xxspltd -; CHECK-LE: xxspltd -; CHECK-LE: xxmrgld +; CHECK-LE: xxmrghd ; CHECK-LE: blr } |
