diff options
Diffstat (limited to 'llvm/test')
23 files changed, 231 insertions, 555 deletions
diff --git a/llvm/test/CodeGen/RISCV/alloca.ll b/llvm/test/CodeGen/RISCV/alloca.ll index 68efceaec20..22dd42ccb7e 100644 --- a/llvm/test/CodeGen/RISCV/alloca.ll +++ b/llvm/test/CodeGen/RISCV/alloca.ll @@ -18,9 +18,7 @@ define void @simple_alloca(i32 %n) nounwind { ; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: mv sp, a0 -; RV32I-NEXT: lui a1, %hi(notdead) -; RV32I-NEXT: addi a1, a1, %lo(notdead) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call notdead ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw s0, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) @@ -47,9 +45,7 @@ define void @scoped_alloca(i32 %n) nounwind { ; RV32I-NEXT: andi a0, a0, -16 ; RV32I-NEXT: sub a0, sp, a0 ; RV32I-NEXT: mv sp, a0 -; RV32I-NEXT: lui a1, %hi(notdead) -; RV32I-NEXT: addi a1, a1, %lo(notdead) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call notdead ; RV32I-NEXT: mv sp, s1 ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw s1, 4(sp) @@ -88,8 +84,6 @@ define void @alloca_callframe(i32 %n) nounwind { ; RV32I-NEXT: sw a1, 4(sp) ; RV32I-NEXT: addi a1, zero, 9 ; RV32I-NEXT: sw a1, 0(sp) -; RV32I-NEXT: lui a1, %hi(func) -; RV32I-NEXT: addi t0, a1, %lo(func) ; RV32I-NEXT: addi a1, zero, 2 ; RV32I-NEXT: addi a2, zero, 3 ; RV32I-NEXT: addi a3, zero, 4 @@ -97,7 +91,7 @@ define void @alloca_callframe(i32 %n) nounwind { ; RV32I-NEXT: addi a5, zero, 6 ; RV32I-NEXT: addi a6, zero, 7 ; RV32I-NEXT: addi a7, zero, 8 -; RV32I-NEXT: jalr t0 +; RV32I-NEXT: call func ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: addi sp, s0, -16 ; RV32I-NEXT: lw s0, 8(sp) diff --git a/llvm/test/CodeGen/RISCV/analyze-branch.ll b/llvm/test/CodeGen/RISCV/analyze-branch.ll index bf34a0d9f9f..f5b07836e87 100644 --- a/llvm/test/CodeGen/RISCV/analyze-branch.ll +++ b/llvm/test/CodeGen/RISCV/analyze-branch.ll @@ -20,16 +20,13 @@ define void @test_bcc_fallthrough_taken(i32 %in) nounwind { ; RV32I-NEXT: addi a1, zero, 42 ; RV32I-NEXT: bne a0, a1, .LBB0_3 ; RV32I-NEXT: # %bb.1: # %true -; RV32I-NEXT: lui a0, %hi(test_true) -; RV32I-NEXT: addi a0, a0, %lo(test_true) +; RV32I-NEXT: call test_true ; RV32I-NEXT: .LBB0_2: # %true -; RV32I-NEXT: jalr a0 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB0_3: # %false -; RV32I-NEXT: lui a0, %hi(test_false) -; RV32I-NEXT: addi a0, a0, %lo(test_false) +; RV32I-NEXT: call test_false ; RV32I-NEXT: j .LBB0_2 %tst = icmp eq i32 %in, 42 br i1 %tst, label %true, label %false, !prof !0 @@ -55,16 +52,13 @@ define void @test_bcc_fallthrough_nottaken(i32 %in) nounwind { ; RV32I-NEXT: addi a1, zero, 42 ; RV32I-NEXT: beq a0, a1, .LBB1_3 ; RV32I-NEXT: # %bb.1: # %false -; RV32I-NEXT: lui a0, %hi(test_false) -; RV32I-NEXT: addi a0, a0, %lo(test_false) +; RV32I-NEXT: call test_false ; RV32I-NEXT: .LBB1_2: # %true -; RV32I-NEXT: jalr a0 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; RV32I-NEXT: .LBB1_3: # %true -; RV32I-NEXT: lui a0, %hi(test_true) -; RV32I-NEXT: addi a0, a0, %lo(test_true) +; RV32I-NEXT: call test_true ; RV32I-NEXT: j .LBB1_2 %tst = icmp eq i32 %in, 42 br i1 %tst, label %true, label %false, !prof !1 diff --git a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll index 8ac687081cd..5fd7a0b2d9a 100644 --- a/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll +++ b/llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll @@ -105,9 +105,7 @@ define i8 @test_cttz_i8(i8 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: j .LBB3_3 ; RV32I-NEXT: .LBB3_2: @@ -151,9 +149,7 @@ define i16 @test_cttz_i16(i16 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: j .LBB4_3 ; RV32I-NEXT: .LBB4_2: @@ -194,9 +190,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: j .LBB5_3 ; RV32I-NEXT: .LBB5_2: @@ -245,9 +239,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: j .LBB6_3 ; RV32I-NEXT: .LBB6_2: @@ -263,16 +255,15 @@ define i32 @test_ctlz_i32(i32 %a) nounwind { define i64 @test_cttz_i64(i64 %a) nounwind { ; RV32I-LABEL: test_cttz_i64: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -48 -; RV32I-NEXT: sw ra, 44(sp) -; RV32I-NEXT: sw s1, 40(sp) -; RV32I-NEXT: sw s2, 36(sp) -; RV32I-NEXT: sw s3, 32(sp) -; RV32I-NEXT: sw s4, 28(sp) -; RV32I-NEXT: sw s5, 24(sp) -; RV32I-NEXT: sw s6, 20(sp) -; RV32I-NEXT: sw s7, 16(sp) -; RV32I-NEXT: sw s8, 12(sp) +; RV32I-NEXT: addi sp, sp, -32 +; RV32I-NEXT: sw ra, 28(sp) +; RV32I-NEXT: sw s1, 24(sp) +; RV32I-NEXT: sw s2, 20(sp) +; RV32I-NEXT: sw s3, 16(sp) +; RV32I-NEXT: sw s4, 12(sp) +; RV32I-NEXT: sw s5, 8(sp) +; RV32I-NEXT: sw s6, 4(sp) +; RV32I-NEXT: sw s7, 0(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: addi a0, a0, -1 @@ -293,13 +284,11 @@ define i64 @test_cttz_i64(i64 %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s4, a1, 257 -; RV32I-NEXT: lui a1, %hi(__mulsi3) -; RV32I-NEXT: addi s7, a1, %lo(__mulsi3) ; RV32I-NEXT: lui a1, 61681 -; RV32I-NEXT: addi s8, a1, -241 -; RV32I-NEXT: and a0, a0, s8 +; RV32I-NEXT: addi s7, a1, -241 +; RV32I-NEXT: and a0, a0, s7 ; RV32I-NEXT: mv a1, s4 -; RV32I-NEXT: jalr s7 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: addi a0, s2, -1 ; RV32I-NEXT: not a1, s2 @@ -313,9 +302,9 @@ define i64 @test_cttz_i64(i64 %a) nounwind { ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: add a0, a0, a1 -; RV32I-NEXT: and a0, a0, s8 +; RV32I-NEXT: and a0, a0, s7 ; RV32I-NEXT: mv a1, s4 -; RV32I-NEXT: jalr s7 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s3, .LBB7_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 24 @@ -325,16 +314,15 @@ define i64 @test_cttz_i64(i64 %a) nounwind { ; RV32I-NEXT: srli a0, s1, 24 ; RV32I-NEXT: .LBB7_3: ; RV32I-NEXT: mv a1, zero -; RV32I-NEXT: lw s8, 12(sp) -; RV32I-NEXT: lw s7, 16(sp) -; RV32I-NEXT: lw s6, 20(sp) -; RV32I-NEXT: lw s5, 24(sp) -; RV32I-NEXT: lw s4, 28(sp) -; RV32I-NEXT: lw s3, 32(sp) -; RV32I-NEXT: lw s2, 36(sp) -; RV32I-NEXT: lw s1, 40(sp) -; RV32I-NEXT: lw ra, 44(sp) -; RV32I-NEXT: addi sp, sp, 48 +; RV32I-NEXT: lw s7, 0(sp) +; RV32I-NEXT: lw s6, 4(sp) +; RV32I-NEXT: lw s5, 8(sp) +; RV32I-NEXT: lw s4, 12(sp) +; RV32I-NEXT: lw s3, 16(sp) +; RV32I-NEXT: lw s2, 20(sp) +; RV32I-NEXT: lw s1, 24(sp) +; RV32I-NEXT: lw ra, 28(sp) +; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret %tmp = call i64 @llvm.cttz.i64(i64 %a, i1 false) ret i64 %tmp @@ -366,9 +354,7 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 @@ -403,9 +389,7 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 @@ -440,9 +424,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 @@ -454,16 +436,15 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind { define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind { ; RV32I-LABEL: test_cttz_i64_zero_undef: ; RV32I: # %bb.0: -; RV32I-NEXT: addi sp, sp, -48 -; RV32I-NEXT: sw ra, 44(sp) -; RV32I-NEXT: sw s1, 40(sp) -; RV32I-NEXT: sw s2, 36(sp) -; RV32I-NEXT: sw s3, 32(sp) -; RV32I-NEXT: sw s4, 28(sp) -; RV32I-NEXT: sw s5, 24(sp) -; RV32I-NEXT: sw s6, 20(sp) -; RV32I-NEXT: sw s7, 16(sp) -; RV32I-NEXT: sw s8, 12(sp) +; RV32I-NEXT: addi sp, sp, -32 +; RV32I-NEXT: sw ra, 28(sp) +; RV32I-NEXT: sw s1, 24(sp) +; RV32I-NEXT: sw s2, 20(sp) +; RV32I-NEXT: sw s3, 16(sp) +; RV32I-NEXT: sw s4, 12(sp) +; RV32I-NEXT: sw s5, 8(sp) +; RV32I-NEXT: sw s6, 4(sp) +; RV32I-NEXT: sw s7, 0(sp) ; RV32I-NEXT: mv s2, a1 ; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: addi a0, a0, -1 @@ -484,13 +465,11 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind { ; RV32I-NEXT: add a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi s4, a1, 257 -; RV32I-NEXT: lui a1, %hi(__mulsi3) -; RV32I-NEXT: addi s7, a1, %lo(__mulsi3) ; RV32I-NEXT: lui a1, 61681 -; RV32I-NEXT: addi s8, a1, -241 -; RV32I-NEXT: and a0, a0, s8 +; RV32I-NEXT: addi s7, a1, -241 +; RV32I-NEXT: and a0, a0, s7 ; RV32I-NEXT: mv a1, s4 -; RV32I-NEXT: jalr s7 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: addi a0, s2, -1 ; RV32I-NEXT: not a1, s2 @@ -504,9 +483,9 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind { ; RV32I-NEXT: add a0, a1, a0 ; RV32I-NEXT: srli a1, a0, 4 ; RV32I-NEXT: add a0, a0, a1 -; RV32I-NEXT: and a0, a0, s8 +; RV32I-NEXT: and a0, a0, s7 ; RV32I-NEXT: mv a1, s4 -; RV32I-NEXT: jalr s7 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: bnez s3, .LBB11_2 ; RV32I-NEXT: # %bb.1: ; RV32I-NEXT: srli a0, a0, 24 @@ -516,16 +495,15 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind { ; RV32I-NEXT: srli a0, s1, 24 ; RV32I-NEXT: .LBB11_3: ; RV32I-NEXT: mv a1, zero -; RV32I-NEXT: lw s8, 12(sp) -; RV32I-NEXT: lw s7, 16(sp) -; RV32I-NEXT: lw s6, 20(sp) -; RV32I-NEXT: lw s5, 24(sp) -; RV32I-NEXT: lw s4, 28(sp) -; RV32I-NEXT: lw s3, 32(sp) -; RV32I-NEXT: lw s2, 36(sp) -; RV32I-NEXT: lw s1, 40(sp) -; RV32I-NEXT: lw ra, 44(sp) -; RV32I-NEXT: addi sp, sp, 48 +; RV32I-NEXT: lw s7, 0(sp) +; RV32I-NEXT: lw s6, 4(sp) +; RV32I-NEXT: lw s5, 8(sp) +; RV32I-NEXT: lw s4, 12(sp) +; RV32I-NEXT: lw s3, 16(sp) +; RV32I-NEXT: lw s2, 20(sp) +; RV32I-NEXT: lw s1, 24(sp) +; RV32I-NEXT: lw ra, 28(sp) +; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret %tmp = call i64 @llvm.cttz.i64(i64 %a, i1 true) ret i64 %tmp @@ -554,9 +532,7 @@ define i32 @test_ctpop_i32(i32 %a) nounwind { ; RV32I-NEXT: and a0, a0, a1 ; RV32I-NEXT: lui a1, 4112 ; RV32I-NEXT: addi a1, a1, 257 -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: srli a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/byval.ll b/llvm/test/CodeGen/RISCV/byval.ll index 943983aa819..ea7e5640b8d 100644 --- a/llvm/test/CodeGen/RISCV/byval.ll +++ b/llvm/test/CodeGen/RISCV/byval.ll @@ -34,10 +34,8 @@ define void @caller() nounwind { ; RV32I-NEXT: lui a0, %hi(foo) ; RV32I-NEXT: lw a0, %lo(foo)(a0) ; RV32I-NEXT: sw a0, 12(sp) -; RV32I-NEXT: lui a0, %hi(callee) -; RV32I-NEXT: addi a1, a0, %lo(callee) ; RV32I-NEXT: addi a0, sp, 12 -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call callee ; RV32I-NEXT: lw ra, 28(sp) ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll b/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll index 8f921b630f0..6609ab2008e 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll @@ -16,9 +16,7 @@ define void @pass_uint8_as_uint8(i8 zeroext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(receive_uint8) -; RV32I-NEXT: addi a1, a1, %lo(receive_uint8) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call receive_uint8 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -33,9 +31,7 @@ define zeroext i8 @ret_callresult_uint8_as_uint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a0, %hi(return_uint8) -; RV32I-NEXT: addi a0, a0, %lo(return_uint8) -; RV32I-NEXT: jalr a0 +; RV32I-NEXT: call return_uint8 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -59,11 +55,9 @@ define void @pass_uint8_as_sint8(i8 zeroext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(receive_sint8) -; RV32I-NEXT: addi a1, a1, %lo(receive_sint8) ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call receive_sint8 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -77,9 +71,7 @@ define signext i8 @ret_callresult_uint8_as_sint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a0, %hi(return_uint8) -; RV32I-NEXT: addi a0, a0, %lo(return_uint8) -; RV32I-NEXT: jalr a0 +; RV32I-NEXT: call return_uint8 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) @@ -104,9 +96,7 @@ define void @pass_uint8_as_anyint32(i8 zeroext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(receive_anyint32) -; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call receive_anyint32 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -120,9 +110,7 @@ define signext i32 @ret_callresult_uint8_as_anyint32() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a0, %hi(return_uint8) -; RV32I-NEXT: addi a0, a0, %lo(return_uint8) -; RV32I-NEXT: jalr a0 +; RV32I-NEXT: call return_uint8 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -145,9 +133,7 @@ define void @pass_sint8_as_uint8(i8 signext %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: andi a0, a0, 255 -; RV32I-NEXT: lui a1, %hi(receive_uint8) -; RV32I-NEXT: addi a1, a1, %lo(receive_uint8) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call receive_uint8 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -162,9 +148,7 @@ define zeroext i8 @ret_callresult_sint8_as_uint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a0, %hi(return_sint8) -; RV32I-NEXT: addi a0, a0, %lo(return_sint8) -; RV32I-NEXT: jalr a0 +; RV32I-NEXT: call return_sint8 ; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 @@ -185,9 +169,7 @@ define void @pass_sint8_as_sint8(i8 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(receive_sint8) -; RV32I-NEXT: addi a1, a1, %lo(receive_sint8) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call receive_sint8 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -200,9 +182,7 @@ define signext i8 @ret_callresult_sint8_as_sint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a0, %hi(return_sint8) -; RV32I-NEXT: addi a0, a0, %lo(return_sint8) -; RV32I-NEXT: jalr a0 +; RV32I-NEXT: call return_sint8 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -223,9 +203,7 @@ define void @pass_sint8_as_anyint32(i8 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(receive_anyint32) -; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call receive_anyint32 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -239,9 +217,7 @@ define signext i32 @ret_callresult_sint8_as_anyint32() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a0, %hi(return_sint8) -; RV32I-NEXT: addi a0, a0, %lo(return_sint8) -; RV32I-NEXT: jalr a0 +; RV32I-NEXT: call return_sint8 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -265,9 +241,7 @@ define void @pass_anyint32_as_uint8(i32 signext %a) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: andi a0, a0, 255 -; RV32I-NEXT: lui a1, %hi(receive_uint8) -; RV32I-NEXT: addi a1, a1, %lo(receive_uint8) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call receive_uint8 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -283,9 +257,7 @@ define zeroext i8 @ret_callresult_anyint32_as_uint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a0, %hi(return_anyint32) -; RV32I-NEXT: addi a0, a0, %lo(return_anyint32) -; RV32I-NEXT: jalr a0 +; RV32I-NEXT: call return_anyint32 ; RV32I-NEXT: andi a0, a0, 255 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 @@ -310,11 +282,9 @@ define void @pass_anyint32_as_sint8(i32 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(receive_sint8) -; RV32I-NEXT: addi a1, a1, %lo(receive_sint8) ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call receive_sint8 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -328,9 +298,7 @@ define signext i8 @ret_callresult_anyint32_as_sint8() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a0, %hi(return_anyint32) -; RV32I-NEXT: addi a0, a0, %lo(return_anyint32) -; RV32I-NEXT: jalr a0 +; RV32I-NEXT: call return_anyint32 ; RV32I-NEXT: slli a0, a0, 24 ; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: lw ra, 12(sp) @@ -353,9 +321,7 @@ define void @pass_anyint32_as_anyint32(i32 signext %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(receive_anyint32) -; RV32I-NEXT: addi a1, a1, %lo(receive_anyint32) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call receive_anyint32 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -368,9 +334,7 @@ define signext i32 @ret_callresult_anyint32_as_anyint32() nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a0, %hi(return_anyint32) -; RV32I-NEXT: addi a0, a0, %lo(return_anyint32) -; RV32I-NEXT: jalr a0 +; RV32I-NEXT: call return_anyint32 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/calling-conv.ll b/llvm/test/CodeGen/RISCV/calling-conv.ll index 31e9c93a9ea..7338a59c28e 100644 --- a/llvm/test/CodeGen/RISCV/calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/calling-conv.ll @@ -23,11 +23,9 @@ define i32 @callee_scalars(i32 %a, i64 %b, i32 %c, i32 %d, double %e) nounwind { ; RV32I-FPELIM-NEXT: mv s2, a3 ; RV32I-FPELIM-NEXT: mv s3, a1 ; RV32I-FPELIM-NEXT: mv s4, a0 -; RV32I-FPELIM-NEXT: lui a0, %hi(__fixdfsi) -; RV32I-FPELIM-NEXT: addi a2, a0, %lo(__fixdfsi) ; RV32I-FPELIM-NEXT: mv a0, a5 ; RV32I-FPELIM-NEXT: mv a1, a6 -; RV32I-FPELIM-NEXT: jalr a2 +; RV32I-FPELIM-NEXT: call __fixdfsi ; RV32I-FPELIM-NEXT: add a1, s4, s3 ; RV32I-FPELIM-NEXT: add a1, a1, s2 ; RV32I-FPELIM-NEXT: add a1, a1, s1 @@ -54,11 +52,9 @@ define i32 @callee_scalars(i32 %a, i64 %b, i32 %c, i32 %d, double %e) nounwind { ; RV32I-WITHFP-NEXT: mv s2, a3 ; RV32I-WITHFP-NEXT: mv s3, a1 ; RV32I-WITHFP-NEXT: mv s4, a0 -; RV32I-WITHFP-NEXT: lui a0, %hi(__fixdfsi) -; RV32I-WITHFP-NEXT: addi a2, a0, %lo(__fixdfsi) ; RV32I-WITHFP-NEXT: mv a0, a5 ; RV32I-WITHFP-NEXT: mv a1, a6 -; RV32I-WITHFP-NEXT: jalr a2 +; RV32I-WITHFP-NEXT: call __fixdfsi ; RV32I-WITHFP-NEXT: add a1, s4, s3 ; RV32I-WITHFP-NEXT: add a1, a1, s2 ; RV32I-WITHFP-NEXT: add a1, a1, s1 @@ -85,8 +81,6 @@ define i32 @caller_scalars() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_scalars) -; RV32I-FPELIM-NEXT: addi a7, a0, %lo(callee_scalars) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a3, zero, 3 @@ -94,7 +88,7 @@ define i32 @caller_scalars() nounwind { ; RV32I-FPELIM-NEXT: lui a6, 262464 ; RV32I-FPELIM-NEXT: mv a2, zero ; RV32I-FPELIM-NEXT: mv a5, zero -; RV32I-FPELIM-NEXT: jalr a7 +; RV32I-FPELIM-NEXT: call callee_scalars ; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -105,8 +99,6 @@ define i32 @caller_scalars() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_scalars) -; RV32I-WITHFP-NEXT: addi a7, a0, %lo(callee_scalars) ; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a3, zero, 3 @@ -114,7 +106,7 @@ define i32 @caller_scalars() nounwind { ; RV32I-WITHFP-NEXT: lui a6, 262464 ; RV32I-WITHFP-NEXT: mv a2, zero ; RV32I-WITHFP-NEXT: mv a5, zero -; RV32I-WITHFP-NEXT: jalr a7 +; RV32I-WITHFP-NEXT: call callee_scalars ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -195,11 +187,9 @@ define i32 @caller_large_scalars() nounwind { ; RV32I-FPELIM-NEXT: sw zero, 28(sp) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: sw a0, 24(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars) -; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_large_scalars) ; RV32I-FPELIM-NEXT: addi a0, sp, 24 ; RV32I-FPELIM-NEXT: mv a1, sp -; RV32I-FPELIM-NEXT: jalr a2 +; RV32I-FPELIM-NEXT: call callee_large_scalars ; RV32I-FPELIM-NEXT: lw ra, 44(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 48 ; RV32I-FPELIM-NEXT: ret @@ -220,11 +210,9 @@ define i32 @caller_large_scalars() nounwind { ; RV32I-WITHFP-NEXT: sw zero, -20(s0) ; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: sw a0, -24(s0) -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars) -; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_large_scalars) ; RV32I-WITHFP-NEXT: addi a0, s0, -24 ; RV32I-WITHFP-NEXT: addi a1, s0, -48 -; RV32I-WITHFP-NEXT: jalr a2 +; RV32I-WITHFP-NEXT: call callee_large_scalars ; RV32I-WITHFP-NEXT: lw s0, 40(sp) ; RV32I-WITHFP-NEXT: lw ra, 44(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 48 @@ -312,8 +300,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-FPELIM-NEXT: sw zero, 44(sp) ; RV32I-FPELIM-NEXT: addi a0, zero, 8 ; RV32I-FPELIM-NEXT: sw a0, 40(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs) -; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a2, zero, 3 @@ -322,7 +308,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-FPELIM-NEXT: addi a5, zero, 6 ; RV32I-FPELIM-NEXT: addi a6, zero, 7 ; RV32I-FPELIM-NEXT: addi a7, sp, 40 -; RV32I-FPELIM-NEXT: jalr t0 +; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs ; RV32I-FPELIM-NEXT: lw ra, 60(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: ret @@ -347,8 +333,6 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-WITHFP-NEXT: sw zero, -20(s0) ; RV32I-WITHFP-NEXT: addi a0, zero, 8 ; RV32I-WITHFP-NEXT: sw a0, -24(s0) -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs) -; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs) ; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a2, zero, 3 @@ -357,7 +341,7 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind { ; RV32I-WITHFP-NEXT: addi a5, zero, 6 ; RV32I-WITHFP-NEXT: addi a6, zero, 7 ; RV32I-WITHFP-NEXT: addi a7, s0, -24 -; RV32I-WITHFP-NEXT: jalr t0 +; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs ; RV32I-WITHFP-NEXT: lw s0, 56(sp) ; RV32I-WITHFP-NEXT: lw ra, 60(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 64 @@ -377,10 +361,8 @@ define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind { ; RV32I-FPELIM-NEXT: sw ra, 28(sp) ; RV32I-FPELIM-NEXT: mv a2, a1 ; RV32I-FPELIM-NEXT: mv a1, a0 -; RV32I-FPELIM-NEXT: lui a0, %hi(__floatditf) -; RV32I-FPELIM-NEXT: addi a3, a0, %lo(__floatditf) ; RV32I-FPELIM-NEXT: addi a0, sp, 8 -; RV32I-FPELIM-NEXT: jalr a3 +; RV32I-FPELIM-NEXT: call __floatditf ; RV32I-FPELIM-NEXT: lw a0, 8(sp) ; RV32I-FPELIM-NEXT: lw ra, 28(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 32 @@ -394,10 +376,8 @@ define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind { ; RV32I-WITHFP-NEXT: addi s0, sp, 32 ; RV32I-WITHFP-NEXT: mv a2, a1 ; RV32I-WITHFP-NEXT: mv a1, a0 -; RV32I-WITHFP-NEXT: lui a0, %hi(__floatditf) -; RV32I-WITHFP-NEXT: addi a3, a0, %lo(__floatditf) ; RV32I-WITHFP-NEXT: addi a0, s0, -24 -; RV32I-WITHFP-NEXT: jalr a3 +; RV32I-WITHFP-NEXT: call __floatditf ; RV32I-WITHFP-NEXT: lw a0, -24(s0) ; RV32I-WITHFP-NEXT: lw s0, 24(sp) ; RV32I-WITHFP-NEXT: lw ra, 28(sp) @@ -481,8 +461,6 @@ define i32 @caller_many_scalars() nounwind { ; RV32I-FPELIM-NEXT: addi a0, zero, 8 ; RV32I-FPELIM-NEXT: sw a0, 4(sp) ; RV32I-FPELIM-NEXT: sw zero, 0(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_many_scalars) -; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_many_scalars) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a1, zero, 2 ; RV32I-FPELIM-NEXT: addi a2, zero, 3 @@ -491,7 +469,7 @@ define i32 @caller_many_scalars() nounwind { ; RV32I-FPELIM-NEXT: addi a6, zero, 6 ; RV32I-FPELIM-NEXT: addi a7, zero, 7 ; RV32I-FPELIM-NEXT: mv a4, zero -; RV32I-FPELIM-NEXT: jalr t0 +; RV32I-FPELIM-NEXT: call callee_many_scalars ; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -505,8 +483,6 @@ define i32 @caller_many_scalars() nounwind { ; RV32I-WITHFP-NEXT: addi a0, zero, 8 ; RV32I-WITHFP-NEXT: sw a0, 4(sp) ; RV32I-WITHFP-NEXT: sw zero, 0(sp) -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_many_scalars) -; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_many_scalars) ; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a1, zero, 2 ; RV32I-WITHFP-NEXT: addi a2, zero, 3 @@ -515,7 +491,7 @@ define i32 @caller_many_scalars() nounwind { ; RV32I-WITHFP-NEXT: addi a6, zero, 6 ; RV32I-WITHFP-NEXT: addi a7, zero, 7 ; RV32I-WITHFP-NEXT: mv a4, zero -; RV32I-WITHFP-NEXT: jalr t0 +; RV32I-WITHFP-NEXT: call callee_many_scalars ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -559,11 +535,9 @@ define i32 @caller_small_coerced_struct() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_coerced_struct) -; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_small_coerced_struct) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a1, zero, 2 -; RV32I-FPELIM-NEXT: jalr a2 +; RV32I-FPELIM-NEXT: call callee_small_coerced_struct ; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -574,11 +548,9 @@ define i32 @caller_small_coerced_struct() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_coerced_struct) -; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_small_coerced_struct) ; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a1, zero, 2 -; RV32I-WITHFP-NEXT: jalr a2 +; RV32I-WITHFP-NEXT: call callee_small_coerced_struct ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -637,10 +609,8 @@ define i32 @caller_large_struct() nounwind { ; RV32I-FPELIM-NEXT: addi a0, zero, 4 ; RV32I-FPELIM-NEXT: sw a0, 36(sp) ; RV32I-FPELIM-NEXT: sw a0, 20(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_struct) -; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_struct) ; RV32I-FPELIM-NEXT: addi a0, sp, 8 -; RV32I-FPELIM-NEXT: jalr a1 +; RV32I-FPELIM-NEXT: call callee_large_struct ; RV32I-FPELIM-NEXT: lw ra, 44(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 48 ; RV32I-FPELIM-NEXT: ret @@ -663,10 +633,8 @@ define i32 @caller_large_struct() nounwind { ; RV32I-WITHFP-NEXT: addi a0, zero, 4 ; RV32I-WITHFP-NEXT: sw a0, -12(s0) ; RV32I-WITHFP-NEXT: sw a0, -28(s0) -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_struct) -; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_struct) ; RV32I-WITHFP-NEXT: addi a0, s0, -40 -; RV32I-WITHFP-NEXT: jalr a1 +; RV32I-WITHFP-NEXT: call callee_large_struct ; RV32I-WITHFP-NEXT: lw s0, 40(sp) ; RV32I-WITHFP-NEXT: lw ra, 44(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 48 @@ -772,8 +740,6 @@ define void @caller_aligned_stack() nounwind { ; RV32I-FPELIM-NEXT: sw a0, 32(sp) ; RV32I-FPELIM-NEXT: lui a0, 688509 ; RV32I-FPELIM-NEXT: addi a5, a0, -2048 -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_aligned_stack) -; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_aligned_stack) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a1, zero, 11 ; RV32I-FPELIM-NEXT: addi a2, sp, 32 @@ -781,7 +747,7 @@ define void @caller_aligned_stack() nounwind { ; RV32I-FPELIM-NEXT: addi a4, zero, 13 ; RV32I-FPELIM-NEXT: addi a6, zero, 4 ; RV32I-FPELIM-NEXT: addi a7, zero, 14 -; RV32I-FPELIM-NEXT: jalr t0 +; RV32I-FPELIM-NEXT: call callee_aligned_stack ; RV32I-FPELIM-NEXT: lw ra, 60(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: ret @@ -820,8 +786,6 @@ define void @caller_aligned_stack() nounwind { ; RV32I-WITHFP-NEXT: sw a0, -32(s0) ; RV32I-WITHFP-NEXT: lui a0, 688509 ; RV32I-WITHFP-NEXT: addi a5, a0, -2048 -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_aligned_stack) -; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_aligned_stack) ; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a1, zero, 11 ; RV32I-WITHFP-NEXT: addi a2, s0, -32 @@ -829,7 +793,7 @@ define void @caller_aligned_stack() nounwind { ; RV32I-WITHFP-NEXT: addi a4, zero, 13 ; RV32I-WITHFP-NEXT: addi a6, zero, 4 ; RV32I-WITHFP-NEXT: addi a7, zero, 14 -; RV32I-WITHFP-NEXT: jalr t0 +; RV32I-WITHFP-NEXT: call callee_aligned_stack ; RV32I-WITHFP-NEXT: lw s0, 56(sp) ; RV32I-WITHFP-NEXT: lw ra, 60(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 64 @@ -872,18 +836,18 @@ define i32 @caller_small_scalar_ret() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_scalar_ret) -; RV32I-FPELIM-NEXT: addi a0, a0, %lo(callee_small_scalar_ret) -; RV32I-FPELIM-NEXT: jalr a0 -; RV32I-FPELIM-NEXT: lui a2, 56 -; RV32I-FPELIM-NEXT: addi a2, a2, 580 -; RV32I-FPELIM-NEXT: xor a1, a1, a2 +; RV32I-FPELIM-NEXT: sw s1, 8(sp) +; RV32I-FPELIM-NEXT: lui a0, 56 +; RV32I-FPELIM-NEXT: addi s1, a0, 580 +; RV32I-FPELIM-NEXT: call callee_small_scalar_ret +; RV32I-FPELIM-NEXT: xor a1, a1, s1 ; RV32I-FPELIM-NEXT: lui a2, 200614 ; RV32I-FPELIM-NEXT: addi a2, a2, 647 ; RV32I-FPELIM-NEXT: xor a0, a0, a2 ; RV32I-FPELIM-NEXT: or a0, a0, a1 ; RV32I-FPELIM-NEXT: xor a0, a0, zero ; RV32I-FPELIM-NEXT: seqz a0, a0 +; RV32I-FPELIM-NEXT: lw s1, 8(sp) ; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -893,19 +857,19 @@ define i32 @caller_small_scalar_ret() nounwind { ; RV32I-WITHFP-NEXT: addi sp, sp, -16 ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) +; RV32I-WITHFP-NEXT: sw s1, 4(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_scalar_ret) -; RV32I-WITHFP-NEXT: addi a0, a0, %lo(callee_small_scalar_ret) -; RV32I-WITHFP-NEXT: jalr a0 -; RV32I-WITHFP-NEXT: lui a2, 56 -; RV32I-WITHFP-NEXT: addi a2, a2, 580 -; RV32I-WITHFP-NEXT: xor a1, a1, a2 +; RV32I-WITHFP-NEXT: lui a0, 56 +; RV32I-WITHFP-NEXT: addi s1, a0, 580 +; RV32I-WITHFP-NEXT: call callee_small_scalar_ret +; RV32I-WITHFP-NEXT: xor a1, a1, s1 ; RV32I-WITHFP-NEXT: lui a2, 200614 ; RV32I-WITHFP-NEXT: addi a2, a2, 647 ; RV32I-WITHFP-NEXT: xor a0, a0, a2 ; RV32I-WITHFP-NEXT: or a0, a0, a1 ; RV32I-WITHFP-NEXT: xor a0, a0, zero ; RV32I-WITHFP-NEXT: seqz a0, a0 +; RV32I-WITHFP-NEXT: lw s1, 4(sp) ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -945,9 +909,7 @@ define i32 @caller_small_struct_ret() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_struct_ret) -; RV32I-FPELIM-NEXT: addi a0, a0, %lo(callee_small_struct_ret) -; RV32I-FPELIM-NEXT: jalr a0 +; RV32I-FPELIM-NEXT: call callee_small_struct_ret ; RV32I-FPELIM-NEXT: add a0, a0, a1 ; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 16 @@ -959,9 +921,7 @@ define i32 @caller_small_struct_ret() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_struct_ret) -; RV32I-WITHFP-NEXT: addi a0, a0, %lo(callee_small_struct_ret) -; RV32I-WITHFP-NEXT: jalr a0 +; RV32I-WITHFP-NEXT: call callee_small_struct_ret ; RV32I-WITHFP-NEXT: add a0, a0, a1 ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) @@ -1010,10 +970,8 @@ define void @caller_large_scalar_ret() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -32 ; RV32I-FPELIM-NEXT: sw ra, 28(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalar_ret) -; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_scalar_ret) ; RV32I-FPELIM-NEXT: mv a0, sp -; RV32I-FPELIM-NEXT: jalr a1 +; RV32I-FPELIM-NEXT: call callee_large_scalar_ret ; RV32I-FPELIM-NEXT: lw ra, 28(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: ret @@ -1024,10 +982,8 @@ define void @caller_large_scalar_ret() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 28(sp) ; RV32I-WITHFP-NEXT: sw s0, 24(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 32 -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalar_ret) -; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_scalar_ret) ; RV32I-WITHFP-NEXT: addi a0, s0, -32 -; RV32I-WITHFP-NEXT: jalr a1 +; RV32I-WITHFP-NEXT: call callee_large_scalar_ret ; RV32I-WITHFP-NEXT: lw s0, 24(sp) ; RV32I-WITHFP-NEXT: lw ra, 28(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 32 @@ -1085,10 +1041,8 @@ define i32 @caller_large_struct_ret() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -32 ; RV32I-FPELIM-NEXT: sw ra, 28(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_struct_ret) -; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_struct_ret) ; RV32I-FPELIM-NEXT: addi a0, sp, 8 -; RV32I-FPELIM-NEXT: jalr a1 +; RV32I-FPELIM-NEXT: call callee_large_struct_ret ; RV32I-FPELIM-NEXT: lw a0, 20(sp) ; RV32I-FPELIM-NEXT: lw a1, 8(sp) ; RV32I-FPELIM-NEXT: add a0, a1, a0 @@ -1102,10 +1056,8 @@ define i32 @caller_large_struct_ret() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 28(sp) ; RV32I-WITHFP-NEXT: sw s0, 24(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 32 -; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_struct_ret) -; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_struct_ret) ; RV32I-WITHFP-NEXT: addi a0, s0, -24 -; RV32I-WITHFP-NEXT: jalr a1 +; RV32I-WITHFP-NEXT: call callee_large_struct_ret ; RV32I-WITHFP-NEXT: lw a0, -12(s0) ; RV32I-WITHFP-NEXT: lw a1, -24(s0) ; RV32I-WITHFP-NEXT: add a0, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/calls.ll b/llvm/test/CodeGen/RISCV/calls.ll index 8875015e5b3..4ef32fb7afb 100644 --- a/llvm/test/CodeGen/RISCV/calls.ll +++ b/llvm/test/CodeGen/RISCV/calls.ll @@ -9,9 +9,7 @@ define i32 @test_call_external(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(external_function) -; RV32I-NEXT: addi a1, a1, %lo(external_function) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call external_function ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -33,9 +31,7 @@ define i32 @test_call_defined(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(defined_function) -; RV32I-NEXT: addi a1, a1, %lo(defined_function) -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call defined_function ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -77,10 +73,7 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw s1, 8(sp) ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lui a0, %hi(fastcc_function) -; RV32I-NEXT: addi a2, a0, %lo(fastcc_function) -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call fastcc_function ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: lw s1, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) @@ -101,17 +94,14 @@ define i32 @test_call_external_many_args(i32 %a) nounwind { ; RV32I-NEXT: mv s1, a0 ; RV32I-NEXT: sw a0, 4(sp) ; RV32I-NEXT: sw a0, 0(sp) -; RV32I-NEXT: lui a0, %hi(external_many_args) -; RV32I-NEXT: addi t0, a0, %lo(external_many_args) -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: mv a1, s1 -; RV32I-NEXT: mv a2, s1 -; RV32I-NEXT: mv a3, s1 -; RV32I-NEXT: mv a4, s1 -; RV32I-NEXT: mv a5, s1 -; RV32I-NEXT: mv a6, s1 -; RV32I-NEXT: mv a7, s1 -; RV32I-NEXT: jalr t0 +; RV32I-NEXT: mv a1, a0 +; RV32I-NEXT: mv a2, a0 +; RV32I-NEXT: mv a3, a0 +; RV32I-NEXT: mv a4, a0 +; RV32I-NEXT: mv a5, a0 +; RV32I-NEXT: mv a6, a0 +; RV32I-NEXT: mv a7, a0 +; RV32I-NEXT: call external_many_args ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: lw s1, 8(sp) ; RV32I-NEXT: lw ra, 12(sp) @@ -139,8 +129,6 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: sw a0, 4(sp) ; RV32I-NEXT: sw a0, 0(sp) -; RV32I-NEXT: lui a1, %hi(defined_many_args) -; RV32I-NEXT: addi t0, a1, %lo(defined_many_args) ; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a3, a0 @@ -148,7 +136,7 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind { ; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: mv a7, a0 -; RV32I-NEXT: jalr t0 +; RV32I-NEXT: call defined_many_args ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/div.ll b/llvm/test/CodeGen/RISCV/div.ll index 96484459ecc..da9df17ccd4 100644 --- a/llvm/test/CodeGen/RISCV/div.ll +++ b/llvm/test/CodeGen/RISCV/div.ll @@ -9,9 +9,7 @@ define i32 @udiv(i32 %a, i32 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a2, %hi(__udivsi3) -; RV32I-NEXT: addi a2, a2, %lo(__udivsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -29,10 +27,8 @@ define i32 @udiv_constant(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(__udivsi3) -; RV32I-NEXT: addi a2, a1, %lo(__udivsi3) ; RV32I-NEXT: addi a1, zero, 5 -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __udivsi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -67,9 +63,7 @@ define i64 @udiv64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a4, %hi(__udivdi3) -; RV32I-NEXT: addi a4, a4, %lo(__udivdi3) -; RV32I-NEXT: jalr a4 +; RV32I-NEXT: call __udivdi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -78,9 +72,7 @@ define i64 @udiv64(i64 %a, i64 %b) nounwind { ; RV32IM: # %bb.0: ; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: sw ra, 12(sp) -; RV32IM-NEXT: lui a4, %hi(__udivdi3) -; RV32IM-NEXT: addi a4, a4, %lo(__udivdi3) -; RV32IM-NEXT: jalr a4 +; RV32IM-NEXT: call __udivdi3 ; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -93,11 +85,9 @@ define i64 @udiv64_constant(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a2, %hi(__udivdi3) -; RV32I-NEXT: addi a4, a2, %lo(__udivdi3) ; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: mv a3, zero -; RV32I-NEXT: jalr a4 +; RV32I-NEXT: call __udivdi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -106,11 +96,9 @@ define i64 @udiv64_constant(i64 %a) nounwind { ; RV32IM: # %bb.0: ; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: sw ra, 12(sp) -; RV32IM-NEXT: lui a2, %hi(__udivdi3) -; RV32IM-NEXT: addi a4, a2, %lo(__udivdi3) ; RV32IM-NEXT: addi a2, zero, 5 ; RV32IM-NEXT: mv a3, zero -; RV32IM-NEXT: jalr a4 +; RV32IM-NEXT: call __udivdi3 ; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -123,9 +111,7 @@ define i32 @sdiv(i32 %a, i32 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a2, %hi(__divsi3) -; RV32I-NEXT: addi a2, a2, %lo(__divsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -143,10 +129,8 @@ define i32 @sdiv_constant(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(__divsi3) -; RV32I-NEXT: addi a2, a1, %lo(__divsi3) ; RV32I-NEXT: addi a1, zero, 5 -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __divsi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -189,9 +173,7 @@ define i64 @sdiv64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a4, %hi(__divdi3) -; RV32I-NEXT: addi a4, a4, %lo(__divdi3) -; RV32I-NEXT: jalr a4 +; RV32I-NEXT: call __divdi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -200,9 +182,7 @@ define i64 @sdiv64(i64 %a, i64 %b) nounwind { ; RV32IM: # %bb.0: ; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: sw ra, 12(sp) -; RV32IM-NEXT: lui a4, %hi(__divdi3) -; RV32IM-NEXT: addi a4, a4, %lo(__divdi3) -; RV32IM-NEXT: jalr a4 +; RV32IM-NEXT: call __divdi3 ; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret @@ -215,11 +195,9 @@ define i64 @sdiv64_constant(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a2, %hi(__divdi3) -; RV32I-NEXT: addi a4, a2, %lo(__divdi3) ; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: mv a3, zero -; RV32I-NEXT: jalr a4 +; RV32I-NEXT: call __divdi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -228,11 +206,9 @@ define i64 @sdiv64_constant(i64 %a) nounwind { ; RV32IM: # %bb.0: ; RV32IM-NEXT: addi sp, sp, -16 ; RV32IM-NEXT: sw ra, 12(sp) -; RV32IM-NEXT: lui a2, %hi(__divdi3) -; RV32IM-NEXT: addi a4, a2, %lo(__divdi3) ; RV32IM-NEXT: addi a2, zero, 5 ; RV32IM-NEXT: mv a3, zero -; RV32IM-NEXT: jalr a4 +; RV32IM-NEXT: call __divdi3 ; RV32IM-NEXT: lw ra, 12(sp) ; RV32IM-NEXT: addi sp, sp, 16 ; RV32IM-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll index 5d2ce7ed589..d1055c66586 100644 --- a/llvm/test/CodeGen/RISCV/double-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/double-br-fcmp.ll @@ -17,9 +17,7 @@ define void @br_fcmp_false(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB0_2: # %if.else -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp false double %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -47,9 +45,7 @@ define void @br_fcmp_oeq(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB1_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp oeq double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -81,9 +77,7 @@ define void @br_fcmp_oeq_alt(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB2_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp oeq double %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -111,9 +105,7 @@ define void @br_fcmp_ogt(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB3_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp ogt double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -141,9 +133,7 @@ define void @br_fcmp_oge(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB4_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp oge double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -171,9 +161,7 @@ define void @br_fcmp_olt(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB5_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp olt double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -201,9 +189,7 @@ define void @br_fcmp_ole(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB6_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp ole double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -239,9 +225,7 @@ define void @br_fcmp_one(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB7_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp one double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -273,9 +257,7 @@ define void @br_fcmp_ord(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB8_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp ord double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -308,9 +290,7 @@ define void @br_fcmp_ueq(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB9_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp ueq double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -339,9 +319,7 @@ define void @br_fcmp_ugt(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB10_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp ugt double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -370,9 +348,7 @@ define void @br_fcmp_uge(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB11_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp uge double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -401,9 +377,7 @@ define void @br_fcmp_ult(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB12_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp ult double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -432,9 +406,7 @@ define void @br_fcmp_ule(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB13_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp ule double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -463,9 +435,7 @@ define void @br_fcmp_une(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB14_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp une double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -497,9 +467,7 @@ define void @br_fcmp_uno(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB15_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp uno double %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -521,9 +489,7 @@ define void @br_fcmp_true(double %a, double %b) nounwind { ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; RV32IFD-NEXT: .LBB16_2: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort %1 = fcmp true double %a, %b br i1 %1, label %if.then, label %if.else if.else: diff --git a/llvm/test/CodeGen/RISCV/double-calling-conv.ll b/llvm/test/CodeGen/RISCV/double-calling-conv.ll index aa69e6dbe4c..5e9382fdf69 100644 --- a/llvm/test/CodeGen/RISCV/double-calling-conv.ll +++ b/llvm/test/CodeGen/RISCV/double-calling-conv.ll @@ -34,8 +34,6 @@ define double @caller_double_inreg() nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) -; RV32IFD-NEXT: lui a0, %hi(callee_double_inreg) -; RV32IFD-NEXT: addi a4, a0, %lo(callee_double_inreg) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0) ; RV32IFD-NEXT: fld ft0, 0(a0) @@ -48,7 +46,7 @@ define double @caller_double_inreg() nounwind { ; RV32IFD-NEXT: fsd ft0, 0(sp) ; RV32IFD-NEXT: lw a2, 0(sp) ; RV32IFD-NEXT: lw a3, 4(sp) -; RV32IFD-NEXT: jalr a4 +; RV32IFD-NEXT: call callee_double_inreg ; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret @@ -89,8 +87,6 @@ define double @caller_double_split_reg_stack() nounwind { ; RV32IFD-NEXT: lw a7, 16(sp) ; RV32IFD-NEXT: lw a0, 20(sp) ; RV32IFD-NEXT: sw a0, 0(sp) -; RV32IFD-NEXT: lui a0, %hi(callee_double_split_reg_stack) -; RV32IFD-NEXT: addi t0, a0, %lo(callee_double_split_reg_stack) ; RV32IFD-NEXT: lui a0, %hi(.LCPI3_1) ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI3_1) ; RV32IFD-NEXT: fld ft0, 0(a0) @@ -102,7 +98,7 @@ define double @caller_double_split_reg_stack() nounwind { ; RV32IFD-NEXT: addi a3, zero, 3 ; RV32IFD-NEXT: mv a2, zero ; RV32IFD-NEXT: mv a4, zero -; RV32IFD-NEXT: jalr t0 +; RV32IFD-NEXT: call callee_double_split_reg_stack ; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: ret @@ -141,8 +137,6 @@ define double @caller_double_stack() nounwind { ; RV32IFD-NEXT: addi a0, a0, -1311 ; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 8(sp) -; RV32IFD-NEXT: lui a0, %hi(callee_double_stack) -; RV32IFD-NEXT: addi t0, a0, %lo(callee_double_stack) ; RV32IFD-NEXT: addi a0, zero, 1 ; RV32IFD-NEXT: addi a2, zero, 2 ; RV32IFD-NEXT: addi a4, zero, 3 @@ -151,7 +145,7 @@ define double @caller_double_stack() nounwind { ; RV32IFD-NEXT: mv a3, zero ; RV32IFD-NEXT: mv a5, zero ; RV32IFD-NEXT: mv a7, zero -; RV32IFD-NEXT: jalr t0 +; RV32IFD-NEXT: call callee_double_stack ; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-intrinsics.ll b/llvm/test/CodeGen/RISCV/double-intrinsics.ll index cc67472f349..7d80d2cc8e0 100644 --- a/llvm/test/CodeGen/RISCV/double-intrinsics.ll +++ b/llvm/test/CodeGen/RISCV/double-intrinsics.ll @@ -13,9 +13,7 @@ define double @foo(double %a) nounwind { ; RV32IFD: # %bb.0: ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) -; RV32IFD-NEXT: lui a2, %hi(floor) -; RV32IFD-NEXT: addi a2, a2, %lo(floor) -; RV32IFD-NEXT: jalr a2 +; RV32IFD-NEXT: call floor ; RV32IFD-NEXT: lw ra, 12(sp) ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-mem.ll b/llvm/test/CodeGen/RISCV/double-mem.ll index 40aae5bf3d6..c50cd441fbb 100644 --- a/llvm/test/CodeGen/RISCV/double-mem.ll +++ b/llvm/test/CodeGen/RISCV/double-mem.ll @@ -118,10 +118,8 @@ define double @fld_stack(double %a) nounwind { ; RV32IFD-NEXT: sw s2, 20(sp) ; RV32IFD-NEXT: mv s1, a1 ; RV32IFD-NEXT: mv s2, a0 -; RV32IFD-NEXT: lui a0, %hi(notdead) -; RV32IFD-NEXT: addi a1, a0, %lo(notdead) ; RV32IFD-NEXT: addi a0, sp, 8 -; RV32IFD-NEXT: jalr a1 +; RV32IFD-NEXT: call notdead ; RV32IFD-NEXT: sw s2, 0(sp) ; RV32IFD-NEXT: sw s1, 4(sp) ; RV32IFD-NEXT: fld ft0, 0(sp) @@ -156,10 +154,8 @@ define void @fsd_stack(double %a, double %b) nounwind { ; RV32IFD-NEXT: fld ft1, 8(sp) ; RV32IFD-NEXT: fadd.d ft0, ft1, ft0 ; RV32IFD-NEXT: fsd ft0, 16(sp) -; RV32IFD-NEXT: lui a0, %hi(notdead) -; RV32IFD-NEXT: addi a1, a0, %lo(notdead) ; RV32IFD-NEXT: addi a0, sp, 16 -; RV32IFD-NEXT: jalr a1 +; RV32IFD-NEXT: call notdead ; RV32IFD-NEXT: lw ra, 28(sp) ; RV32IFD-NEXT: addi sp, sp, 32 ; RV32IFD-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/double-previous-failure.ll b/llvm/test/CodeGen/RISCV/double-previous-failure.ll index 38840493dc9..3a07e5d5858 100644 --- a/llvm/test/CodeGen/RISCV/double-previous-failure.ll +++ b/llvm/test/CodeGen/RISCV/double-previous-failure.ll @@ -17,21 +17,19 @@ define i32 @main() nounwind { ; RV32IFD: # %bb.0: # %entry ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) -; RV32IFD-NEXT: lui a0, %hi(test) -; RV32IFD-NEXT: addi a2, a0, %lo(test) ; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0) ; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_0) ; RV32IFD-NEXT: fld ft0, 0(a0) ; RV32IFD-NEXT: fsd ft0, 0(sp) ; RV32IFD-NEXT: lw a0, 0(sp) ; RV32IFD-NEXT: lw a1, 4(sp) -; RV32IFD-NEXT: jalr a2 +; RV32IFD-NEXT: call test +; RV32IFD-NEXT: lui a2, %hi(.LCPI1_1) +; RV32IFD-NEXT: addi a2, a2, %lo(.LCPI1_1) +; RV32IFD-NEXT: fld ft1, 0(a2) ; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: fld ft0, 0(sp) -; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1) -; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI1_1) -; RV32IFD-NEXT: fld ft1, 0(a0) ; RV32IFD-NEXT: flt.d a0, ft0, ft1 ; RV32IFD-NEXT: bnez a0, .LBB1_3 ; RV32IFD-NEXT: # %bb.1: # %entry @@ -42,14 +40,10 @@ define i32 @main() nounwind { ; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: beqz a0, .LBB1_3 ; RV32IFD-NEXT: # %bb.2: # %if.end -; RV32IFD-NEXT: lui a0, %hi(exit) -; RV32IFD-NEXT: addi a1, a0, %lo(exit) ; RV32IFD-NEXT: mv a0, zero -; RV32IFD-NEXT: jalr a1 +; RV32IFD-NEXT: call exit ; RV32IFD-NEXT: .LBB1_3: # %if.then -; RV32IFD-NEXT: lui a0, %hi(abort) -; RV32IFD-NEXT: addi a0, a0, %lo(abort) -; RV32IFD-NEXT: jalr a0 +; RV32IFD-NEXT: call abort entry: %call = call double @test(double 2.000000e+00) %cmp = fcmp olt double %call, 2.400000e-01 diff --git a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll index 923b9a8c156..b5c0b991e6c 100644 --- a/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll +++ b/llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll @@ -13,13 +13,11 @@ define double @func(double %d, i32 %n) nounwind { ; RV32IFD-NEXT: beqz a2, .LBB0_2 ; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: addi a2, a2, -1 -; RV32IFD-NEXT: lui a0, %hi(func) -; RV32IFD-NEXT: addi a3, a0, %lo(func) ; RV32IFD-NEXT: fsd ft0, 16(sp) ; RV32IFD-NEXT: lw a0, 16(sp) ; RV32IFD-NEXT: lw a1, 20(sp) ; RV32IFD-NEXT: fsd ft0, 8(sp) -; RV32IFD-NEXT: jalr a3 +; RV32IFD-NEXT: call func ; RV32IFD-NEXT: sw a0, 16(sp) ; RV32IFD-NEXT: sw a1, 20(sp) ; RV32IFD-NEXT: fld ft0, 16(sp) diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll index c4924037911..5804bd0fd1f 100644 --- a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll +++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll @@ -18,9 +18,7 @@ define void @br_fcmp_false(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB0_2: # %if.else -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp false float %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -44,9 +42,7 @@ define void @br_fcmp_oeq(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB1_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp oeq float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -74,9 +70,7 @@ define void @br_fcmp_oeq_alt(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB2_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp oeq float %a, %b br i1 %1, label %if.then, label %if.else if.then: @@ -100,9 +94,7 @@ define void @br_fcmp_ogt(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB3_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp ogt float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -126,9 +118,7 @@ define void @br_fcmp_oge(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB4_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp oge float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -152,9 +142,7 @@ define void @br_fcmp_olt(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB5_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp olt float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -178,9 +166,7 @@ define void @br_fcmp_ole(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB6_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp ole float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -212,9 +198,7 @@ define void @br_fcmp_one(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB7_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp one float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -242,9 +226,7 @@ define void @br_fcmp_ord(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB8_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp ord float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -273,9 +255,7 @@ define void @br_fcmp_ueq(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB9_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp ueq float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -300,9 +280,7 @@ define void @br_fcmp_ugt(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB10_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp ugt float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -327,9 +305,7 @@ define void @br_fcmp_uge(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB11_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp uge float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -354,9 +330,7 @@ define void @br_fcmp_ult(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB12_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp ult float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -381,9 +355,7 @@ define void @br_fcmp_ule(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB13_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp ule float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -408,9 +380,7 @@ define void @br_fcmp_une(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB14_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp une float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -438,9 +408,7 @@ define void @br_fcmp_uno(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB15_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp uno float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -462,9 +430,7 @@ define void @br_fcmp_true(float %a, float %b) nounwind { ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB16_2: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort %1 = fcmp true float %a, %b br i1 %1, label %if.then, label %if.else if.else: @@ -482,35 +448,29 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind { ; RV32IF: # %bb.0: # %entry ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) -; RV32IF-NEXT: sw s1, 8(sp) -; RV32IF-NEXT: lui a0, %hi(dummy) -; RV32IF-NEXT: addi s1, a0, %lo(dummy) ; RV32IF-NEXT: mv a0, zero -; RV32IF-NEXT: jalr s1 +; RV32IF-NEXT: call dummy +; RV32IF-NEXT: lui a1, %hi(.LCPI17_0) +; RV32IF-NEXT: addi a1, a1, %lo(.LCPI17_0) +; RV32IF-NEXT: flw ft1, 0(a1) ; RV32IF-NEXT: fmv.w.x ft0, a0 -; RV32IF-NEXT: lui a0, %hi(.LCPI17_0) -; RV32IF-NEXT: addi a0, a0, %lo(.LCPI17_0) -; RV32IF-NEXT: flw ft1, 0(a0) -; RV32IF-NEXT: fsw ft1, 4(sp) +; RV32IF-NEXT: fsw ft1, 8(sp) ; RV32IF-NEXT: feq.s a0, ft0, ft1 ; RV32IF-NEXT: beqz a0, .LBB17_3 ; RV32IF-NEXT: # %bb.1: # %if.end ; RV32IF-NEXT: mv a0, zero -; RV32IF-NEXT: jalr s1 +; RV32IF-NEXT: call dummy ; RV32IF-NEXT: fmv.w.x ft0, a0 -; RV32IF-NEXT: flw ft1, 4(sp) +; RV32IF-NEXT: flw ft1, 8(sp) ; RV32IF-NEXT: feq.s a0, ft0, ft1 ; RV32IF-NEXT: beqz a0, .LBB17_3 ; RV32IF-NEXT: # %bb.2: # %if.end4 ; RV32IF-NEXT: mv a0, zero -; RV32IF-NEXT: lw s1, 8(sp) ; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; RV32IF-NEXT: .LBB17_3: # %if.then -; RV32IF-NEXT: lui a0, %hi(abort) -; RV32IF-NEXT: addi a0, a0, %lo(abort) -; RV32IF-NEXT: jalr a0 +; RV32IF-NEXT: call abort entry: %call = call float @dummy(float 0.000000e+00) %cmp = fcmp une float %call, 0.000000e+00 diff --git a/llvm/test/CodeGen/RISCV/float-mem.ll b/llvm/test/CodeGen/RISCV/float-mem.ll index 397cccc17ee..23cd2c32509 100644 --- a/llvm/test/CodeGen/RISCV/float-mem.ll +++ b/llvm/test/CodeGen/RISCV/float-mem.ll @@ -92,10 +92,8 @@ define float @flw_stack(float %a) nounwind { ; RV32IF-NEXT: sw ra, 12(sp) ; RV32IF-NEXT: sw s1, 8(sp) ; RV32IF-NEXT: mv s1, a0 -; RV32IF-NEXT: lui a0, %hi(notdead) -; RV32IF-NEXT: addi a1, a0, %lo(notdead) ; RV32IF-NEXT: addi a0, sp, 4 -; RV32IF-NEXT: jalr a1 +; RV32IF-NEXT: call notdead ; RV32IF-NEXT: fmv.w.x ft0, s1 ; RV32IF-NEXT: flw ft1, 4(sp) ; RV32IF-NEXT: fadd.s ft0, ft1, ft0 @@ -121,10 +119,8 @@ define void @fsw_stack(float %a, float %b) nounwind { ; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fadd.s ft0, ft1, ft0 ; RV32IF-NEXT: fsw ft0, 8(sp) -; RV32IF-NEXT: lui a0, %hi(notdead) -; RV32IF-NEXT: addi a1, a0, %lo(notdead) ; RV32IF-NEXT: addi a0, sp, 8 -; RV32IF-NEXT: jalr a1 +; RV32IF-NEXT: call notdead ; RV32IF-NEXT: lw ra, 12(sp) ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/fp128.ll b/llvm/test/CodeGen/RISCV/fp128.ll index b2d07cdd084..636e7f8540c 100644 --- a/llvm/test/CodeGen/RISCV/fp128.ll +++ b/llvm/test/CodeGen/RISCV/fp128.ll @@ -37,11 +37,9 @@ define i32 @test_load_and_cmp() nounwind { ; RV32I-NEXT: lui a0, %hi(x) ; RV32I-NEXT: lw a0, %lo(x)(a0) ; RV32I-NEXT: sw a0, 24(sp) -; RV32I-NEXT: lui a0, %hi(__netf2) -; RV32I-NEXT: addi a2, a0, %lo(__netf2) ; RV32I-NEXT: addi a0, sp, 24 ; RV32I-NEXT: addi a1, sp, 8 -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __netf2 ; RV32I-NEXT: xor a0, a0, zero ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: lw ra, 44(sp) @@ -83,12 +81,10 @@ define i32 @test_add_and_fptosi() nounwind { ; RV32I-NEXT: lui a0, %hi(x) ; RV32I-NEXT: lw a0, %lo(x)(a0) ; RV32I-NEXT: sw a0, 40(sp) -; RV32I-NEXT: lui a0, %hi(__addtf3) -; RV32I-NEXT: addi a3, a0, %lo(__addtf3) ; RV32I-NEXT: addi a0, sp, 56 ; RV32I-NEXT: addi a1, sp, 40 ; RV32I-NEXT: addi a2, sp, 24 -; RV32I-NEXT: jalr a3 +; RV32I-NEXT: call __addtf3 ; RV32I-NEXT: lw a0, 68(sp) ; RV32I-NEXT: sw a0, 20(sp) ; RV32I-NEXT: lw a0, 64(sp) @@ -97,10 +93,8 @@ define i32 @test_add_and_fptosi() nounwind { ; RV32I-NEXT: sw a0, 12(sp) ; RV32I-NEXT: lw a0, 56(sp) ; RV32I-NEXT: sw a0, 8(sp) -; RV32I-NEXT: lui a0, %hi(__fixtfsi) -; RV32I-NEXT: addi a1, a0, %lo(__fixtfsi) ; RV32I-NEXT: addi a0, sp, 8 -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call __fixtfsi ; RV32I-NEXT: lw ra, 76(sp) ; RV32I-NEXT: addi sp, sp, 80 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/frame.ll b/llvm/test/CodeGen/RISCV/frame.ll index 11dc784426e..a1f58095188 100644 --- a/llvm/test/CodeGen/RISCV/frame.ll +++ b/llvm/test/CodeGen/RISCV/frame.ll @@ -16,10 +16,8 @@ define i32 @test() nounwind { ; RV32I-FPELIM-NEXT: sw zero, 16(sp) ; RV32I-FPELIM-NEXT: sw zero, 12(sp) ; RV32I-FPELIM-NEXT: sw zero, 8(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(test1) -; RV32I-FPELIM-NEXT: addi a1, a0, %lo(test1) ; RV32I-FPELIM-NEXT: addi a0, sp, 12 -; RV32I-FPELIM-NEXT: jalr a1 +; RV32I-FPELIM-NEXT: call test1 ; RV32I-FPELIM-NEXT: mv a0, zero ; RV32I-FPELIM-NEXT: lw ra, 28(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 32 @@ -36,10 +34,8 @@ define i32 @test() nounwind { ; RV32I-WITHFP-NEXT: sw zero, -24(s0) ; RV32I-WITHFP-NEXT: sw zero, -28(s0) ; RV32I-WITHFP-NEXT: sw zero, -32(s0) -; RV32I-WITHFP-NEXT: lui a0, %hi(test1) -; RV32I-WITHFP-NEXT: addi a1, a0, %lo(test1) ; RV32I-WITHFP-NEXT: addi a0, s0, -28 -; RV32I-WITHFP-NEXT: jalr a1 +; RV32I-WITHFP-NEXT: call test1 ; RV32I-WITHFP-NEXT: mv a0, zero ; RV32I-WITHFP-NEXT: lw s0, 24(sp) ; RV32I-WITHFP-NEXT: lw ra, 28(sp) diff --git a/llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll b/llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll index ab9e4bf6891..967f2246e56 100644 --- a/llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll +++ b/llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll @@ -46,10 +46,8 @@ define i8* @test_frameaddress_3_alloca() nounwind { ; RV32I-NEXT: sw ra, 108(sp) ; RV32I-NEXT: sw s0, 104(sp) ; RV32I-NEXT: addi s0, sp, 112 -; RV32I-NEXT: lui a0, %hi(notdead) -; RV32I-NEXT: addi a1, a0, %lo(notdead) ; RV32I-NEXT: addi a0, s0, -108 -; RV32I-NEXT: jalr a1 +; RV32I-NEXT: call notdead ; RV32I-NEXT: lw a0, -8(s0) ; RV32I-NEXT: lw a0, -8(a0) ; RV32I-NEXT: lw a0, -8(a0) diff --git a/llvm/test/CodeGen/RISCV/mul.ll b/llvm/test/CodeGen/RISCV/mul.ll index e1b2f6f7c2e..444a75f3751 100644 --- a/llvm/test/CodeGen/RISCV/mul.ll +++ b/llvm/test/CodeGen/RISCV/mul.ll @@ -9,10 +9,8 @@ define i32 @square(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) ; RV32I-NEXT: mv a1, a0 -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -30,9 +28,7 @@ define i32 @mul(i32 %a, i32 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a2, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a2, %lo(__mulsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -50,10 +46,8 @@ define i32 @mul_constant(i32 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a1, %hi(__mulsi3) -; RV32I-NEXT: addi a2, a1, %lo(__mulsi3) ; RV32I-NEXT: addi a1, zero, 5 -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __mulsi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -86,9 +80,7 @@ define i64 @mul64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a4, %hi(__muldi3) -; RV32I-NEXT: addi a4, a4, %lo(__muldi3) -; RV32I-NEXT: jalr a4 +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -111,11 +103,9 @@ define i64 @mul64_constant(i64 %a) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a2, %hi(__muldi3) -; RV32I-NEXT: addi a4, a2, %lo(__muldi3) ; RV32I-NEXT: addi a2, zero, 5 ; RV32I-NEXT: mv a3, zero -; RV32I-NEXT: jalr a4 +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -138,11 +128,9 @@ define i32 @mulhs(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: lui a1, %hi(__muldi3) -; RV32I-NEXT: addi a4, a1, %lo(__muldi3) ; RV32I-NEXT: srai a1, a0, 31 ; RV32I-NEXT: srai a3, a2, 31 -; RV32I-NEXT: jalr a4 +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 @@ -166,11 +154,9 @@ define i32 @mulhu(i32 %a, i32 %b) nounwind { ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) ; RV32I-NEXT: mv a2, a1 -; RV32I-NEXT: lui a1, %hi(__muldi3) -; RV32I-NEXT: addi a4, a1, %lo(__muldi3) ; RV32I-NEXT: mv a1, zero ; RV32I-NEXT: mv a3, zero -; RV32I-NEXT: jalr a4 +; RV32I-NEXT: call __muldi3 ; RV32I-NEXT: mv a0, a1 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rem.ll b/llvm/test/CodeGen/RISCV/rem.ll index f9ef4c9c8e6..f37931f448e 100644 --- a/llvm/test/CodeGen/RISCV/rem.ll +++ b/llvm/test/CodeGen/RISCV/rem.ll @@ -9,9 +9,7 @@ define i32 @urem(i32 %a, i32 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a2, %hi(__umodsi3) -; RV32I-NEXT: addi a2, a2, %lo(__umodsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __umodsi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -29,9 +27,7 @@ define i32 @srem(i32 %a, i32 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a2, %hi(__modsi3) -; RV32I-NEXT: addi a2, a2, %lo(__modsi3) -; RV32I-NEXT: jalr a2 +; RV32I-NEXT: call __modsi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/shifts.ll b/llvm/test/CodeGen/RISCV/shifts.ll index 0a3e07e11b5..4aa66b0b63c 100644 --- a/llvm/test/CodeGen/RISCV/shifts.ll +++ b/llvm/test/CodeGen/RISCV/shifts.ll @@ -10,9 +10,7 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a3, %hi(__lshrdi3) -; RV32I-NEXT: addi a3, a3, %lo(__lshrdi3) -; RV32I-NEXT: jalr a3 +; RV32I-NEXT: call __lshrdi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -25,9 +23,7 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a3, %hi(__ashrdi3) -; RV32I-NEXT: addi a3, a3, %lo(__ashrdi3) -; RV32I-NEXT: jalr a3 +; RV32I-NEXT: call __ashrdi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret @@ -40,9 +36,7 @@ define i64 @shl64(i64 %a, i64 %b) nounwind { ; RV32I: # %bb.0: ; RV32I-NEXT: addi sp, sp, -16 ; RV32I-NEXT: sw ra, 12(sp) -; RV32I-NEXT: lui a3, %hi(__ashldi3) -; RV32I-NEXT: addi a3, a3, %lo(__ashldi3) -; RV32I-NEXT: jalr a3 +; RV32I-NEXT: call __ashldi3 ; RV32I-NEXT: lw ra, 12(sp) ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/vararg.ll b/llvm/test/CodeGen/RISCV/vararg.ll index c930f7d1af6..5d00a0e7f2a 100644 --- a/llvm/test/CodeGen/RISCV/vararg.ll +++ b/llvm/test/CodeGen/RISCV/vararg.ll @@ -192,9 +192,7 @@ define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind { ; RV32I-FPELIM-NEXT: andi a0, a0, -16 ; RV32I-FPELIM-NEXT: sub a0, sp, a0 ; RV32I-FPELIM-NEXT: mv sp, a0 -; RV32I-FPELIM-NEXT: lui a1, %hi(notdead) -; RV32I-FPELIM-NEXT: addi a1, a1, %lo(notdead) -; RV32I-FPELIM-NEXT: jalr a1 +; RV32I-FPELIM-NEXT: call notdead ; RV32I-FPELIM-NEXT: mv a0, s1 ; RV32I-FPELIM-NEXT: addi sp, s0, -16 ; RV32I-FPELIM-NEXT: lw s1, 4(sp) @@ -224,9 +222,7 @@ define i32 @va1_va_arg_alloca(i8* %fmt, ...) nounwind { ; RV32I-WITHFP-NEXT: andi a0, a0, -16 ; RV32I-WITHFP-NEXT: sub a0, sp, a0 ; RV32I-WITHFP-NEXT: mv sp, a0 -; RV32I-WITHFP-NEXT: lui a1, %hi(notdead) -; RV32I-WITHFP-NEXT: addi a1, a1, %lo(notdead) -; RV32I-WITHFP-NEXT: jalr a1 +; RV32I-WITHFP-NEXT: call notdead ; RV32I-WITHFP-NEXT: mv a0, s1 ; RV32I-WITHFP-NEXT: addi sp, s0, -16 ; RV32I-WITHFP-NEXT: lw s1, 4(sp) @@ -264,12 +260,10 @@ define void @va1_caller() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(va1) -; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va1) ; RV32I-FPELIM-NEXT: lui a3, 261888 ; RV32I-FPELIM-NEXT: addi a4, zero, 2 ; RV32I-FPELIM-NEXT: mv a2, zero -; RV32I-FPELIM-NEXT: jalr a0 +; RV32I-FPELIM-NEXT: call va1 ; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -280,12 +274,10 @@ define void @va1_caller() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, %hi(va1) -; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va1) ; RV32I-WITHFP-NEXT: lui a3, 261888 ; RV32I-WITHFP-NEXT: addi a4, zero, 2 ; RV32I-WITHFP-NEXT: mv a2, zero -; RV32I-WITHFP-NEXT: jalr a0 +; RV32I-WITHFP-NEXT: call va1 ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -470,11 +462,9 @@ define void @va2_caller() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(va2) -; RV32I-FPELIM-NEXT: addi a0, a0, %lo(va2) ; RV32I-FPELIM-NEXT: lui a3, 261888 ; RV32I-FPELIM-NEXT: mv a2, zero -; RV32I-FPELIM-NEXT: jalr a0 +; RV32I-FPELIM-NEXT: call va2 ; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -485,11 +475,9 @@ define void @va2_caller() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, %hi(va2) -; RV32I-WITHFP-NEXT: addi a0, a0, %lo(va2) ; RV32I-WITHFP-NEXT: lui a3, 261888 ; RV32I-WITHFP-NEXT: mv a2, zero -; RV32I-WITHFP-NEXT: jalr a0 +; RV32I-WITHFP-NEXT: call va2 ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -538,8 +526,6 @@ define double @va3(i32 %a, double %b, ...) nounwind { ; RV32I-FPELIM-NEXT: sw a3, 12(sp) ; RV32I-FPELIM-NEXT: addi a0, sp, 27 ; RV32I-FPELIM-NEXT: sw a0, 0(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3) -; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3) ; RV32I-FPELIM-NEXT: addi a0, sp, 19 ; RV32I-FPELIM-NEXT: andi a0, a0, -8 ; RV32I-FPELIM-NEXT: lw a4, 0(a0) @@ -548,7 +534,7 @@ define double @va3(i32 %a, double %b, ...) nounwind { ; RV32I-FPELIM-NEXT: mv a0, a1 ; RV32I-FPELIM-NEXT: mv a1, a2 ; RV32I-FPELIM-NEXT: mv a2, a4 -; RV32I-FPELIM-NEXT: jalr a5 +; RV32I-FPELIM-NEXT: call __adddf3 ; RV32I-FPELIM-NEXT: lw ra, 4(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: ret @@ -566,8 +552,6 @@ define double @va3(i32 %a, double %b, ...) nounwind { ; RV32I-WITHFP-NEXT: sw a3, 4(s0) ; RV32I-WITHFP-NEXT: addi a0, s0, 19 ; RV32I-WITHFP-NEXT: sw a0, -12(s0) -; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3) -; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3) ; RV32I-WITHFP-NEXT: addi a0, s0, 11 ; RV32I-WITHFP-NEXT: andi a0, a0, -8 ; RV32I-WITHFP-NEXT: lw a4, 0(a0) @@ -576,7 +560,7 @@ define double @va3(i32 %a, double %b, ...) nounwind { ; RV32I-WITHFP-NEXT: mv a0, a1 ; RV32I-WITHFP-NEXT: mv a1, a2 ; RV32I-WITHFP-NEXT: mv a2, a4 -; RV32I-WITHFP-NEXT: jalr a5 +; RV32I-WITHFP-NEXT: call __adddf3 ; RV32I-WITHFP-NEXT: lw s0, 16(sp) ; RV32I-WITHFP-NEXT: lw ra, 20(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 48 @@ -641,13 +625,11 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind { ; RV32I-FPELIM-NEXT: lw a4, 0(a0) ; RV32I-FPELIM-NEXT: addi a0, a3, 4 ; RV32I-FPELIM-NEXT: sw a0, 0(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(__adddf3) -; RV32I-FPELIM-NEXT: addi a5, a0, %lo(__adddf3) ; RV32I-FPELIM-NEXT: lw a3, 0(a3) ; RV32I-FPELIM-NEXT: mv a0, a1 ; RV32I-FPELIM-NEXT: mv a1, a2 ; RV32I-FPELIM-NEXT: mv a2, a4 -; RV32I-FPELIM-NEXT: jalr a5 +; RV32I-FPELIM-NEXT: call __adddf3 ; RV32I-FPELIM-NEXT: lw ra, 4(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 32 ; RV32I-FPELIM-NEXT: ret @@ -670,13 +652,11 @@ define double @va3_va_arg(i32 %a, double %b, ...) nounwind { ; RV32I-WITHFP-NEXT: lw a4, 0(a0) ; RV32I-WITHFP-NEXT: addi a0, a3, 4 ; RV32I-WITHFP-NEXT: sw a0, -12(s0) -; RV32I-WITHFP-NEXT: lui a0, %hi(__adddf3) -; RV32I-WITHFP-NEXT: addi a5, a0, %lo(__adddf3) ; RV32I-WITHFP-NEXT: lw a3, 0(a3) ; RV32I-WITHFP-NEXT: mv a0, a1 ; RV32I-WITHFP-NEXT: mv a1, a2 ; RV32I-WITHFP-NEXT: mv a2, a4 -; RV32I-WITHFP-NEXT: jalr a5 +; RV32I-WITHFP-NEXT: call __adddf3 ; RV32I-WITHFP-NEXT: lw s0, 16(sp) ; RV32I-WITHFP-NEXT: lw ra, 20(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 48 @@ -712,14 +692,12 @@ define void @va3_caller() nounwind { ; RV32I-FPELIM: # %bb.0: ; RV32I-FPELIM-NEXT: addi sp, sp, -16 ; RV32I-FPELIM-NEXT: sw ra, 12(sp) -; RV32I-FPELIM-NEXT: lui a0, %hi(va3) -; RV32I-FPELIM-NEXT: addi a3, a0, %lo(va3) ; RV32I-FPELIM-NEXT: addi a0, zero, 2 ; RV32I-FPELIM-NEXT: lui a2, 261888 ; RV32I-FPELIM-NEXT: lui a5, 262144 ; RV32I-FPELIM-NEXT: mv a1, zero ; RV32I-FPELIM-NEXT: mv a4, zero -; RV32I-FPELIM-NEXT: jalr a3 +; RV32I-FPELIM-NEXT: call va3 ; RV32I-FPELIM-NEXT: lw ra, 12(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 16 ; RV32I-FPELIM-NEXT: ret @@ -730,14 +708,12 @@ define void @va3_caller() nounwind { ; RV32I-WITHFP-NEXT: sw ra, 12(sp) ; RV32I-WITHFP-NEXT: sw s0, 8(sp) ; RV32I-WITHFP-NEXT: addi s0, sp, 16 -; RV32I-WITHFP-NEXT: lui a0, %hi(va3) -; RV32I-WITHFP-NEXT: addi a3, a0, %lo(va3) ; RV32I-WITHFP-NEXT: addi a0, zero, 2 ; RV32I-WITHFP-NEXT: lui a2, 261888 ; RV32I-WITHFP-NEXT: lui a5, 262144 ; RV32I-WITHFP-NEXT: mv a1, zero ; RV32I-WITHFP-NEXT: mv a4, zero -; RV32I-WITHFP-NEXT: jalr a3 +; RV32I-WITHFP-NEXT: call va3 ; RV32I-WITHFP-NEXT: lw s0, 8(sp) ; RV32I-WITHFP-NEXT: lw ra, 12(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 16 @@ -807,9 +783,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; RV32I-FPELIM-NEXT: sw a0, 4(sp) ; RV32I-FPELIM-NEXT: sw a0, 0(sp) ; RV32I-FPELIM-NEXT: lw s1, 20(sp) -; RV32I-FPELIM-NEXT: lui a1, %hi(notdead) -; RV32I-FPELIM-NEXT: addi a1, a1, %lo(notdead) -; RV32I-FPELIM-NEXT: jalr a1 +; RV32I-FPELIM-NEXT: call notdead ; RV32I-FPELIM-NEXT: lw a0, 4(sp) ; RV32I-FPELIM-NEXT: addi a0, a0, 3 ; RV32I-FPELIM-NEXT: andi a0, a0, -4 @@ -852,9 +826,7 @@ define i32 @va4_va_copy(i32 %argno, ...) nounwind { ; RV32I-WITHFP-NEXT: sw a0, -16(s0) ; RV32I-WITHFP-NEXT: sw a0, -20(s0) ; RV32I-WITHFP-NEXT: lw s1, 4(s0) -; RV32I-WITHFP-NEXT: lui a1, %hi(notdead) -; RV32I-WITHFP-NEXT: addi a1, a1, %lo(notdead) -; RV32I-WITHFP-NEXT: jalr a1 +; RV32I-WITHFP-NEXT: call notdead ; RV32I-WITHFP-NEXT: lw a0, -16(s0) ; RV32I-WITHFP-NEXT: addi a0, a0, 3 ; RV32I-WITHFP-NEXT: andi a0, a0, -4 @@ -1029,15 +1001,13 @@ define void @va5_aligned_stack_caller() nounwind { ; RV32I-FPELIM-NEXT: sw a0, 32(sp) ; RV32I-FPELIM-NEXT: lui a0, 688509 ; RV32I-FPELIM-NEXT: addi a6, a0, -2048 -; RV32I-FPELIM-NEXT: lui a0, %hi(va5_aligned_stack_callee) -; RV32I-FPELIM-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee) ; RV32I-FPELIM-NEXT: addi a0, zero, 1 ; RV32I-FPELIM-NEXT: addi a1, zero, 11 ; RV32I-FPELIM-NEXT: addi a2, sp, 32 ; RV32I-FPELIM-NEXT: addi a3, zero, 12 ; RV32I-FPELIM-NEXT: addi a4, zero, 13 ; RV32I-FPELIM-NEXT: addi a7, zero, 4 -; RV32I-FPELIM-NEXT: jalr a5 +; RV32I-FPELIM-NEXT: call va5_aligned_stack_callee ; RV32I-FPELIM-NEXT: lw ra, 60(sp) ; RV32I-FPELIM-NEXT: addi sp, sp, 64 ; RV32I-FPELIM-NEXT: ret @@ -1076,15 +1046,13 @@ define void @va5_aligned_stack_caller() nounwind { ; RV32I-WITHFP-NEXT: sw a0, -32(s0) ; RV32I-WITHFP-NEXT: lui a0, 688509 ; RV32I-WITHFP-NEXT: addi a6, a0, -2048 -; RV32I-WITHFP-NEXT: lui a0, %hi(va5_aligned_stack_callee) -; RV32I-WITHFP-NEXT: addi a5, a0, %lo(va5_aligned_stack_callee) ; RV32I-WITHFP-NEXT: addi a0, zero, 1 ; RV32I-WITHFP-NEXT: addi a1, zero, 11 ; RV32I-WITHFP-NEXT: addi a2, s0, -32 ; RV32I-WITHFP-NEXT: addi a3, zero, 12 ; RV32I-WITHFP-NEXT: addi a4, zero, 13 ; RV32I-WITHFP-NEXT: addi a7, zero, 4 -; RV32I-WITHFP-NEXT: jalr a5 +; RV32I-WITHFP-NEXT: call va5_aligned_stack_callee ; RV32I-WITHFP-NEXT: lw s0, 56(sp) ; RV32I-WITHFP-NEXT: lw ra, 60(sp) ; RV32I-WITHFP-NEXT: addi sp, sp, 64 |
