diff options
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll | 20 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll | 9 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll | 25 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll | 13 | ||||
| -rw-r--r-- | llvm/test/CodeGen/PowerPC/spe.ll | 542 |
5 files changed, 599 insertions, 10 deletions
diff --git a/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll b/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll index 7fcc5e52c36..442580cf72d 100644 --- a/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll +++ b/llvm/test/CodeGen/PowerPC/2008-10-28-f128-i32.ll @@ -7,27 +7,27 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone { ; CHECK-NEXT: mflr 0 ; CHECK-NEXT: stw 0, 4(1) ; CHECK-NEXT: stwu 1, -464(1) -; CHECK-NEXT: lis 3, .LCPI0_0@ha -; CHECK-NEXT: stfd 27, 424(1) # 8-byte Folded Spill ; CHECK-NEXT: mfcr 12 -; CHECK-NEXT: lfs 27, .LCPI0_0@l(3) +; CHECK-NEXT: lis 3, .LCPI0_0@ha ; CHECK-NEXT: stw 29, 412(1) # 4-byte Folded Spill ; CHECK-NEXT: stw 30, 416(1) # 4-byte Folded Spill +; CHECK-NEXT: stw 12, 408(1) +; CHECK-NEXT: stfd 27, 424(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 28, 432(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 29, 440(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 30, 448(1) # 8-byte Folded Spill ; CHECK-NEXT: stfd 31, 456(1) # 8-byte Folded Spill -; CHECK-NEXT: fcmpu 0, 2, 27 -; CHECK-NEXT: stw 12, 408(1) -; CHECK-NEXT: fcmpu 1, 1, 27 +; CHECK-NEXT: lfs 27, .LCPI0_0@l(3) ; CHECK-NEXT: stfd 2, 376(1) -; CHECK-NEXT: crand 20, 6, 0 ; CHECK-NEXT: stfd 1, 384(1) -; CHECK-NEXT: cror 20, 4, 20 +; CHECK-NEXT: fcmpu 0, 2, 27 ; CHECK-NEXT: lwz 3, 380(1) ; CHECK-NEXT: lwz 4, 376(1) ; CHECK-NEXT: lwz 5, 388(1) ; CHECK-NEXT: lwz 6, 384(1) +; CHECK-NEXT: fcmpu 1, 1, 27 +; CHECK-NEXT: crand 20, 6, 0 +; CHECK-NEXT: cror 20, 4, 20 ; CHECK-NEXT: stw 3, 396(1) ; CHECK-NEXT: stw 4, 392(1) ; CHECK-NEXT: stw 5, 404(1) @@ -293,14 +293,14 @@ define i64 @__fixunstfdi(ppc_fp128 %a) nounwind readnone { ; CHECK-NEXT: .LBB0_15: # %bb3 ; CHECK-NEXT: mr 3, 30 ; CHECK-NEXT: .LBB0_16: # %bb5 -; CHECK-NEXT: lwz 12, 408(1) ; CHECK-NEXT: lfd 31, 456(1) # 8-byte Folded Reload ; CHECK-NEXT: lfd 30, 448(1) # 8-byte Folded Reload -; CHECK-NEXT: mtcrf 32, 12 # cr2 ; CHECK-NEXT: lfd 29, 440(1) # 8-byte Folded Reload ; CHECK-NEXT: lfd 28, 432(1) # 8-byte Folded Reload +; CHECK-NEXT: lwz 12, 408(1) ; CHECK-NEXT: lfd 27, 424(1) # 8-byte Folded Reload ; CHECK-NEXT: lwz 30, 416(1) # 4-byte Folded Reload +; CHECK-NEXT: mtcrf 32, 12 # cr2 ; CHECK-NEXT: lwz 29, 412(1) # 4-byte Folded Reload ; CHECK-NEXT: lwz 0, 468(1) ; CHECK-NEXT: addi 1, 1, 464 diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll b/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll index 5881dc3798a..004b82f09b8 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-cmp-imm.ll @@ -3,13 +3,16 @@ ; When fastisel better supports VSX fix up this test case. ; ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s --check-prefix=ELF64 +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE define void @t1a(float %a) nounwind { entry: ; ELF64: t1a +; SPE: t1a %cmp = fcmp oeq float %a, 0.000000e+00 ; ELF64: addis ; ELF64: lfs ; ELF64: fcmpu +; SPE: efscmpeq br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -25,10 +28,12 @@ declare void @foo() define void @t1b(float %a) nounwind { entry: ; ELF64: t1b +; SPE: t1b %cmp = fcmp oeq float %a, -0.000000e+00 ; ELF64: addis ; ELF64: lfs ; ELF64: fcmpu +; SPE: efscmpeq br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -42,10 +47,12 @@ if.end: ; preds = %if.then, %entry define void @t2a(double %a) nounwind { entry: ; ELF64: t2a +; SPE: t2a %cmp = fcmp oeq double %a, 0.000000e+00 ; ELF64: addis ; ELF64: lfd ; ELF64: fcmpu +; SPE: efdcmpeq br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry @@ -59,10 +66,12 @@ if.end: ; preds = %if.then, %entry define void @t2b(double %a) nounwind { entry: ; ELF64: t2b +; SPE: t2b %cmp = fcmp oeq double %a, -0.000000e+00 ; ELF64: addis ; ELF64: lfd ; ELF64: fcmpu +; SPE: efdcmpeq br i1 %cmp, label %if.then, label %if.end if.then: ; preds = %entry diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll b/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll index 3dd53e7f817..ca34aad7ee1 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-conversion.ll @@ -5,6 +5,7 @@ ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx | FileCheck %s ; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx | FileCheck %s ; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=970 -mattr=-vsx | FileCheck %s --check-prefix=PPC970 +; RUN: llc < %s -O0 -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 -mattr=spe | FileCheck %s --check-prefix=SPE ;; Tests for 970 don't use -fast-isel-abort=1 because we intentionally punt ;; to SelectionDAG in some cases. @@ -42,6 +43,7 @@ entry: ; PPC970: lfd ; PPC970: fcfid ; PPC970: frsp +; SPE: efscfsi store float %conv, float* %b.addr, align 4 ret void } @@ -61,6 +63,8 @@ entry: ; PPC970: lfd ; PPC970: fcfid ; PPC970: frsp +; SPE: extsh +; SPE: efscfsi store float %conv, float* %b.addr, align 4 ret void } @@ -80,6 +84,8 @@ entry: ; PPC970: lfd ; PPC970: fcfid ; PPC970: frsp +; SPE: extsb +; SPE: efscfsi store float %conv, float* %b.addr, align 4 ret void } @@ -99,6 +105,7 @@ entry: ; PPC970: std ; PPC970: lfd ; PPC970: fcfid +; SPE: efdcfsi store double %conv, double* %b.addr, align 8 ret void } @@ -133,6 +140,8 @@ entry: ; PPC970: std ; PPC970: lfd ; PPC970: fcfid +; SPE: extsh +; SPE: efdcfsi store double %conv, double* %b.addr, align 8 ret void } @@ -151,6 +160,8 @@ entry: ; PPC970: std ; PPC970: lfd ; PPC970: fcfid +; SPE: extsb +; SPE: efdcfsi store double %conv, double* %b.addr, align 8 ret void } @@ -185,6 +196,7 @@ entry: ; CHECK: fcfidus ; PPC970-NOT: lfiwzx ; PPC970-NOT: fcfidus +; SPE: efscfui store float %conv, float* %b.addr, align 4 ret void } @@ -204,6 +216,8 @@ entry: ; PPC970: lfd ; PPC970: fcfid ; PPC970: frsp +; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 +; SPE: efscfui store float %conv, float* %b.addr, align 4 ret void } @@ -223,6 +237,8 @@ entry: ; PPC970: lfd ; PPC970: fcfid ; PPC970: frsp +; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 +; SPE: efscfui store float %conv, float* %b.addr, align 4 ret void } @@ -254,6 +270,7 @@ entry: ; CHECKLE: fcfidu ; PPC970-NOT: lfiwzx ; PPC970-NOT: fcfidu +; SPE: efdcfui store double %conv, double* %b.addr, align 8 ret void } @@ -272,6 +289,8 @@ entry: ; PPC970: std ; PPC970: lfd ; PPC970: fcfid +; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16 +; SPE: efdcfui store double %conv, double* %b.addr, align 8 ret void } @@ -290,6 +309,8 @@ entry: ; PPC970: std ; PPC970: lfd ; PPC970: fcfid +; SPE: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24 +; SPE: efdcfui store double %conv, double* %b.addr, align 8 ret void } @@ -308,6 +329,7 @@ entry: ; PPC970: fctiwz ; PPC970: stfd ; PPC970: lwa +; SPE: efsctsi store i32 %conv, i32* %b.addr, align 4 ret void } @@ -340,6 +362,7 @@ entry: ; PPC970: fctiwz ; PPC970: stfd ; PPC970: lwa +; SPE: efdctsi store i32 %conv, i32* %b.addr, align 8 ret void } @@ -374,6 +397,7 @@ entry: ; PPC970: fctidz ; PPC970: stfd ; PPC970: lwz +; SPE: efsctui store i32 %conv, i32* %b.addr, align 4 ret void } @@ -404,6 +428,7 @@ entry: ; PPC970: fctidz ; PPC970: stfd ; PPC970: lwz +; SPE: efdctui store i32 %conv, i32* %b.addr, align 8 ret void } diff --git a/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll b/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll index 5317829c6ce..80a733c5da8 100644 --- a/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll +++ b/llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll @@ -3,6 +3,7 @@ ; When fastisel better supports VSX fix up this test case. ; ; RUN: llc -relocation-model=static < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=-vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 +; RUN: llc -relocation-model=static < %s -O0 -verify-machineinstrs -fast-isel -fast-isel-abort=1 -mattr=spe -mtriple=powerpc-unknown-linux-gnu -mcpu=e500 | FileCheck %s --check-prefix=SPE ; This test verifies that load/store instructions are properly generated, ; and that they pass MI verification. @@ -62,19 +63,25 @@ define i64 @t4() nounwind { define float @t5() nounwind { ; ELF64: t5 +; SPE: t5 %1 = load float, float* @e, align 4 ; ELF64: lfs +; SPE: lwz %2 = fadd float %1, 1.0 ; ELF64: fadds +; SPE: efsadd ret float %2 } define double @t6() nounwind { ; ELF64: t6 +; SPE: t6 %1 = load double, double* @f, align 8 ; ELF64: lfd +; SPE: evldd %2 = fadd double %1, 1.0 ; ELF64: fadd +; SPE: efdadd ret double %2 } @@ -126,19 +133,25 @@ define void @t10(i64 %v) nounwind { define void @t11(float %v) nounwind { ; ELF64: t11 +; SPE: t11 %1 = fadd float %v, 1.0 store float %1, float* @e, align 4 ; ELF64: fadds ; ELF64: stfs +; SPE: efsadd +; SPE: stw ret void } define void @t12(double %v) nounwind { ; ELF64: t12 +; SPE: t12 %1 = fadd double %v, 1.0 store double %1, double* @f, align 8 ; ELF64: fadd ; ELF64: stfd +; SPE: efdadd +; SPE: evstdd ret void } diff --git a/llvm/test/CodeGen/PowerPC/spe.ll b/llvm/test/CodeGen/PowerPC/spe.ll new file mode 100644 index 00000000000..8603f45dabb --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/spe.ll @@ -0,0 +1,542 @@ +; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-unknown-linux-gnu \ +; RUN: -mattr=+spe | FileCheck %s + +declare float @llvm.fabs.float(float) +define float @test_float_abs(float %a) #0 { + entry: + %0 = tail call float @llvm.fabs.float(float %a) + ret float %0 +; CHECK-LABEL: test_float_abs +; CHECK: efsabs 3, 3 +; CHECK: blr +} + +define float @test_fnabs(float %a) #0 { + entry: + %0 = tail call float @llvm.fabs.float(float %a) + %sub = fsub float -0.000000e+00, %0 + ret float %sub +; CHECK-LABEL: @test_fnabs +; CHECK: efsnabs +; CHECK: blr +} + +define float @test_fdiv(float %a, float %b) { +entry: + %v = fdiv float %a, %b + ret float %v + +; CHECK-LABEL: test_fdiv +; CHECK: efsdiv +; CHECK: blr +} + +define float @test_fmul(float %a, float %b) { + entry: + %v = fmul float %a, %b + ret float %v +; CHECK-LABEL @test_fmul +; CHECK: efsmul +; CHECK: blr +} + +define float @test_fadd(float %a, float %b) { + entry: + %v = fadd float %a, %b + ret float %v +; CHECK-LABEL @test_fadd +; CHECK: efsadd +; CHECK: blr +} + +define float @test_fsub(float %a, float %b) { + entry: + %v = fsub float %a, %b + ret float %v +; CHECK-LABEL @test_fsub +; CHECK: efssub +; CHECK: blr +} + +define float @test_fneg(float %a) { + entry: + %v = fsub float -0.0, %a + ret float %v + +; CHECK-LABEL @test_fneg +; CHECK: efsneg +; CHECK: blr +} + +define float @test_dtos(double %a) { + entry: + %v = fptrunc double %a to float + ret float %v +; CHECK-LABEL: test_dtos +; CHECK: efscfd +; CHECK: blr +} + +define i1 @test_fcmpgt(float %a, float %b) { + entry: + %r = fcmp ogt float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpgt +; CHECK: efscmpgt +; CHECK: blr +} + +define i1 @test_fcmpugt(float %a, float %b) { + entry: + %r = fcmp ugt float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpugt +; CHECK: efscmpgt +; CHECK: blr +} + +define i1 @test_fcmple(float %a, float %b) { + entry: + %r = fcmp ole float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmple +; CHECK: efscmpgt +; CHECK: blr +} + +define i1 @test_fcmpule(float %a, float %b) { + entry: + %r = fcmp ule float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpule +; CHECK: efscmpgt +; CHECK: blr +} + +define i1 @test_fcmpeq(float %a, float %b) { + entry: + %r = fcmp oeq float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpeq +; CHECK: efscmpeq +; CHECK: blr +} + +; (un)ordered tests are expanded to une and oeq so verify +define i1 @test_fcmpuno(float %a, float %b) { + entry: + %r = fcmp uno float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpuno +; CHECK: efscmpeq +; CHECK: efscmpeq +; CHECK: crand +; CHECK: blr +} + +define i1 @test_fcmpord(float %a, float %b) { + entry: + %r = fcmp ord float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpord +; CHECK: efscmpeq +; CHECK: efscmpeq +; CHECK: crnand +; CHECK: blr +} + +define i1 @test_fcmpueq(float %a, float %b) { + entry: + %r = fcmp ueq float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpueq +; CHECK: efscmpeq +; CHECK: blr +} + +define i1 @test_fcmpne(float %a, float %b) { + entry: + %r = fcmp one float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpne +; CHECK: efscmpeq +; CHECK: blr +} + +define i1 @test_fcmpune(float %a, float %b) { + entry: + %r = fcmp une float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpune +; CHECK: efscmpeq +; CHECK: blr +} + +define i1 @test_fcmplt(float %a, float %b) { + entry: + %r = fcmp olt float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmplt +; CHECK: efscmplt +; CHECK: blr +} + +define i1 @test_fcmpult(float %a, float %b) { + entry: + %r = fcmp ult float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpult +; CHECK: efscmplt +; CHECK: blr +} + +define i1 @test_fcmpge(float %a, float %b) { + entry: + %r = fcmp oge float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpge +; CHECK: efscmplt +; CHECK: blr +} + +define i1 @test_fcmpuge(float %a, float %b) { + entry: + %r = fcmp uge float %a, %b + ret i1 %r +; CHECK-LABEL: test_fcmpuge +; CHECK: efscmplt +; CHECK: blr +} + +define i32 @test_ftoui(float %a) { + %v = fptoui float %a to i32 + ret i32 %v +; CHECK-LABEL: test_ftoui +; CHECK: efsctuiz +} + +define i32 @test_ftosi(float %a) { + %v = fptosi float %a to i32 + ret i32 %v +; CHECK-LABEL: test_ftosi +; CHECK: efsctsiz +} + +define float @test_ffromui(i32 %a) { + %v = uitofp i32 %a to float + ret float %v +; CHECK-LABEL: test_ffromui +; CHECK: efscfui +} + +define float @test_ffromsi(i32 %a) { + %v = sitofp i32 %a to float + ret float %v +; CHECK-LABEL: test_ffromsi +; CHECK: efscfsi +} + +define i32 @test_fasmconst(float %x) { +entry: + %x.addr = alloca float, align 8 + store float %x, float* %x.addr, align 8 + %0 = load float, float* %x.addr, align 8 + %1 = call i32 asm sideeffect "efsctsi $0, $1", "=f,f"(float %0) + ret i32 %1 +; CHECK-LABEL: test_fasmconst +; Check that it's not loading a double +; CHECK-NOT: evldd +; CHECK: #APP +; CHECK: efsctsi +; CHECK: #NO_APP +} + +; Double tests + +define void @test_double_abs(double * %aa) #0 { + entry: + %0 = load double, double * %aa + %1 = tail call double @llvm.fabs.f64(double %0) #2 + store double %1, double * %aa + ret void +; CHECK-LABEL: test_double_abs +; CHECK: efdabs +; CHECK: blr +} + +; Function Attrs: nounwind readnone +declare double @llvm.fabs.f64(double) #1 + +define void @test_dnabs(double * %aa) #0 { + entry: + %0 = load double, double * %aa + %1 = tail call double @llvm.fabs.f64(double %0) #2 + %sub = fsub double -0.000000e+00, %1 + store double %sub, double * %aa + ret void +} +; CHECK-LABEL: @test_dnabs +; CHECK: efdnabs +; CHECK: blr + +define double @test_ddiv(double %a, double %b) { +entry: + %v = fdiv double %a, %b + ret double %v + +; CHECK-LABEL: test_ddiv +; CHECK: efddiv +; CHECK: blr +} + +define double @test_dmul(double %a, double %b) { + entry: + %v = fmul double %a, %b + ret double %v +; CHECK-LABEL @test_dmul +; CHECK: efdmul +; CHECK: blr +} + +define double @test_dadd(double %a, double %b) { + entry: + %v = fadd double %a, %b + ret double %v +; CHECK-LABEL @test_dadd +; CHECK: efdadd +; CHECK: blr +} + +define double @test_dsub(double %a, double %b) { + entry: + %v = fsub double %a, %b + ret double %v +; CHECK-LABEL @test_dsub +; CHECK: efdsub +; CHECK: blr +} + +define double @test_dneg(double %a) { + entry: + %v = fsub double -0.0, %a + ret double %v + +; CHECK-LABEL @test_dneg +; CHECK: blr +} + +define double @test_stod(float %a) { + entry: + %v = fpext float %a to double + ret double %v +; CHECK-LABEL: test_stod +; CHECK: efdcfs +; CHECK: blr +} + +; (un)ordered tests are expanded to une and oeq so verify +define i1 @test_dcmpuno(double %a, double %b) { + entry: + %r = fcmp uno double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpuno +; CHECK: efdcmpeq +; CHECK: efdcmpeq +; CHECK: crand +; CHECK: blr +} + +define i1 @test_dcmpord(double %a, double %b) { + entry: + %r = fcmp ord double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpord +; CHECK: efdcmpeq +; CHECK: efdcmpeq +; CHECK: crnand +; CHECK: blr +} + +define i1 @test_dcmpgt(double %a, double %b) { + entry: + %r = fcmp ogt double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpgt +; CHECK: efdcmpgt +; CHECK: blr +} + +define i1 @test_dcmpugt(double %a, double %b) { + entry: + %r = fcmp ugt double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpugt +; CHECK: efdcmpgt +; CHECK: blr +} + +define i1 @test_dcmple(double %a, double %b) { + entry: + %r = fcmp ole double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmple +; CHECK: efdcmpgt +; CHECK: blr +} + +define i1 @test_dcmpule(double %a, double %b) { + entry: + %r = fcmp ule double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpule +; CHECK: efdcmpgt +; CHECK: blr +} + +define i1 @test_dcmpeq(double %a, double %b) { + entry: + %r = fcmp oeq double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpeq +; CHECK: efdcmpeq +; CHECK: blr +} + +define i1 @test_dcmpueq(double %a, double %b) { + entry: + %r = fcmp ueq double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpueq +; CHECK: efdcmpeq +; CHECK: blr +} + +define i1 @test_dcmpne(double %a, double %b) { + entry: + %r = fcmp one double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpne +; CHECK: efdcmpeq +; CHECK: blr +} + +define i1 @test_dcmpune(double %a, double %b) { + entry: + %r = fcmp une double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpune +; CHECK: efdcmpeq +; CHECK: blr +} + +define i1 @test_dcmplt(double %a, double %b) { + entry: + %r = fcmp olt double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmplt +; CHECK: efdcmplt +; CHECK: blr +} + +define i1 @test_dcmpult(double %a, double %b) { + entry: + %r = fcmp ult double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpult +; CHECK: efdcmplt +; CHECK: blr +} + +define i1 @test_dcmpge(double %a, double %b) { + entry: + %r = fcmp oge double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpge +; CHECK: efdcmplt +; CHECK: blr +} + +define i1 @test_dcmpuge(double %a, double %b) { + entry: + %r = fcmp uge double %a, %b + ret i1 %r +; CHECK-LABEL: test_dcmpuge +; CHECK: efdcmplt +; CHECK: blr +} + +define double @test_dselect(double %a, double %b, i1 %c) { +entry: + %r = select i1 %c, double %a, double %b + ret double %r +; CHECK-LABEL: test_dselect +; CHECK: andi. +; CHECK: bc +; CHECK: evldd +; CHECK: b +; CHECK: evldd +; CHECK: evstdd +; CHECK: blr +} + +define i32 @test_dtoui(double %a) { +entry: + %v = fptoui double %a to i32 + ret i32 %v +; CHECK-LABEL: test_dtoui +; CHECK: efdctuiz +} + +define i32 @test_dtosi(double %a) { +entry: + %v = fptosi double %a to i32 + ret i32 %v +; CHECK-LABEL: test_dtosi +; CHECK: efdctsiz +} + +define double @test_dfromui(i32 %a) { +entry: + %v = uitofp i32 %a to double + ret double %v +; CHECK-LABEL: test_dfromui +; CHECK: efdcfui +} + +define double @test_dfromsi(i32 %a) { +entry: + %v = sitofp i32 %a to double + ret double %v +; CHECK-LABEL: test_dfromsi +; CHECK: efdcfsi +} + +define i32 @test_dasmconst(double %x) { +entry: + %x.addr = alloca double, align 8 + store double %x, double* %x.addr, align 8 + %0 = load double, double* %x.addr, align 8 + %1 = call i32 asm sideeffect "efdctsi $0, $1", "=d,d"(double %0) + ret i32 %1 +; CHECK-LABEL: test_dasmconst +; CHECK: evldd +; CHECK: #APP +; CHECK: efdctsi +; CHECK: #NO_APP +} + +define double @test_spill(double %a) nounwind { +entry: + %0 = fadd double %a, %a + call void asm sideeffect "","~{r0},~{r3},~{s4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"() nounwind + %1 = fadd double %0, 3.14159 + br label %return + +return: + ret double %1 + +; CHECK-LABEL: test_spill +; CHECK: efdadd +; CHECK: evstdd +; CHECK: evldd +} |
