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-rw-r--r--llvm/test/CodeGen/Mips/fcmp.ll383
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll54
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll51
-rw-r--r--llvm/test/CodeGen/Mips/llvm-ir/select-int.ll112
4 files changed, 565 insertions, 35 deletions
diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll
index 0e44c5bded2..adf0692919a 100644
--- a/llvm/test/CodeGen/Mips/fcmp.ll
+++ b/llvm/test/CodeGen/Mips/fcmp.ll
@@ -12,10 +12,26 @@
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-C
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \
; RUN: FileCheck %s -check-prefix=ALL -check-prefix=64-CMP
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6 \
+; RUN: -check-prefix=MM32R6
+; RUN: llc < %s -march=mips -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM -check-prefix=MMR6 \
+; RUN: -check-prefix=MM64R6
define i32 @false_f32(float %a, float %b) nounwind {
; ALL-LABEL: false_f32:
-; ALL: addiu $2, $zero, 0
+; 32-C: addiu $2, $zero, 0
+
+; 32-CMP: addiu $2, $zero, 0
+
+; 64-C: addiu $2, $zero, 0
+
+; 64-CMP: addiu $2, $zero, 0
+
+; MM-DAG: lui $2, 0
%1 = fcmp false float %a, %b
%2 = zext i1 %1 to i32
@@ -41,6 +57,16 @@ define i32 @oeq_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.eq.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp oeq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -65,6 +91,16 @@ define i32 @ogt_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ule.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ogt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -89,6 +125,16 @@ define i32 @oge_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ult.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp oge float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -113,6 +159,16 @@ define i32 @olt_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.olt.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp olt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -137,6 +193,16 @@ define i32 @ole_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ole.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -163,6 +229,17 @@ define i32 @one_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ueq.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]]
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp one float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -189,6 +266,17 @@ define i32 @ord_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.un.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp ord float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -213,6 +301,16 @@ define i32 @ueq_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ueq.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ueq float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -237,6 +335,16 @@ define i32 @ugt_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ole.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ugt float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -261,6 +369,16 @@ define i32 @uge_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.olt.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp uge float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -285,6 +403,15 @@ define i32 @ult_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ult.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
%1 = fcmp ult float %a, %b
%2 = zext i1 %1 to i32
@@ -310,6 +437,16 @@ define i32 @ule_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ule.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ule float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -336,6 +473,17 @@ define i32 @une_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.eq.s $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp une float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -360,6 +508,16 @@ define i32 @uno_f32(float %a, float %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.un.s $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp uno float %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -367,7 +525,15 @@ define i32 @uno_f32(float %a, float %b) nounwind {
define i32 @true_f32(float %a, float %b) nounwind {
; ALL-LABEL: true_f32:
-; ALL: addiu $2, $zero, 1
+; 32-C: addiu $2, $zero, 1
+
+; 32-CMP: addiu $2, $zero, 1
+
+; 64-C: addiu $2, $zero, 1
+
+; 64-CMP: addiu $2, $zero, 1
+
+; MM-DAG: li16 $2, 1
%1 = fcmp true float %a, %b
%2 = zext i1 %1 to i32
@@ -376,7 +542,15 @@ define i32 @true_f32(float %a, float %b) nounwind {
define i32 @false_f64(double %a, double %b) nounwind {
; ALL-LABEL: false_f64:
-; ALL: addiu $2, $zero, 0
+; 32-C: addiu $2, $zero, 0
+
+; 32-CMP: addiu $2, $zero, 0
+
+; 64-C: addiu $2, $zero, 0
+
+; 64-CMP: addiu $2, $zero, 0
+
+; MM-DAG: lui $2, 0
%1 = fcmp false double %a, %b
%2 = zext i1 %1 to i32
@@ -402,6 +576,16 @@ define i32 @oeq_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.eq.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp oeq double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -426,6 +610,16 @@ define i32 @ogt_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ule.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ogt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -450,6 +644,16 @@ define i32 @oge_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ult.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp oge double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -474,6 +678,16 @@ define i32 @olt_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.olt.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp olt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -498,6 +712,16 @@ define i32 @ole_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ole.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ole double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -524,6 +748,17 @@ define i32 @one_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ueq.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp one double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -550,6 +785,17 @@ define i32 @ord_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.un.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp ord double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -574,6 +820,16 @@ define i32 @ueq_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ueq.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ueq double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -598,6 +854,16 @@ define i32 @ugt_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ole.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ugt double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -622,6 +888,16 @@ define i32 @uge_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.olt.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
+; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp uge double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -646,6 +922,16 @@ define i32 @ult_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ult.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ult double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -670,6 +956,16 @@ define i32 @ule_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.ule.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp ule double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -696,6 +992,17 @@ define i32 @une_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
; 64-CMP-DAG: andi $2, $[[T2]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.eq.d $f12, $f14
+; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: nor $[[T2:[0-9]+]], $[[T1]], $zero
+; MMR6-DAG: andi16 $2, $[[T2]], 1
+
%1 = fcmp une double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -720,6 +1027,16 @@ define i32 @uno_f64(double %a, double %b) nounwind {
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
; 64-CMP-DAG: andi $2, $[[T1]], 1
+; MM32R3-DAG: lui $[[T0:[0-9]+]], 0
+; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1
+; MM32R3-DAG: c.un.d $f12, $f14
+; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0
+
+; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
+; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
+; MMR6-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; MMR6-DAG: andi16 $2, $[[T1]], 1
+
%1 = fcmp uno double %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -727,7 +1044,15 @@ define i32 @uno_f64(double %a, double %b) nounwind {
define i32 @true_f64(double %a, double %b) nounwind {
; ALL-LABEL: true_f64:
-; ALL: addiu $2, $zero, 1
+; 32-C: addiu $2, $zero, 1
+
+; 32-CMP: addiu $2, $zero, 1
+
+; 64-C: addiu $2, $zero, 1
+
+; 64-CMP: addiu $2, $zero, 1
+
+; MM-DAG: li16 $2, 1
%1 = fcmp true double %a, %b
%2 = zext i1 %1 to i32
@@ -765,6 +1090,31 @@ entry:
; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
; 64-CMP-DAG: bnezc $[[T4]],
+; MM32R3-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
+; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0)
+; MM32R3-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
+; MM32R3-DAG: c.ole.s $[[T0]], $[[T2]]
+; MM32R3-DAG: bc1t
+
+; MM32R6-DAG: add.s $[[T0:f[0-9]+]], $f14, $f12
+; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI32_0)
+; MM32R6-DAG: lwc1 $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
+; MM32R6-DAG: cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
+; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3:f[0-9]+]]
+; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
+; MM32R6-DAG: bnez $[[T5]],
+
+; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f32)))
+; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25
+; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32)))
+; MM64R6-DAG: add.s $[[T3:f[0-9]+]], $f13, $f12
+; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI32_0)($[[T2]])
+; MM64R6-DAG: lwc1 $[[T5:f[0-9]+]], %got_ofst($CPI32_0)($[[T4]])
+; MM64R6-DAG: cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
+; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]]
+; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1
+; MM64R6-DAG: bnez $[[T8]],
+
%add = fadd fast float %at, %angle
%cmp = fcmp ogt float %add, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end
@@ -809,6 +1159,31 @@ entry:
; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
; 64-CMP-DAG: bnezc $[[T4]],
+; MM32R3-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
+; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)
+; MM32R3-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
+; MM32R3-DAG: c.ole.d $[[T0]], $[[T2]]
+; MM32R3-DAG: bc1t
+
+; MM32R6-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
+; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)
+; MM32R6-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
+; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
+; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]]
+; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
+; MM32R6-DAG: bnez $[[T5]],
+
+; MM64R6-DAG: lui $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f64)))
+; MM64R6-DAG: daddu $[[T1:[0-9]+]], $[[T0]], $25
+; MM64R6-DAG: daddiu $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64)))
+; MM64R6-DAG: add.d $[[T3:f[0-9]+]], $f13, $f12
+; MM64R6-DAG: ld $[[T4:[0-9]+]], %got_page($CPI33_0)($[[T2]])
+; MM64R6-DAG: ldc1 $[[T5:f[0-9]+]], %got_ofst($CPI33_0)($[[T4]])
+; MM64R6-DAG: cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
+; MM64R6-DAG: mfc1 $[[T7:[0-9]+]], $[[T6]]
+; MM64R6-DAG: andi16 $[[T8:[0-9]+]], $[[T7]], 1
+; MM64R6-DAG: bnez $[[T8]],
+
%add = fadd fast double %at, %angle
%cmp = fcmp ogt double %add, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
index 6067cfb3b1c..3962f9d2f1c 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll
@@ -13,7 +13,7 @@
; RUN: -check-prefix=ALL -check-prefix=CMOV \
; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
+; RUN: -check-prefix=ALL -check-prefix=SEL-32 -check-prefix=32R6
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
@@ -27,7 +27,11 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
+; RUN: -check-prefix=ALL -check-prefix=SEL-64 -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM32R6 -check-prefix=SEL-32
define double @tst_select_i1_double(i1 signext %s, double %x, double %y) {
entry:
@@ -71,6 +75,13 @@ entry:
; SEL-64: mtc1 $4, $f0
; SEL-64: sel.d $f0, $f14, $f13
+
+ ; MM32R3: mtc1 $7, $[[F0:f[0-9]+]]
+ ; MM32R3: mthc1 $6, $[[F0]]
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: ldc1 $f0, 16($sp)
+ ; MM32R3: movn.d $f0, $[[F0]], $[[T0]]
+
%r = select i1 %s, double %x, double %y
ret double %r
}
@@ -112,6 +123,12 @@ entry:
; SEL-64: mtc1 $6, $f0
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: lw $[[T0:[0-9]+]], 16($sp)
+ ; MM32R3: andi16 $[[T1:[0-9]+]], $[[T0:[0-9]+]], 1
+ ; MM32R3: movn.d $f14, $f12, $[[T1]]
+ ; MM32R3: mov.d $f0, $f14
+
%r = select i1 %s, double %x, double %y
ret double %r
}
@@ -143,6 +160,11 @@ entry:
; SEL-64: cmp.lt.d $f0, $f12, $f13
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.olt.d $f12, $f14
+ ; MM32R3: movt.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp olt double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
@@ -175,6 +197,11 @@ entry:
; SEL-64: cmp.le.d $f0, $f12, $f13
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.ole.d $f12, $f14
+ ; MM32R3: movt.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp ole double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
@@ -207,6 +234,11 @@ entry:
; SEL-64: cmp.lt.d $f0, $f13, $f12
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.ule.d $f12, $f14
+ ; MM32R3: movf.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp ogt double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
@@ -239,6 +271,11 @@ entry:
; SEL-64: cmp.le.d $f0, $f13, $f12
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.ult.d $f12, $f14
+ ; MM32R3: movf.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp oge double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
@@ -271,6 +308,11 @@ entry:
; SEL-64: cmp.eq.d $f0, $f12, $f13
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.eq.d $f12, $f14
+ ; MM32R3: movt.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp oeq double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
@@ -296,7 +338,8 @@ entry:
; SEL-32: cmp.ueq.d $f0, $f12, $f14
; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
- ; SEL-32: not $[[T0]], $[[T0]]
+ ; 32R6: not $[[T0]], $[[T0]]
+ ; MM32R6: nor $[[T0]], $[[T0]], $zero
; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
; SEL-32: sel.d $f0, $f14, $f12
@@ -309,6 +352,11 @@ entry:
; SEL-64: not $[[T0]], $[[T0]]
; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
; SEL-64: sel.d $f0, $f13, $f12
+
+ ; MM32R3: c.ueq.d $f12, $f14
+ ; MM32R3: movf.d $f14, $f12, $fcc0
+ ; MM32R3: mov.d $f0, $f14
+
%s = fcmp one double %x, %y
%r = select i1 %s, double %x, double %y
ret double %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
index 173055a5ef5..3816727e0d3 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-flt.ll
@@ -13,7 +13,7 @@
; RUN: -check-prefix=ALL -check-prefix=CMOV \
; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
+; RUN: -check-prefix=ALL -check-prefix=SEL-32 -check-prefix=32R6
; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
@@ -27,7 +27,11 @@
; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
-; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
+; RUN: -check-prefix=ALL -check-prefix=SEL-64 -check-prefix=64R6
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM32R6 -check-prefix=SEL-32
define float @tst_select_i1_float(i1 signext %s, float %x, float %y) {
entry:
@@ -60,6 +64,12 @@ entry:
; SEL-64: mtc1 $4, $f0
; SEL-64: sel.s $f0, $f14, $f13
+
+ ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]]
+ ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]]
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: movn.s $f0, $[[F1]], $[[T0]]
+
%r = select i1 %s, float %x, float %y
ret float %r
}
@@ -91,6 +101,11 @@ entry:
; SEL-64: mtc1 $6, $f0
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $6, 1
+ ; MM32R3: movn.s $[[F0:f[0-9]+]], $f12, $[[T0]]
+ ; MM32R3: mov.s $f0, $[[F0]]
+
%r = select i1 %s, float %x, float %y
ret float %r
}
@@ -122,6 +137,11 @@ entry:
; SEL-64: cmp.lt.s $f0, $f12, $f13
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: c.olt.s $f12, $f14
+ ; MM32R3: movt.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp olt float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
@@ -154,6 +174,11 @@ entry:
; SEL-64: cmp.le.s $f0, $f12, $f13
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: c.ole.s $f12, $f14
+ ; MM32R3: movt.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp ole float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
@@ -186,6 +211,11 @@ entry:
; SEL-64: cmp.lt.s $f0, $f13, $f12
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: c.ule.s $f12, $f14
+ ; MM32R3: movf.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp ogt float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
@@ -218,6 +248,11 @@ entry:
; SEL-64: cmp.le.s $f0, $f13, $f12
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: c.ult.s $f12, $f14
+ ; MM32R3: movf.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp oge float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
@@ -250,6 +285,11 @@ entry:
; SEL-64: cmp.eq.s $f0, $f12, $f13
; SEL-64: sel.s $f0, $f13, $f12
+
+ ; MM32R3: c.eq.s $f12, $f14
+ ; MM32R3: movt.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp oeq float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
@@ -275,7 +315,8 @@ entry:
; SEL-32: cmp.ueq.s $f0, $f12, $f14
; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
- ; SEL-32: not $[[T0]], $[[T0]]
+ ; 32R6: not $[[T0]], $[[T0]]
+ ; MM32R6: nor $[[T0]], $[[T0]], $zero
; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
; SEL-32: sel.s $f0, $f14, $f12
@@ -289,6 +330,10 @@ entry:
; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
; SEL-64: sel.s $f0, $f13, $f12
+ ; MM32R3: c.ueq.s $f12, $f14
+ ; MM32R3: movf.s $f14, $f12, $fcc0
+ ; MM32R3: mov.s $f0, $f14
+
%s = fcmp one float %x, %y
%r = select i1 %s, float %x, float %y
ret float %r
diff --git a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
index d179446b2c3..1ebe4bc2888 100644
--- a/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
+++ b/llvm/test/CodeGen/Mips/llvm-ir/select-int.ll
@@ -28,6 +28,10 @@
; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
+; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MM32R3
+; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
+; RUN: -check-prefix=ALL -check-prefix=MMR6 -check-prefix=MM32R6
define signext i1 @tst_select_i1_i1(i1 signext %s,
i1 signext %x, i1 signext %y) {
@@ -50,6 +54,16 @@ entry:
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
; SEL: or $2, $[[T2]], $[[T1]]
+
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
+ ; MM32R3: move $2, $[[T1]]
+
+ ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
+ ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
+ ; MMR6: or $2, $[[T2]], $[[T1]]
+
%r = select i1 %s, i1 %x, i1 %y
ret i1 %r
}
@@ -75,6 +89,16 @@ entry:
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
; SEL: or $2, $[[T2]], $[[T1]]
+
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
+ ; MM32R3: move $2, $[[T1]]
+
+ ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
+ ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
+ ; MMR6: or $2, $[[T2]], $[[T1]]
+
%r = select i1 %s, i8 %x, i8 %y
ret i8 %r
}
@@ -100,6 +124,16 @@ entry:
; SEL: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL: selnez $[[T2:[0-9]+]], $5, $[[T0]]
; SEL: or $2, $[[T2]], $[[T1]]
+
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: movn $[[T1:[0-9]+]], $5, $[[T0]]
+ ; MM32R3: move $2, $[[T1]]
+
+ ; MMR6: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MMR6: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
+ ; MMR6: selnez $[[T2:[0-9]+]], $5, $[[T0]]
+ ; MMR6: or $2, $[[T2]], $[[T1]]
+
%r = select i1 %s, i32 %x, i32 %y
ret i32 %r
}
@@ -157,6 +191,23 @@ entry:
; SEL-64: seleqz $[[T1:[0-9]+]], $6, $[[T0]]
; SEL-64: selnez $[[T0]], $5, $[[T0]]
; SEL-64: or $2, $[[T0]], $[[T1]]
+
+ ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R3: lw $2, 16($sp)
+ ; MM32R3: movn $2, $6, $[[T0]]
+ ; MM32R3: lw $3, 20($sp)
+ ; MM32R3: movn $3, $7, $[[T0]]
+
+ ; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1
+ ; MM32R6: lw $[[T1:[0-9]+]], 16($sp)
+ ; MM32R6: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]]
+ ; MM32R6: selnez $[[T3:[0-9]+]], $6, $[[T0]]
+ ; MM32R6: or $2, $[[T3]], $[[T2]]
+ ; MM32R6: lw $[[T4:[0-9]+]], 20($sp)
+ ; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]]
+ ; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]]
+ ; MM32R6: or $3, $[[T6]], $[[T5]]
+
%r = select i1 %s, i64 %x, i64 %y
ret i64 %r
}
@@ -164,47 +215,58 @@ entry:
define i8* @tst_select_word_cst(i8* %a, i8* %b) {
; ALL-LABEL: tst_select_word_cst:
- ; M2: addiu $1, $zero, -1
- ; M2: xor $1, $5, $1
- ; M2: sltu $1, $zero, $1
- ; M2: bnez $1, $[[BB0:BB[0-9_]+]]
+ ; M2: addiu $[[T0:[0-9]+]], $zero, -1
+ ; M2: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; M2: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
+ ; M2: bnez $[[T2]], $[[BB0:BB[0-9_]+]]
; M2: addiu $2, $zero, 0
; M2: move $2, $4
; M2: $[[BB0]]:
; M2: jr $ra
- ; M3: daddiu $1, $zero, -1
- ; M3: xor $1, $5, $1
- ; M3: sltu $1, $zero, $1
- ; M3: bnez $1, $[[BB0:BB[0-9_]+]]
+ ; M3: daddiu $[[T0:[0-9]+]], $zero, -1
+ ; M3: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; M3: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
+ ; M3: bnez $[[T2]], $[[BB0:BB[0-9_]+]]
; M3: daddiu $2, $zero, 0
; M3: move $2, $4
; M3: $[[BB0]]:
; M3: jr $ra
- ; CMOV-32: addiu $1, $zero, -1
- ; CMOV-32: xor $1, $5, $1
- ; CMOV-32: movn $4, $zero, $1
+ ; CMOV-32: addiu $[[T0:[0-9]+]], $zero, -1
+ ; CMOV-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; CMOV-32: movn $[[T2:[0-9]+]], $zero, $[[T1]]
; CMOV-32: jr $ra
- ; CMOV-32: move $2, $4
+ ; CMOV-32: move $2, $[[T2]]
- ; SEL-32: addiu $1, $zero, -1
- ; SEL-32: xor $1, $5, $1
- ; SEL-32: sltu $1, $zero, $1
+ ; SEL-32: addiu $[[T0:[0-9]+]], $zero, -1
+ ; SEL-32: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; SEL-32: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
; SEL-32: jr $ra
- ; SEL-32: seleqz $2, $4, $1
+ ; SEL-32: seleqz $2, $4, $[[T2]]
- ; CMOV-64: daddiu $1, $zero, -1
- ; CMOV-64: xor $1, $5, $1
- ; CMOV-64: movn $4, $zero, $1
- ; CMOV-64: move $2, $4
+ ; CMOV-64: daddiu $[[T0:[0-9]+]], $zero, -1
+ ; CMOV-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; CMOV-64: movn $[[T2:[0-9]+]], $zero, $[[T1]]
+ ; CMOV-64: move $2, $[[T2]]
- ; SEL-64: daddiu $1, $zero, -1
- ; SEL-64: xor $1, $5, $1
- ; SEL-64: sltu $1, $zero, $1
+ ; SEL-64: daddiu $[[T0:[0-9]+]], $zero, -1
+ ; SEL-64: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; SEL-64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
; FIXME: This shift is redundant.
- ; SEL-64: sll $1, $1, 0
- ; SEL-64: seleqz $2, $4, $1
+ ; SEL-64: sll $[[T2]], $[[T2]], 0
+ ; SEL-64: seleqz $2, $4, $[[T2]]
+
+ ; MM32R3: li16 $[[T0:[0-9]+]], -1
+ ; MM32R3: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; MM32R3: lui $[[T2:[0-9]+]], 0
+ ; MM32R3: movn $[[T3:[0-9]+]], $[[T2]], $[[T1]]
+ ; MM32R3: move $2, $[[T3]]
+
+ ; MM32R6: li16 $[[T0:[0-9]+]], -1
+ ; MM32R6: xor $[[T1:[0-9]+]], $5, $[[T0]]
+ ; MM32R6: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
+ ; MM32R6: seleqz $2, $4, $[[T2]]
%cmp = icmp eq i8* %b, inttoptr (i64 -1 to i8*)
%r = select i1 %cmp, i8* %a, i8* null
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