4 files changed, 180 insertions, 0 deletions
diff --git a/llvm/test/MC/AArch64/SVE/sdot-diagnostics.s b/llvm/test/MC/AArch64/SVE/sdot-diagnostics.s
new file mode 100644
index 00000000000..cc22f21aa24
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/sdot-diagnostics.s
@@ -0,0 +1,58 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+sdot  z0.s, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sdot  z0.s, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot  z0.d, z1.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sdot  z0.d, z1.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: sdot  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid restricted register for indexed vector.
+
+sdot  z0.s, z1.b, z8.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sdot  z0.s, z1.b, z8.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot  z0.d, z1.h, z16.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sdot  z0.d, z1.h, z16.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element index
+
+sdot  z0.s, z1.b, z7.b[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: sdot  z0.s, z1.b, z7.b[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot  z0.s, z1.b, z7.b[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: sdot  z0.s, z1.b, z7.b[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot  z0.d, z1.h, z15.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: sdot  z0.d, z1.h, z15.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sdot  z0.d, z1.h, z15.h[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: sdot  z0.d, z1.h, z15.h[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/sdot.s b/llvm/test/MC/AArch64/SVE/sdot.s
new file mode 100644
index 00000000000..dbc6b3eabc0
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/sdot.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+sdot  z0.s, z1.b, z31.b
+// CHECK-INST: sdot	z0.s, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x00,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 9f 44 <unknown>
+
+sdot  z0.d, z1.h, z31.h
+// CHECK-INST: sdot	z0.d, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x00,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 df 44 <unknown>
+
+sdot  z0.s, z1.b, z7.b[3]
+// CHECK-INST: sdot	z0.s, z1.b, z7.b[3]
+// CHECK-ENCODING: [0x20,0x00,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 bf 44 <unknown>
+
+sdot  z0.d, z1.h, z15.h[1]
+// CHECK-INST: sdot	z0.d, z1.h, z15.h[1]
+// CHECK-ENCODING: [0x20,0x00,0xff,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 00 ff 44 <unknown>
diff --git a/llvm/test/MC/AArch64/SVE/udot-diagnostics.s b/llvm/test/MC/AArch64/SVE/udot-diagnostics.s
new file mode 100644
index 00000000000..08abd77592e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/udot-diagnostics.s
@@ -0,0 +1,58 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve  2>&1 < %s| FileCheck %s
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element size
+
+udot  z0.s, z1.h, z31.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: udot  z0.s, z1.h, z31.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot  z0.d, z1.b, z31.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: udot  z0.d, z1.b, z31.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot  z0.d, z1.s, z31.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: udot  z0.d, z1.s, z31.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid restricted register for indexed vector.
+
+udot  z0.s, z1.b, z8.b[3]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: udot  z0.s, z1.b, z8.b[3]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot  z0.d, z1.h, z16.h[1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: udot  z0.d, z1.h, z16.h[1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// ------------------------------------------------------------------------- //
+// Invalid element index
+
+udot  z0.s, z1.b, z7.b[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: udot  z0.s, z1.b, z7.b[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot  z0.s, z1.b, z7.b[4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
+// CHECK-NEXT: udot  z0.s, z1.b, z7.b[4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot  z0.d, z1.h, z15.h[-1]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: udot  z0.d, z1.h, z15.h[-1]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+udot  z0.d, z1.h, z15.h[2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
+// CHECK-NEXT: udot  z0.d, z1.h, z15.h[2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/udot.s b/llvm/test/MC/AArch64/SVE/udot.s
new file mode 100644
index 00000000000..0c3a392093c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE/udot.s
@@ -0,0 +1,32 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d -mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+udot  z0.s, z1.b, z31.b
+// CHECK-INST: udot	z0.s, z1.b, z31.b
+// CHECK-ENCODING: [0x20,0x04,0x9f,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 9f 44 <unknown>
+
+udot  z0.d, z1.h, z31.h
+// CHECK-INST: udot	z0.d, z1.h, z31.h
+// CHECK-ENCODING: [0x20,0x04,0xdf,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 df 44 <unknown>
+
+udot  z0.s, z1.b, z7.b[3]
+// CHECK-INST: udot	z0.s, z1.b, z7.b[3]
+// CHECK-ENCODING: [0x20,0x04,0xbf,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 bf 44 <unknown>
+
+udot  z0.d, z1.h, z15.h[1]
+// CHECK-INST: udot	z0.d, z1.h, z15.h[1]
+// CHECK-ENCODING: [0x20,0x04,0xff,0x44]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 20 04 ff 44 <unknown>