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-rw-r--r--llvm/test/CodeGen/Mips/fcmp.ll168
-rw-r--r--llvm/test/CodeGen/Mips/select.ll36
2 files changed, 124 insertions, 80 deletions
diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll
index dce8a7d6da5..b7759831c5a 100644
--- a/llvm/test/CodeGen/Mips/fcmp.ll
+++ b/llvm/test/CodeGen/Mips/fcmp.ll
@@ -29,10 +29,12 @@ define i32 @oeq_f32(float %a, float %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp oeq float %a, %b
%2 = zext i1 %1 to i32
@@ -53,10 +55,12 @@ define i32 @ogt_f32(float %a, float %b) nounwind {
; 64-C-DAG: movf $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ogt float %a, %b
%2 = zext i1 %1 to i32
@@ -77,10 +81,12 @@ define i32 @oge_f32(float %a, float %b) nounwind {
; 64-C-DAG: movf $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp oge float %a, %b
%2 = zext i1 %1 to i32
@@ -101,10 +107,12 @@ define i32 @olt_f32(float %a, float %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp olt float %a, %b
%2 = zext i1 %1 to i32
@@ -125,10 +133,12 @@ define i32 @ole_f32(float %a, float %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ole float %a, %b
%2 = zext i1 %1 to i32
@@ -150,11 +160,13 @@ define i32 @one_f32(float %a, float %b) nounwind {
; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG: not $2, $[[T1]]
+; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG: not $2, $[[T1]]
+; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG: andi $2, $[[T2]], 1
%1 = fcmp one float %a, %b
%2 = zext i1 %1 to i32
@@ -176,11 +188,13 @@ define i32 @ord_f32(float %a, float %b) nounwind {
; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG: not $2, $[[T1]]
+; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG: not $2, $[[T1]]
+; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG: andi $2, $[[T2]], 1
%1 = fcmp ord float %a, %b
%2 = zext i1 %1 to i32
@@ -201,10 +215,12 @@ define i32 @ueq_f32(float %a, float %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ueq float %a, %b
%2 = zext i1 %1 to i32
@@ -225,10 +241,12 @@ define i32 @ugt_f32(float %a, float %b) nounwind {
; 64-C-DAG: movf $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ugt float %a, %b
%2 = zext i1 %1 to i32
@@ -249,10 +267,12 @@ define i32 @uge_f32(float %a, float %b) nounwind {
; 64-C-DAG: movf $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp uge float %a, %b
%2 = zext i1 %1 to i32
@@ -273,10 +293,12 @@ define i32 @ult_f32(float %a, float %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ult float %a, %b
%2 = zext i1 %1 to i32
@@ -297,10 +319,12 @@ define i32 @ule_f32(float %a, float %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ule float %a, %b
%2 = zext i1 %1 to i32
@@ -322,11 +346,13 @@ define i32 @une_f32(float %a, float %b) nounwind {
; 32-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG: not $2, $[[T1]]
+; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG: not $2, $[[T1]]
+; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG: andi $2, $[[T2]], 1
%1 = fcmp une float %a, %b
%2 = zext i1 %1 to i32
@@ -347,10 +373,12 @@ define i32 @uno_f32(float %a, float %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp uno float %a, %b
%2 = zext i1 %1 to i32
@@ -389,10 +417,12 @@ define i32 @oeq_f64(double %a, double %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp oeq double %a, %b
%2 = zext i1 %1 to i32
@@ -413,10 +443,12 @@ define i32 @ogt_f64(double %a, double %b) nounwind {
; 64-C-DAG: movf $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ogt double %a, %b
%2 = zext i1 %1 to i32
@@ -437,10 +469,12 @@ define i32 @oge_f64(double %a, double %b) nounwind {
; 64-C-DAG: movf $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp oge double %a, %b
%2 = zext i1 %1 to i32
@@ -461,10 +495,12 @@ define i32 @olt_f64(double %a, double %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp olt double %a, %b
%2 = zext i1 %1 to i32
@@ -485,10 +521,12 @@ define i32 @ole_f64(double %a, double %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ole double %a, %b
%2 = zext i1 %1 to i32
@@ -510,11 +548,13 @@ define i32 @one_f64(double %a, double %b) nounwind {
; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG: not $2, $[[T1]]
+; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG: not $2, $[[T1]]
+; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG: andi $2, $[[T2]], 1
%1 = fcmp one double %a, %b
%2 = zext i1 %1 to i32
@@ -536,11 +576,13 @@ define i32 @ord_f64(double %a, double %b) nounwind {
; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG: not $2, $[[T1]]
+; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG: not $2, $[[T1]]
+; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG: andi $2, $[[T2]], 1
%1 = fcmp ord double %a, %b
%2 = zext i1 %1 to i32
@@ -561,10 +603,12 @@ define i32 @ueq_f64(double %a, double %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ueq double %a, %b
%2 = zext i1 %1 to i32
@@ -585,10 +629,12 @@ define i32 @ugt_f64(double %a, double %b) nounwind {
; 64-C-DAG: movf $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ugt double %a, %b
%2 = zext i1 %1 to i32
@@ -609,10 +655,12 @@ define i32 @uge_f64(double %a, double %b) nounwind {
; 64-C-DAG: movf $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp uge double %a, %b
%2 = zext i1 %1 to i32
@@ -633,10 +681,12 @@ define i32 @ult_f64(double %a, double %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ult double %a, %b
%2 = zext i1 %1 to i32
@@ -657,10 +707,12 @@ define i32 @ule_f64(double %a, double %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp ule double %a, %b
%2 = zext i1 %1 to i32
@@ -682,11 +734,13 @@ define i32 @une_f64(double %a, double %b) nounwind {
; 32-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 32-CMP-DAG: not $2, $[[T1]]
+; 32-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 32-CMP-DAG: andi $2, $[[T2]], 1
; 64-CMP-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
-; 64-CMP-DAG: not $2, $[[T1]]
+; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]]
+; 64-CMP-DAG: andi $2, $[[T2]], 1
%1 = fcmp une double %a, %b
%2 = zext i1 %1 to i32
@@ -707,10 +761,12 @@ define i32 @uno_f64(double %a, double %b) nounwind {
; 64-C-DAG: movt $[[T0]], $1, $fcc0
; 32-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
-; 32-CMP-DAG: mfc1 $2, $[[T0]]
+; 32-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 32-CMP-DAG: andi $2, $[[T1]], 1
; 64-CMP-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
-; 64-CMP-DAG: mfc1 $2, $[[T0]]
+; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]]
+; 64-CMP-DAG: andi $2, $[[T1]], 1
%1 = fcmp uno double %a, %b
%2 = zext i1 %1 to i32
diff --git a/llvm/test/CodeGen/Mips/select.ll b/llvm/test/CodeGen/Mips/select.ll
index 91471a2ce6b..eb2198b36df 100644
--- a/llvm/test/CodeGen/Mips/select.ll
+++ b/llvm/test/CodeGen/Mips/select.ll
@@ -516,9 +516,8 @@ entry:
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
; 32R6: cmp.eq.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 32R6: or $2, $[[NE]], $[[EQ]]
@@ -532,9 +531,8 @@ entry:
; 64R6: cmp.eq.s $[[CC:f[0-9]+]], $f14, $f15
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 64R6: or $2, $[[NE]], $[[EQ]]
@@ -563,9 +561,8 @@ entry:
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F2]], $[[F3]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 32R6: or $2, $[[NE]], $[[EQ]]
@@ -579,9 +576,8 @@ entry:
; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f14, $f15
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 64R6: or $2, $[[NE]], $[[EQ]]
%cmp = fcmp olt float %f2, %f3
@@ -609,9 +605,8 @@ entry:
; 32R6-DAG: mtc1 $7, $[[F3:f[0-9]+]]
; 32R6: cmp.lt.s $[[CC:f[0-9]+]], $[[F3]], $[[F2]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 32R6: or $2, $[[NE]], $[[EQ]]
@@ -625,9 +620,8 @@ entry:
; 64R6: cmp.lt.s $[[CC:f[0-9]+]], $f15, $f14
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 64R6: or $2, $[[NE]], $[[EQ]]
@@ -668,9 +662,8 @@ entry:
; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
; 32R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 32R6: or $2, $[[NE]], $[[EQ]]
@@ -702,9 +695,8 @@ entry:
; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
; 64R6: cmp.eq.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 64R6: or $2, $[[NE]], $[[EQ]]
@@ -747,9 +739,8 @@ entry:
; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 32R6: or $2, $[[NE]], $[[EQ]]
@@ -781,9 +772,8 @@ entry:
; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP]], $[[TMP1]]
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 64R6: or $2, $[[NE]], $[[EQ]]
@@ -826,9 +816,8 @@ entry:
; 32R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
; 32R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 32R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 32R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 32R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 32R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 32R6: or $2, $[[NE]], $[[EQ]]
@@ -860,9 +849,8 @@ entry:
; 64R6-DAG: ldc1 $[[TMP1:f[0-9]+]], 0($[[D3]])
; 64R6: cmp.lt.d $[[CC:f[0-9]+]], $[[TMP1]], $[[TMP]]
; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
+; 64R6: andi $[[CCGPR]], $[[CCGPR]], 1
; 64R6: seleqz $[[EQ:[0-9]+]], $5, $[[CCGPR]]
-; FIXME: This move is redundant
-; 64R6: mfc1 $[[CCGPR:[0-9]+]], $[[CC]]
; 64R6: selnez $[[NE:[0-9]+]], $4, $[[CCGPR]]
; 64R6: or $2, $[[NE]], $[[EQ]]
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