4 files changed, 169 insertions, 85 deletions
diff --git a/llvm/test/CodeGen/RISCV/alu32.ll b/llvm/test/CodeGen/RISCV/alu32.ll
index f34efe932b8..6ecd08878dd 100644
--- a/llvm/test/CodeGen/RISCV/alu32.ll
+++ b/llvm/test/CodeGen/RISCV/alu32.ll
@@ -2,10 +2,6 @@
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 
-; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s \
-; RUN:   |llvm-objdump -d -triple=riscv32 -mattr=+c -riscv-no-aliases - \
-; RUN:   | FileCheck -check-prefix=RV32IC %s
-
 ; These tests are each targeted at a particular RISC-V ALU instruction. Other
 ; files in this folder exercise LLVM IR instructions that don't directly match a
 ; RISC-V instruction
@@ -17,10 +13,6 @@ define i32 @addi(i32 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, a0, 1
 ; RV32I-NEXT:    ret
-
-; RV32IC-LABEL: addi:
-; RV32IC-NEXT:  c.addi a0, 1
-; RV32IC-NEXT:  c.jr ra
   %1 = add i32 %a, 1
   ret i32 %1
 }
@@ -68,11 +60,6 @@ define i32 @andi(i32 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    andi a0, a0, 6
 ; RV32I-NEXT:    ret
-
-
-; RV32IC-LABEL: andi:
-; RV32IC: c.andi a0, 6
-; RV32IC: c.jr ra
   %1 = and i32 %a, 6
   ret i32 %1
 }
@@ -82,10 +69,6 @@ define i32 @slli(i32 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 7
 ; RV32I-NEXT:    ret
-
-; RV32IC-LABEL: slli:
-; RV32IC-NEXT:  slli a0, 7
-; RV32IC-NEXT:  c.jr ra
   %1 = shl i32 %a, 7
   ret i32 %1
 }
@@ -95,10 +78,6 @@ define i32 @srli(i32 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a0, a0, 8
 ; RV32I-NEXT:    ret
-
-; RV32IC-LABEL: srli:
-; RV32IC-NEXT:    c.srli a0, 8
-; RV32IC-NEXT:    c.jr ra
   %1 = lshr i32 %a, 8
   ret i32 %1
 }
@@ -108,10 +87,6 @@ define i32 @srai(i32 %a) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a0, a0, 9
 ; RV32I-NEXT:    ret
-
-; RV32IC-LABEL: srai:
-; RV32IC-NEXT:  c.srai a0, 9
-; RV32IC-NEXT:  c.jr ra
   %1 = ashr i32 %a, 9
   ret i32 %1
 }
@@ -123,11 +98,6 @@ define i32 @add(i32 %a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
-
-; RV32IC-LABEL: add:
-; RV32IC-NEXT:    c.add a0, a1
-; RV32IC-NEXT:    c.jr ra
-
   %1 = add i32 %a, %b
   ret i32 %1
 }
@@ -137,10 +107,6 @@ define i32 @sub(i32 %a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sub a0, a0, a1
 ; RV32I-NEXT:    ret
-
-; RV32IC-LABEL: sub:
-; RV32IC-NEXT:    c.sub a0, a1
-; RV32IC-NEXT:    c.jr ra
   %1 = sub i32 %a, %b
   ret i32 %1
 }
@@ -179,10 +145,6 @@ define i32 @xor(i32 %a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    ret
-
-; RV32IC-LABEL: xor:
-; RV32IC-NEXT:    c.xor a0, a1
-; RV32IC-NEXT:    c.jr ra
   %1 = xor i32 %a, %b
   ret i32 %1
 }
@@ -219,10 +181,6 @@ define i32 @and(i32 %a, i32 %b) nounwind {
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    and a0, a0, a1
 ; RV32I-NEXT:    ret
-
-; RV32IC-LABEL: and:
-; RV32IC-NEXT:    c.and a0, a1
-; RV32IC-NEXT:    c.jr ra
   %1 = and i32 %a, %b
   ret i32 %1
 }
diff --git a/llvm/test/CodeGen/RISCV/branch.ll b/llvm/test/CodeGen/RISCV/branch.ll
index f6d9299b07d..71daf0e57b9 100644
--- a/llvm/test/CodeGen/RISCV/branch.ll
+++ b/llvm/test/CodeGen/RISCV/branch.ll
@@ -2,11 +2,6 @@
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 
-
-; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj < %s \
-; RUN:   |llvm-objdump -d -triple=riscv32 -mattr=+c -riscv-no-aliases - \
-; RUN:   | FileCheck -check-prefix=RV32IC %s
-
 define void @foo(i32 %a, i32 *%b, i1 %c) {
 ; RV32I-LABEL: foo:
 ; RV32I:       # %bb.0:
@@ -47,34 +42,6 @@ define void @foo(i32 %a, i32 *%b, i1 %c) {
 ; RV32I-NEXT:    lw a0, 0(a1)
 ; RV32I-NEXT:  .LBB0_12: # %end
 ; RV32I-NEXT:    ret
-
-; RV32IC-LABEL: foo:
-; RV32IC:       c.lw a3, 0(a1)
-; RV32IC-NEXT:  beq  a3, a0, 68
-; RV32IC-NEXT:  c.lw a3, 0(a1)
-; RV32IC-NEXT:  bne  a3, a0, 62
-; RV32IC-NEXT:  c.lw a3, 0(a1)
-; RV32IC-NEXT:  blt  a3, a0, 56
-; RV32IC-NEXT:  c.lw a3, 0(a1)
-; RV32IC-NEXT:  bge  a3, a0, 50
-; RV32IC-NEXT:  c.lw a3, 0(a1)
-; RV32IC-NEXT:  bltu a3, a0, 44
-; RV32IC-NEXT:  c.lw a3, 0(a1)
-; RV32IC-NEXT:  bgeu a3, a0, 38
-; RV32IC-NEXT:  c.lw a3, 0(a1)
-; RV32IC-NEXT:  blt  a0, a3, 32
-; RV32IC-NEXT:  c.lw a3, 0(a1)
-; RV32IC-NEXT:  bge  a0, a3, 26
-; RV32IC-NEXT:  c.lw a3, 0(a1)
-; RV32IC-NEXT:  bltu a0, a3, 20
-; RV32IC-NEXT:  c.lw a3, 0(a1)
-; RV32IC-NEXT:  bgeu a0, a3, 14
-; RV32IC-NEXT:  c.lw a0, 0(a1)
-; RV32IC-NEXT:  andi a0, a2, 1
-; RV32IC-NEXT:  c.bnez a0, 4
-; RV32IC-NEXT:  c.lw a0, 0(a1)
-; RV32IC-NEXT:  c.jr ra
-
   %val1 = load volatile i32, i32* %b
   %tst1 = icmp eq i32 %val1, %a
   br i1 %tst1, label %end, label %test2
diff --git a/llvm/test/CodeGen/RISCV/compress-Pseudo.ll b/llvm/test/CodeGen/RISCV/compress-Pseudo.ll
deleted file mode 100644
index bb25fe9d51d..00000000000
--- a/llvm/test/CodeGen/RISCV/compress-Pseudo.ll
+++ /dev/null
@@ -1,10 +0,0 @@
-; RUN: llc -mtriple=riscv32 -mattr=+c  -riscv-no-aliases -o %t1 < %s
-; RUN: FileCheck %s < %t1
-
-define void @foo() {
-; CHECK-LABEL: foo:
-; CHECK:   c.jr
-
-end:
-  ret void
-}
diff --git a/llvm/test/CodeGen/RISCV/compress.ll b/llvm/test/CodeGen/RISCV/compress.ll
new file mode 100644
index 00000000000..0f912e8ba20
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/compress.ll
@@ -0,0 +1,169 @@
+; RUN: llc -mtriple=riscv32 -mattr=+c -filetype=obj \
+; RUN:   -disable-block-placement < %s \
+; RUN:   | llvm-objdump -d -triple=riscv32 -mattr=+c -riscv-no-aliases - \
+; RUN:   | FileCheck -check-prefix=RV32IC %s
+
+; This acts as a sanity check for the codegen instruction compression path,
+; verifying that the assembled file contains compressed instructions when
+; expected. Handling of the compressed ISA is implemented so the same
+; transformation patterns should be used whether compressing an input .s file or
+; compressing codegen output. This file contains sanity checks to ensure that is
+; working as expected. Particular care should be taken to test pseudo
+; instructions.
+
+; Note: TODOs in this file are only appropriate if they highlight a case where
+; a generated instruction that can be compressed by an existing pattern isn't.
+; It may be useful to have tests that indicate where better compression would be
+; possible if alternative codegen choices were made, but they belong in a
+; different test file.
+
+define i32 @simple_arith(i32 %a, i32 %b) nounwind {
+; RV32IC-LABEL: simple_arith:
+; RV32IC:         c.srai a1, 9
+; RV32IC-NEXT:    addi a2, a0, 1
+; RV32IC-NEXT:    c.andi a2, 11
+; RV32IC-NEXT:    c.slli a2, 7
+; RV32IC-NEXT:    c.add a1, a2
+; RV32IC-NEXT:    sub a0, a1, a0
+; RV32IC-NEXT:    c.jr ra
+  %1 = add i32 %a, 1
+  %2 = and i32 %1, 11
+  %3 = shl i32 %2, 7
+  %4 = ashr i32 %b, 9
+  %5 = add i32 %3, %4
+  %6 = sub i32 %5, %a
+  ret i32 %6
+}
+
+define i32 @select(i32 %a, i32 *%b) nounwind {
+; RV32IC-LABEL: select:
+; RV32IC:         c.lw a2, 0(a1)
+; RV32IC-NEXT:    c.beqz a2, 4
+; RV32IC-NEXT:    c.mv a0, a2
+; RV32IC-NEXT:    c.lw a2, 0(a1)
+; RV32IC-NEXT:    c.bnez a2, 4
+; RV32IC-NEXT:    c.mv a0, a2
+; RV32IC-NEXT:    c.lw a2, 0(a1)
+; RV32IC-NEXT:    bltu a2, a0, 6
+; RV32IC-NEXT:    c.mv a0, a2
+; RV32IC-NEXT:    c.lw a2, 0(a1)
+; RV32IC-NEXT:    bgeu a0, a2, 6
+; RV32IC-NEXT:    c.mv a0, a2
+; RV32IC-NEXT:    c.lw a2, 0(a1)
+; RV32IC-NEXT:    bltu a0, a2, 6
+; RV32IC-NEXT:    c.mv a0, a2
+; RV32IC-NEXT:    c.lw a2, 0(a1)
+; RV32IC-NEXT:    bgeu a2, a0, 6
+; RV32IC-NEXT:    c.mv a0, a2
+; RV32IC-NEXT:    c.lw a2, 0(a1)
+; RV32IC-NEXT:    blt a2, a0, 6
+; RV32IC-NEXT:    c.mv a0, a2
+; RV32IC-NEXT:    c.lw a2, 0(a1)
+; RV32IC-NEXT:    bge a0, a2, 6
+; RV32IC-NEXT:    c.mv a0, a2
+; RV32IC-NEXT:    c.lw a2, 0(a1)
+; RV32IC-NEXT:    blt a0, a2, 6
+; RV32IC-NEXT:    c.mv a0, a2
+; RV32IC-NEXT:    c.lw a1, 0(a1)
+; RV32IC-NEXT:    bge a1, a0, 6
+; RV32IC-NEXT:    c.mv a0, a1
+; RV32IC-NEXT:    c.jr ra
+  %val1 = load volatile i32, i32* %b
+  %tst1 = icmp eq i32 0, %val1
+  %val2 = select i1 %tst1, i32 %a, i32 %val1
+
+  %val3 = load volatile i32, i32* %b
+  %tst2 = icmp ne i32 0, %val3
+  %val4 = select i1 %tst2, i32 %val2, i32 %val3
+
+  %val5 = load volatile i32, i32* %b
+  %tst3 = icmp ugt i32 %val4, %val5
+  %val6 = select i1 %tst3, i32 %val4, i32 %val5
+
+  %val7 = load volatile i32, i32* %b
+  %tst4 = icmp uge i32 %val6, %val7
+  %val8 = select i1 %tst4, i32 %val6, i32 %val7
+
+  %val9 = load volatile i32, i32* %b
+  %tst5 = icmp ult i32 %val8, %val9
+  %val10 = select i1 %tst5, i32 %val8, i32 %val9
+
+  %val11 = load volatile i32, i32* %b
+  %tst6 = icmp ule i32 %val10, %val11
+  %val12 = select i1 %tst6, i32 %val10, i32 %val11
+
+  %val13 = load volatile i32, i32* %b
+  %tst7 = icmp sgt i32 %val12, %val13
+  %val14 = select i1 %tst7, i32 %val12, i32 %val13
+
+  %val15 = load volatile i32, i32* %b
+  %tst8 = icmp sge i32 %val14, %val15
+  %val16 = select i1 %tst8, i32 %val14, i32 %val15
+
+  %val17 = load volatile i32, i32* %b
+  %tst9 = icmp slt i32 %val16, %val17
+  %val18 = select i1 %tst9, i32 %val16, i32 %val17
+
+  %val19 = load volatile i32, i32* %b
+  %tst10 = icmp sle i32 %val18, %val19
+  %val20 = select i1 %tst10, i32 %val18, i32 %val19
+
+  ret i32 %val20
+}
+
+define i32 @pos_tiny() nounwind {
+; RV32IC-LABEL: pos_tiny:
+; RV32IC:         c.li a0, 18
+; RV32IC-NEXT:    c.jr ra
+  ret i32 18
+}
+
+define i32 @pos_i32() nounwind {
+; RV32IC-LABEL: pos_i32:
+; RV32IC:         lui a0, 423811
+; RV32IC-NEXT:    addi a0, a0, -1297
+; RV32IC-NEXT:    c.jr ra
+  ret i32 1735928559
+}
+
+define i32 @pos_i32_half_compressible() nounwind {
+; RV32IC-LABEL: pos_i32_half_compressible:
+; RV32IC:         lui a0, 423810
+; RV32IC-NEXT:    c.addi  a0, 28
+; RV32IC-NEXT:    c.jr    ra
+  ret i32 1735925788
+}
+
+
+define i32 @neg_tiny() nounwind {
+; RV32IC-LABEL: neg_tiny:
+; RV32IC:       c.li a0, -19
+; RV32IC-NEXT:  c.jr ra
+  ret i32 -19
+}
+
+define i32 @neg_i32() nounwind {
+; RV32IC-LABEL: neg_i32:
+; RV32IC:       lui a0, 912092
+; RV32IC-NEXT:  addi a0, a0, -273
+; RV32IC-NEXT:  c.jr ra
+  ret i32 -559038737
+}
+
+; TODO: c.mv is unnecessary.
+define i32 @pos_i32_hi20_only() nounwind {
+; RV32IC-LABEL: pos_i32_hi20_only:
+; RV32IC:       c.lui a0, 16
+; RV32IC:       c.mv a0, a0
+; RV32IC-NEXT:  c.jr ra
+  ret i32 65536
+}
+
+; TODO: c.mv is unnecessary.
+define i32 @neg_i32_hi20_only() nounwind {
+; RV32IC-LABEL: neg_i32_hi20_only:
+; RV32IC:       c.lui a0, 1048560
+; RV32IC:       c.mv a0, a0
+; RV32IC-NEXT:  c.jr ra
+  ret i32 -65536
+}