diff options
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir | 111 |
1 files changed, 111 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir b/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir new file mode 100644 index 00000000000..80b98150876 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/misched-fusion-arith-logic.mir @@ -0,0 +1,111 @@ +# RUN: llc -o - %s -mtriple aarch64-unknown -mattr=fuse-arith-logic -run-pass=machine-scheduler -misched-print-dags |& FileCheck %s +# REQUIRES: asserts + +--- +name: arith +body: | + bb.0.entry: + %0:gpr32 = SUBWrr undef $w0, undef $w1 + %1:gpr32 = ADDWrr undef $w1, undef $w2 + %2:gpr32 = SUBWrs %0, undef $w2, 0 + %3:gpr32 = ADDWrs %1, undef $w3, 0 + + ; CHECK: SU(0): %0:gpr32 = SUBWrr undef $w0, undef $w1 + ; CHECK: Successors: + ; CHECK: SU(2): Ord Latency=0 Cluster + ; CHECK: SU(1): %1:gpr32 = ADDWrr undef $w1, undef $w2 + ; CHECK: Successors: + ; CHECK: SU(3): Ord Latency=0 Cluster + ; CHECK: SU(2): dead %2:gpr32 = SUBWrs %0:gpr32, undef $w2, 0 + ; CHECK: Predecessors: + ; CHECK: SU(0): Ord Latency=0 Cluster + ; CHECK: SU(3): dead %3:gpr32 = ADDWrs %1:gpr32, undef $w3, 0 + ; CHECK: Predecessors: + ; CHECK: SU(1): Ord Latency=0 Cluster +... +--- +name: compare +body: | + bb.0.entry: + %0:gpr64 = ADDXrr undef $x0, undef $x1 + %1:gpr64 = SUBXrs undef $x1, undef $x2, 0 + %2:gpr64 = ADDSXrr %0, undef $x3, implicit-def $nzcv + %3:gpr64 = SUBSXrs %1, undef $x4, 0, implicit-def $nzcv + + ; CHECK: SU(0): %0:gpr64 = ADDXrr undef $x0, undef $x1 + ; CHECK: Successors: + ; CHECK: SU(2): Ord Latency=0 Cluster + ; CHECK: SU(1): %1:gpr64 = SUBXrs undef $x1, undef $x2, 0 + ; CHECK: Successors: + ; CHECK: SU(3): Ord Latency=0 Cluster + ; CHECK: SU(2): dead %2:gpr64 = ADDSXrr %0:gpr64, undef $x3, implicit-def $nzcv + ; CHECK: Predecessors: + ; CHECK: SU(0): Ord Latency=0 Cluster + ; CHECK: SU(3): dead %3:gpr64 = SUBSXrs %1:gpr64, undef $x4, 0, implicit-def $nzcv + ; CHECK: Predecessors: + ; CHECK: SU(1): Ord Latency=0 Cluster +... +--- +name: logic +body: | + bb.0.entry: + %0:gpr32 = ADDWrr undef $w0, undef $w1 + %1:gpr64 = SUBXrs undef $x1, undef $x2, 0 + %3:gpr32 = ANDWrs %0, undef $w3, 0 + %4:gpr64 = ORRXrr %1, undef $x4 + + ; CHECK: SU(0): %0:gpr32 = ADDWrr undef $w0, undef $w1 + ; CHECK: Successors: + ; CHECK: SU(2): Ord Latency=0 Cluster + ; CHECK: SU(1): %1:gpr64 = SUBXrs undef $x1, undef $x2, 0 + ; CHECK: Successors: + ; CHECK: SU(3): Ord Latency=0 Cluster + ; CHECK: SU(2): dead %2:gpr32 = ANDWrs %0:gpr32, undef $w3, 0 + ; CHECK: Predecessors: + ; CHECK: SU(0): Ord Latency=0 Cluster + ; CHECK: SU(3): dead %3:gpr64 = ORRXrr %1:gpr64, undef $x4 + ; CHECK: Predecessors: + ; CHECK: SU(1): Ord Latency=0 Cluster +... +--- +name: nope +body: | + bb.0.entry: + ; Shifted register. + %0:gpr32 = SUBWrr undef $w0, undef $w1 + %1:gpr32 = SUBWrs %0, undef $w2, 1 + ; CHECKSU(0)%0:gpr32 = SUBWrr undef $w0, undef $w1 + ; CHECKSuccessors: + ; CHECK-NOTSU(1)Ord Latency=0 Cluster + ; CHECKSU(1)dead %1:gpr32 = SUBWrs %0:gpr32, undef $w2, 1 + + ; Multiple successors. + %2:gpr64 = ADDXrr undef $x0, undef $x1 + %3:gpr32 = EXTRACT_SUBREG %2, %subreg.sub_32 + %4:gpr32 = ANDWrs %3, undef $w2, 0 + %5:gpr64 = ADDSXrr %2, undef $x3, implicit-def $nzcv + ; CHECKSU(2)%2:gpr64 = ADDXrr undef $x0, undef $x1 + ; CHECKSuccessors: + ; CHECK-NOTSU(3)Ord Latency=0 Cluster + ; CHECKSU(5)Ord Latency=0 Cluster + ; CHECKSU(3)%3:gpr32 = EXTRACT_SUBREG %2:gpr64, %subreg.sub_32 + ; CHECKSU(5)dead %5:gpr64 = ADDSXrr %2:gpr64, undef $x3, implicit-def $nzcv + + ; Different register sizes. + %6:gpr32 = SUBWrr undef $w0, undef $w1 + %7:gpr64 = ADDXrr undef $x1, undef $x2 + %8:gpr64 = SUBXrr %7, undef $x3 + %9:gpr32 = ADDWrr %6, undef $w4 + ; CHECKSU(6)%6:gpr32 = SUBWrr undef $w0, undef $w1 + ; CHECKSuccessors: + ; CHECK-NOTSU(8)Ord Latency=0 Cluster + ; CHECKSU(7)%7:gpr64 = ADDXrr undef $x1, undef $x2 + ; CHECKSuccessors: + ; CHECK-NOTSU(9)Ord Latency=0 Cluster + ; CHECKSU(8)dead %8:gpr64 = SUBXrr %7:gpr64, undef $x3 + ; CHECKPredecessors: + ; CHECKSU(7)Ord Latency=0 Cluster + ; CHECKSU(9)dead %9:gpr32 = ADDWrr %6:gpr32, undef $w4 + ; CHECKPredecessors: + ; CHECKSU(6)Ord Latency=0 Cluster +... |
