diff options
Diffstat (limited to 'llvm/test')
39 files changed, 217 insertions, 581 deletions
diff --git a/llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll b/llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll index 948b67eb66c..f4cb30f2d01 100644 --- a/llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll +++ b/llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll @@ -8,7 +8,7 @@ define i16 @am1(i16 %x, i16* %a) nounwind { ret i16 %2 } ; CHECK-LABEL: am1: -; CHECK: bis 0(r13), r12 +; CHECK: bis.w 0(r13), r12 @foo = external global i16 @@ -18,7 +18,7 @@ define i16 @am2(i16 %x) nounwind { ret i16 %2 } ; CHECK-LABEL: am2: -; CHECK: bis &foo, r12 +; CHECK: bis.w &foo, r12 @bar = internal constant [2 x i8] [ i8 32, i8 64 ] @@ -37,7 +37,7 @@ define i16 @am4(i16 %x) nounwind { ret i16 %2 } ; CHECK-LABEL: am4: -; CHECK: bis &32, r12 +; CHECK: bis.w &32, r12 define i16 @am5(i16 %x, i16* %a) nounwind { %1 = getelementptr i16, i16* %a, i16 2 @@ -46,7 +46,7 @@ define i16 @am5(i16 %x, i16* %a) nounwind { ret i16 %3 } ; CHECK-LABEL: am5: -; CHECK: bis 4(r13), r12 +; CHECK: bis.w 4(r13), r12 %S = type { i16, i16 } @baz = common global %S zeroinitializer, align 1 @@ -57,7 +57,7 @@ define i16 @am6(i16 %x) nounwind { ret i16 %2 } ; CHECK-LABEL: am6: -; CHECK: bis &baz+2, r12 +; CHECK: bis.w &baz+2, r12 %T = type { i16, [2 x i8] } @duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] } diff --git a/llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll b/llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll index 6d3a497386d..1e150f38206 100644 --- a/llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll +++ b/llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll @@ -9,7 +9,7 @@ define void @am1(i16* %a, i16 %x) nounwind { ret void } ; CHECK-LABEL: am1: -; CHECK: bis r13, 0(r12) +; CHECK: bis.w r13, 0(r12) @foo = external global i16 @@ -20,7 +20,7 @@ define void @am2(i16 %x) nounwind { ret void } ; CHECK-LABEL: am2: -; CHECK: bis r12, &foo +; CHECK: bis.w r12, &foo @bar = external global [2 x i8] @@ -41,7 +41,7 @@ define void @am4(i16 %x) nounwind { ret void } ; CHECK-LABEL: am4: -; CHECK: bis r12, &32 +; CHECK: bis.w r12, &32 define void @am5(i16* %a, i16 %x) readonly { %1 = getelementptr inbounds i16, i16* %a, i16 2 @@ -51,7 +51,7 @@ define void @am5(i16* %a, i16 %x) readonly { ret void } ; CHECK-LABEL: am5: -; CHECK: bis r13, 4(r12) +; CHECK: bis.w r13, 4(r12) %S = type { i16, i16 } @baz = common global %S zeroinitializer @@ -63,7 +63,7 @@ define void @am6(i16 %x) nounwind { ret void } ; CHECK-LABEL: am6: -; CHECK: bis r12, &baz+2 +; CHECK: bis.w r12, &baz+2 %T = type { i16, [2 x i8] } @duh = external global %T diff --git a/llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll b/llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll index 0605e8e86ce..808aca0ea10 100644 --- a/llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll +++ b/llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll @@ -7,7 +7,7 @@ define i16 @am1(i16* %a) nounwind { ret i16 %1 } ; CHECK-LABEL: am1: -; CHECK: mov 0(r12), r12 +; CHECK: mov.w 0(r12), r12 @foo = external global i16 @@ -16,7 +16,7 @@ define i16 @am2() nounwind { ret i16 %1 } ; CHECK-LABEL: am2: -; CHECK: mov &foo, r12 +; CHECK: mov.w &foo, r12 @bar = internal constant [2 x i8] [ i8 32, i8 64 ] @@ -33,7 +33,7 @@ define i16 @am4() nounwind { ret i16 %1 } ; CHECK-LABEL: am4: -; CHECK: mov &32, r12 +; CHECK: mov.w &32, r12 define i16 @am5(i16* %a) nounwind { %1 = getelementptr i16, i16* %a, i16 2 @@ -41,7 +41,7 @@ define i16 @am5(i16* %a) nounwind { ret i16 %2 } ; CHECK-LABEL: am5: -; CHECK: mov 4(r12), r12 +; CHECK: mov.w 4(r12), r12 %S = type { i16, i16 } @baz = common global %S zeroinitializer, align 1 @@ -51,7 +51,7 @@ define i16 @am6() nounwind { ret i16 %1 } ; CHECK-LABEL: am6: -; CHECK: mov &baz+2, r12 +; CHECK: mov.w &baz+2, r12 %T = type { i16, [2 x i8] } @duh = internal constant %T { i16 16, [2 x i8][i8 32, i8 64 ] } diff --git a/llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll b/llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll index acc0b825711..c336289a60d 100644 --- a/llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll +++ b/llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll @@ -7,7 +7,7 @@ define void @am1(i16* %a, i16 %b) nounwind { ret void } ; CHECK-LABEL: am1: -; CHECK: mov r13, 0(r12) +; CHECK: mov.w r13, 0(r12) @foo = external global i16 @@ -16,7 +16,7 @@ define void @am2(i16 %a) nounwind { ret void } ; CHECK-LABEL: am2: -; CHECK: mov r12, &foo +; CHECK: mov.w r12, &foo @bar = external global [2 x i8] @@ -33,7 +33,7 @@ define void @am4(i16 %a) nounwind { ret void } ; CHECK-LABEL: am4: -; CHECK: mov r12, &32 +; CHECK: mov.w r12, &32 define void @am5(i16* nocapture %p, i16 %a) nounwind readonly { %1 = getelementptr inbounds i16, i16* %p, i16 2 @@ -41,7 +41,7 @@ define void @am5(i16* nocapture %p, i16 %a) nounwind readonly { ret void } ; CHECK-LABEL: am5: -; CHECK: mov r13, 4(r12) +; CHECK: mov.w r13, 4(r12) %S = type { i16, i16 } @baz = common global %S zeroinitializer, align 1 @@ -51,7 +51,7 @@ define void @am6(i16 %a) nounwind { ret void } ; CHECK-LABEL: am6: -; CHECK: mov r12, &baz+2 +; CHECK: mov.w r12, &baz+2 %T = type { i16, [2 x i8] } @duh = external global %T diff --git a/llvm/test/CodeGen/MSP430/Inst16mi.ll b/llvm/test/CodeGen/MSP430/Inst16mi.ll index bb99e28a1ba..38c16f2ba23 100644 --- a/llvm/test/CodeGen/MSP430/Inst16mi.ll +++ b/llvm/test/CodeGen/MSP430/Inst16mi.ll @@ -6,14 +6,14 @@ target triple = "msp430-generic-generic" define void @mov() nounwind { ; CHECK-LABEL: mov: -; CHECK: mov #2, &foo +; CHECK: mov.w #2, &foo store i16 2, i16 * @foo ret void } define void @add() nounwind { ; CHECK-LABEL: add: -; CHECK: incd &foo +; CHECK: add.w #2, &foo %1 = load i16, i16* @foo %2 = add i16 %1, 2 store i16 %2, i16 * @foo @@ -22,7 +22,7 @@ define void @add() nounwind { define void @and() nounwind { ; CHECK-LABEL: and: -; CHECK: and #2, &foo +; CHECK: and.w #2, &foo %1 = load i16, i16* @foo %2 = and i16 %1, 2 store i16 %2, i16 * @foo @@ -31,7 +31,7 @@ define void @and() nounwind { define void @bis() nounwind { ; CHECK-LABEL: bis: -; CHECK: bis #2, &foo +; CHECK: bis.w #2, &foo %1 = load i16, i16* @foo %2 = or i16 %1, 2 store i16 %2, i16 * @foo @@ -40,7 +40,7 @@ define void @bis() nounwind { define void @xor() nounwind { ; CHECK-LABEL: xor: -; CHECK: xor #2, &foo +; CHECK: xor.w #2, &foo %1 = load i16, i16* @foo %2 = xor i16 %1, 2 store i16 %2, i16 * @foo diff --git a/llvm/test/CodeGen/MSP430/Inst16mm.ll b/llvm/test/CodeGen/MSP430/Inst16mm.ll index 21fab42fd59..14a799b9171 100644 --- a/llvm/test/CodeGen/MSP430/Inst16mm.ll +++ b/llvm/test/CodeGen/MSP430/Inst16mm.ll @@ -6,7 +6,7 @@ target triple = "msp430-generic-generic" define void @mov() nounwind { ; CHECK-LABEL: mov: -; CHECK: mov &bar, &foo +; CHECK: mov.w &bar, &foo %1 = load i16, i16* @bar store i16 %1, i16* @foo ret void @@ -14,7 +14,7 @@ define void @mov() nounwind { define void @add() nounwind { ; CHECK-LABEL: add: -; CHECK: add &bar, &foo +; CHECK: add.w &bar, &foo %1 = load i16, i16* @bar %2 = load i16, i16* @foo %3 = add i16 %2, %1 @@ -24,7 +24,7 @@ define void @add() nounwind { define void @and() nounwind { ; CHECK-LABEL: and: -; CHECK: and &bar, &foo +; CHECK: and.w &bar, &foo %1 = load i16, i16* @bar %2 = load i16, i16* @foo %3 = and i16 %2, %1 @@ -34,7 +34,7 @@ define void @and() nounwind { define void @bis() nounwind { ; CHECK-LABEL: bis: -; CHECK: bis &bar, &foo +; CHECK: bis.w &bar, &foo %1 = load i16, i16* @bar %2 = load i16, i16* @foo %3 = or i16 %2, %1 @@ -44,7 +44,7 @@ define void @bis() nounwind { define void @xor() nounwind { ; CHECK-LABEL: xor: -; CHECK: xor &bar, &foo +; CHECK: xor.w &bar, &foo %1 = load i16, i16* @bar %2 = load i16, i16* @foo %3 = xor i16 %2, %1 @@ -64,6 +64,6 @@ entry: %0 = load i16, i16* %retval ; <i16> [#uses=1] ret i16 %0 ; CHECK-LABEL: mov2: -; CHECK-DAG: mov 2(r1), 6(r1) -; CHECK-DAG: mov 0(r1), 4(r1) +; CHECK-DAG: mov.w 2(r1), 6(r1) +; CHECK-DAG: mov.w 0(r1), 4(r1) } diff --git a/llvm/test/CodeGen/MSP430/Inst16mr.ll b/llvm/test/CodeGen/MSP430/Inst16mr.ll index e3f23d9c562..847c093f408 100644 --- a/llvm/test/CodeGen/MSP430/Inst16mr.ll +++ b/llvm/test/CodeGen/MSP430/Inst16mr.ll @@ -5,14 +5,14 @@ target triple = "msp430-generic-generic" define void @mov(i16 %a) nounwind { ; CHECK-LABEL: mov: -; CHECK: mov r12, &foo +; CHECK: mov.w r12, &foo store i16 %a, i16* @foo ret void } define void @add(i16 %a) nounwind { ; CHECK-LABEL: add: -; CHECK: add r12, &foo +; CHECK: add.w r12, &foo %1 = load i16, i16* @foo %2 = add i16 %a, %1 store i16 %2, i16* @foo @@ -21,7 +21,7 @@ define void @add(i16 %a) nounwind { define void @and(i16 %a) nounwind { ; CHECK-LABEL: and: -; CHECK: and r12, &foo +; CHECK: and.w r12, &foo %1 = load i16, i16* @foo %2 = and i16 %a, %1 store i16 %2, i16* @foo @@ -30,7 +30,7 @@ define void @and(i16 %a) nounwind { define void @bis(i16 %a) nounwind { ; CHECK-LABEL: bis: -; CHECK: bis r12, &foo +; CHECK: bis.w r12, &foo %1 = load i16, i16* @foo %2 = or i16 %a, %1 store i16 %2, i16* @foo @@ -39,7 +39,7 @@ define void @bis(i16 %a) nounwind { define void @bic(i16 zeroext %m) nounwind { ; CHECK-LABEL: bic: -; CHECK: bic r12, &foo +; CHECK: bic.w r12, &foo %1 = xor i16 %m, -1 %2 = load i16, i16* @foo %3 = and i16 %2, %1 @@ -49,7 +49,7 @@ define void @bic(i16 zeroext %m) nounwind { define void @xor(i16 %a) nounwind { ; CHECK-LABEL: xor: -; CHECK: xor r12, &foo +; CHECK: xor.w r12, &foo %1 = load i16, i16* @foo %2 = xor i16 %a, %1 store i16 %2, i16* @foo diff --git a/llvm/test/CodeGen/MSP430/Inst16ri.ll b/llvm/test/CodeGen/MSP430/Inst16ri.ll index 58b2791194a..3a4bb6a93d9 100644 --- a/llvm/test/CodeGen/MSP430/Inst16ri.ll +++ b/llvm/test/CodeGen/MSP430/Inst16ri.ll @@ -4,34 +4,34 @@ target triple = "msp430-generic-generic" define i16 @mov() nounwind { ; CHECK-LABEL: mov: -; CHECK: mov #1, r12 +; CHECK: mov.w #1, r12 ret i16 1 } define i16 @add(i16 %a, i16 %b) nounwind { ; CHECK-LABEL: add: -; CHECK: inc r12 +; CHECK: add.w #1, r12 %1 = add i16 %a, 1 ret i16 %1 } define i16 @and(i16 %a, i16 %b) nounwind { ; CHECK-LABEL: and: -; CHECK: and #1, r12 +; CHECK: and.w #1, r12 %1 = and i16 %a, 1 ret i16 %1 } define i16 @bis(i16 %a, i16 %b) nounwind { ; CHECK-LABEL: bis: -; CHECK: bis #1, r12 +; CHECK: bis.w #1, r12 %1 = or i16 %a, 1 ret i16 %1 } define i16 @xor(i16 %a, i16 %b) nounwind { ; CHECK-LABEL: xor: -; CHECK: xor #1, r12 +; CHECK: xor.w #1, r12 %1 = xor i16 %a, 1 ret i16 %1 } diff --git a/llvm/test/CodeGen/MSP430/Inst16rm.ll b/llvm/test/CodeGen/MSP430/Inst16rm.ll index 8a3cd0a46fb..44b8f39d8fa 100644 --- a/llvm/test/CodeGen/MSP430/Inst16rm.ll +++ b/llvm/test/CodeGen/MSP430/Inst16rm.ll @@ -5,7 +5,7 @@ target triple = "msp430-generic-generic" define i16 @add(i16 %a) nounwind { ; CHECK-LABEL: add: -; CHECK: add &foo, r12 +; CHECK: add.w &foo, r12 %1 = load i16, i16* @foo %2 = add i16 %a, %1 ret i16 %2 @@ -13,7 +13,7 @@ define i16 @add(i16 %a) nounwind { define i16 @and(i16 %a) nounwind { ; CHECK-LABEL: and: -; CHECK: and &foo, r12 +; CHECK: and.w &foo, r12 %1 = load i16, i16* @foo %2 = and i16 %a, %1 ret i16 %2 @@ -21,7 +21,7 @@ define i16 @and(i16 %a) nounwind { define i16 @bis(i16 %a) nounwind { ; CHECK-LABEL: bis: -; CHECK: bis &foo, r12 +; CHECK: bis.w &foo, r12 %1 = load i16, i16* @foo %2 = or i16 %a, %1 ret i16 %2 @@ -29,7 +29,7 @@ define i16 @bis(i16 %a) nounwind { define i16 @bic(i16 %a) nounwind { ; CHECK-LABEL: bic: -; CHECK: bic &foo, r12 +; CHECK: bic.w &foo, r12 %1 = load i16, i16* @foo %2 = xor i16 %1, -1 %3 = and i16 %a, %2 @@ -38,7 +38,7 @@ define i16 @bic(i16 %a) nounwind { define i16 @xor(i16 %a) nounwind { ; CHECK-LABEL: xor: -; CHECK: xor &foo, r12 +; CHECK: xor.w &foo, r12 %1 = load i16, i16* @foo %2 = xor i16 %a, %1 ret i16 %2 diff --git a/llvm/test/CodeGen/MSP430/Inst16rr.ll b/llvm/test/CodeGen/MSP430/Inst16rr.ll index 124d42113a2..75440ca2b40 100644 --- a/llvm/test/CodeGen/MSP430/Inst16rr.ll +++ b/llvm/test/CodeGen/MSP430/Inst16rr.ll @@ -4,34 +4,34 @@ target triple = "msp430-generic-generic" define i16 @mov(i16 %a, i16 %b) nounwind { ; CHECK-LABEL: mov: -; CHECK: mov r13, r12 +; CHECK: mov.w r13, r12 ret i16 %b } define i16 @add(i16 %a, i16 %b) nounwind { ; CHECK-LABEL: add: -; CHECK: add r13, r12 +; CHECK: add.w r13, r12 %1 = add i16 %a, %b ret i16 %1 } define i16 @and(i16 %a, i16 %b) nounwind { ; CHECK-LABEL: and: -; CHECK: and r13, r12 +; CHECK: and.w r13, r12 %1 = and i16 %a, %b ret i16 %1 } define i16 @bis(i16 %a, i16 %b) nounwind { ; CHECK-LABEL: bis: -; CHECK: bis r13, r12 +; CHECK: bis.w r13, r12 %1 = or i16 %a, %b ret i16 %1 } define i16 @bic(i16 %a, i16 %b) nounwind { ; CHECK-LABEL: bic: -; CHECK: bic r13, r12 +; CHECK: bic.w r13, r12 %1 = xor i16 %b, -1 %2 = and i16 %a, %1 ret i16 %2 @@ -39,7 +39,7 @@ define i16 @bic(i16 %a, i16 %b) nounwind { define i16 @xor(i16 %a, i16 %b) nounwind { ; CHECK-LABEL: xor: -; CHECK: xor r13, r12 +; CHECK: xor.w r13, r12 %1 = xor i16 %a, %b ret i16 %1 } diff --git a/llvm/test/CodeGen/MSP430/Inst8mi.ll b/llvm/test/CodeGen/MSP430/Inst8mi.ll index 36eb3f91f84..ff22d7e1eb3 100644 --- a/llvm/test/CodeGen/MSP430/Inst8mi.ll +++ b/llvm/test/CodeGen/MSP430/Inst8mi.ll @@ -12,7 +12,7 @@ define void @mov() nounwind { define void @add() nounwind { ; CHECK-LABEL: add: -; CHECK: incd.b &foo +; CHECK: add.b #2, &foo %1 = load i8, i8* @foo %2 = add i8 %1, 2 store i8 %2, i8 * @foo diff --git a/llvm/test/CodeGen/MSP430/Inst8ri.ll b/llvm/test/CodeGen/MSP430/Inst8ri.ll index ff3dee8bfb9..0e50f17f2a5 100644 --- a/llvm/test/CodeGen/MSP430/Inst8ri.ll +++ b/llvm/test/CodeGen/MSP430/Inst8ri.ll @@ -10,7 +10,7 @@ define i8 @mov() nounwind { define i8 @add(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: add: -; CHECK: inc.b r12 +; CHECK: add.b #1, r12 %1 = add i8 %a, 1 ret i8 %1 } diff --git a/llvm/test/CodeGen/MSP430/Inst8rr.ll b/llvm/test/CodeGen/MSP430/Inst8rr.ll index 20c4fa5aacf..f37bc32a28f 100644 --- a/llvm/test/CodeGen/MSP430/Inst8rr.ll +++ b/llvm/test/CodeGen/MSP430/Inst8rr.ll @@ -4,7 +4,7 @@ target triple = "msp430-generic-generic" define i8 @mov(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: mov: -; CHECK: mov r13, r12 +; CHECK: mov.{{[bw]}} r13, r12 ret i8 %b } @@ -17,14 +17,14 @@ define i8 @add(i8 %a, i8 %b) nounwind { define i8 @and(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: and: -; CHECK: and r13, r12 +; CHECK: and.w r13, r12 %1 = and i8 %a, %b ret i8 %1 } define i8 @bis(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: bis: -; CHECK: bis r13, r12 +; CHECK: bis.w r13, r12 %1 = or i8 %a, %b ret i8 %1 } @@ -39,7 +39,7 @@ define i8 @bic(i8 %a, i8 %b) nounwind { define i8 @xor(i8 %a, i8 %b) nounwind { ; CHECK-LABEL: xor: -; CHECK: xor r13, r12 +; CHECK: xor.w r13, r12 %1 = xor i8 %a, %b ret i8 %1 } diff --git a/llvm/test/CodeGen/MSP430/asm-clobbers.ll b/llvm/test/CodeGen/MSP430/asm-clobbers.ll index 0a0335057f1..216a3fe4018 100644 --- a/llvm/test/CodeGen/MSP430/asm-clobbers.ll +++ b/llvm/test/CodeGen/MSP430/asm-clobbers.ll @@ -6,8 +6,8 @@ target triple = "msp430---elf" define void @test() { entry: ; CHECK-LABEL: test: -; CHECK: push r10 +; CHECK: push.w r10 call void asm sideeffect "", "~{r10}"() -; CHECK: pop r10 +; CHECK: pop.w r10 ret void } diff --git a/llvm/test/CodeGen/MSP430/bit.ll b/llvm/test/CodeGen/MSP430/bit.ll index a4b781243b4..172822fbb5f 100644 --- a/llvm/test/CodeGen/MSP430/bit.ll +++ b/llvm/test/CodeGen/MSP430/bit.ll @@ -93,7 +93,7 @@ define i16 @bitwrr(i16 %a, i16 %b) nounwind { ret i16 %t3 } ; CHECK-LABEL: bitwrr: -; CHECK: bit r13, r12 +; CHECK: bit.w r13, r12 define i16 @bitwri(i16 %a) nounwind { %t1 = and i16 %a, 4080 @@ -102,7 +102,7 @@ define i16 @bitwri(i16 %a) nounwind { ret i16 %t3 } ; CHECK-LABEL: bitwri: -; CHECK: bit #4080, r12 +; CHECK: bit.w #4080, r12 define i16 @bitwir(i16 %a) nounwind { %t1 = and i16 4080, %a @@ -111,7 +111,7 @@ define i16 @bitwir(i16 %a) nounwind { ret i16 %t3 } ; CHECK-LABEL: bitwir: -; CHECK: bit #4080, r12 +; CHECK: bit.w #4080, r12 define i16 @bitwmi() nounwind { %t1 = load i16, i16* @foo16 @@ -121,7 +121,7 @@ define i16 @bitwmi() nounwind { ret i16 %t4 } ; CHECK-LABEL: bitwmi: -; CHECK: bit #4080, &foo16 +; CHECK: bit.w #4080, &foo16 define i16 @bitwim() nounwind { %t1 = load i16, i16* @foo16 @@ -131,7 +131,7 @@ define i16 @bitwim() nounwind { ret i16 %t4 } ; CHECK-LABEL: bitwim: -; CHECK: bit #4080, &foo16 +; CHECK: bit.w #4080, &foo16 define i16 @bitwrm(i16 %a) nounwind { %t1 = load i16, i16* @foo16 @@ -141,7 +141,7 @@ define i16 @bitwrm(i16 %a) nounwind { ret i16 %t4 } ; CHECK-LABEL: bitwrm: -; CHECK: bit &foo16, r12 +; CHECK: bit.w &foo16, r12 define i16 @bitwmr(i16 %a) nounwind { %t1 = load i16, i16* @foo16 @@ -151,7 +151,7 @@ define i16 @bitwmr(i16 %a) nounwind { ret i16 %t4 } ; CHECK-LABEL: bitwmr: -; CHECK: bit r12, &foo16 +; CHECK: bit.w r12, &foo16 define i16 @bitwmm() nounwind { %t1 = load i16, i16* @foo16 @@ -162,5 +162,5 @@ define i16 @bitwmm() nounwind { ret i16 %t5 } ; CHECK-LABEL: bitwmm: -; CHECK: bit &bar16, &foo16 +; CHECK: bit.w &bar16, &foo16 diff --git a/llvm/test/CodeGen/MSP430/byval.ll b/llvm/test/CodeGen/MSP430/byval.ll index 838e883d4be..401896b43c2 100644 --- a/llvm/test/CodeGen/MSP430/byval.ll +++ b/llvm/test/CodeGen/MSP430/byval.ll @@ -9,7 +9,7 @@ target triple = "msp430---elf" define i16 @callee(%struct.Foo* byval %f) nounwind { entry: ; CHECK-LABEL: callee: -; CHECK: mov 2(r1), r12 +; CHECK: mov.w 2(r1), r12 %0 = getelementptr inbounds %struct.Foo, %struct.Foo* %f, i32 0, i32 0 %1 = load i16, i16* %0, align 2 ret i16 %1 @@ -18,9 +18,9 @@ entry: define void @caller() nounwind { entry: ; CHECK-LABEL: caller: -; CHECK: mov &foo+4, 4(r1) -; CHECK-NEXT: mov &foo+2, 2(r1) -; CHECK-NEXT: mov &foo, 0(r1) +; CHECK: mov.w &foo+4, 4(r1) +; CHECK-NEXT: mov.w &foo+2, 2(r1) +; CHECK-NEXT: mov.w &foo, 0(r1) %call = call i16 @callee(%struct.Foo* byval @foo) ret void } diff --git a/llvm/test/CodeGen/MSP430/cc_args.ll b/llvm/test/CodeGen/MSP430/cc_args.ll index eb7e470a9b6..70ac901f7e4 100644 --- a/llvm/test/CodeGen/MSP430/cc_args.ll +++ b/llvm/test/CodeGen/MSP430/cc_args.ll @@ -7,50 +7,50 @@ define void @test() #0 { entry: ; CHECK: test: -; CHECK: mov #1, r12 +; CHECK: mov.w #1, r12 ; CHECK: call #f_i16 call void @f_i16(i16 1) -; CHECK: mov #772, r12 -; CHECK: mov #258, r13 +; CHECK: mov.w #772, r12 +; CHECK: mov.w #258, r13 ; CHECK: call #f_i32 call void @f_i32(i32 16909060) -; CHECK: mov #1800, r12 -; CHECK: mov #1286, r13 -; CHECK: mov #772, r14 -; CHECK: mov #258, r15 +; CHECK: mov.w #1800, r12 +; CHECK: mov.w #1286, r13 +; CHECK: mov.w #772, r14 +; CHECK: mov.w #258, r15 ; CHECK: call #f_i64 call void @f_i64(i64 72623859790382856) -; CHECK: mov #772, r12 -; CHECK: mov #258, r13 -; CHECK: mov #1800, r14 -; CHECK: mov #1286, r15 +; CHECK: mov.w #772, r12 +; CHECK: mov.w #258, r13 +; CHECK: mov.w #1800, r14 +; CHECK: mov.w #1286, r15 ; CHECK: call #f_i32_i32 call void @f_i32_i32(i32 16909060, i32 84281096) -; CHECK: mov #1, r12 -; CHECK: mov #772, r13 -; CHECK: mov #258, r14 -; CHECK: mov #2, r15 +; CHECK: mov.w #1, r12 +; CHECK: mov.w #772, r13 +; CHECK: mov.w #258, r14 +; CHECK: mov.w #2, r15 ; CHECK: call #f_i16_i32_i16 call void @f_i16_i32_i16(i16 1, i32 16909060, i16 2) -; CHECK: mov #1286, 0(r1) -; CHECK: mov #1, r12 -; CHECK: mov #772, r13 -; CHECK: mov #258, r14 -; CHECK: mov #1800, r15 +; CHECK: mov.w #1286, 0(r1) +; CHECK: mov.w #1, r12 +; CHECK: mov.w #772, r13 +; CHECK: mov.w #258, r14 +; CHECK: mov.w #1800, r15 ; CHECK: call #f_i16_i32_i32 call void @f_i16_i32_i32(i16 1, i32 16909060, i32 84281096) -; CHECK: mov #258, 6(r1) -; CHECK: mov #772, 4(r1) -; CHECK: mov #1286, 2(r1) -; CHECK: mov #1800, 0(r1) -; CHECK: mov #1, r12 -; CHECK: mov #2, r13 +; CHECK: mov.w #258, 6(r1) +; CHECK: mov.w #772, 4(r1) +; CHECK: mov.w #1286, 2(r1) +; CHECK: mov.w #1800, 0(r1) +; CHECK: mov.w #1, r12 +; CHECK: mov.w #2, r13 ; CHECK: call #f_i16_i64_i16 call void @f_i16_i64_i16(i16 1, i64 72623859790382856, i16 2) @@ -63,75 +63,75 @@ entry: define void @f_i16(i16 %a) #0 { ; CHECK: f_i16: -; CHECK: mov r12, &g_i16 +; CHECK: mov.w r12, &g_i16 store volatile i16 %a, i16* @g_i16, align 2 ret void } define void @f_i32(i32 %a) #0 { ; CHECK: f_i32: -; CHECK: mov r13, &g_i32+2 -; CHECK: mov r12, &g_i32 +; CHECK: mov.w r13, &g_i32+2 +; CHECK: mov.w r12, &g_i32 store volatile i32 %a, i32* @g_i32, align 2 ret void } define void @f_i64(i64 %a) #0 { ; CHECK: f_i64: -; CHECK: mov r15, &g_i64+6 -; CHECK: mov r14, &g_i64+4 -; CHECK: mov r13, &g_i64+2 -; CHECK: mov r12, &g_i64 +; CHECK: mov.w r15, &g_i64+6 +; CHECK: mov.w r14, &g_i64+4 +; CHECK: mov.w r13, &g_i64+2 +; CHECK: mov.w r12, &g_i64 store volatile i64 %a, i64* @g_i64, align 2 ret void } define void @f_i32_i32(i32 %a, i32 %b) #0 { ; CHECK: f_i32_i32: -; CHECK: mov r13, &g_i32+2 -; CHECK: mov r12, &g_i32 +; CHECK: mov.w r13, &g_i32+2 +; CHECK: mov.w r12, &g_i32 store volatile i32 %a, i32* @g_i32, align 2 -; CHECK: mov r15, &g_i32+2 -; CHECK: mov r14, &g_i32 +; CHECK: mov.w r15, &g_i32+2 +; CHECK: mov.w r14, &g_i32 store volatile i32 %b, i32* @g_i32, align 2 ret void } define void @f_i16_i32_i32(i16 %a, i32 %b, i32 %c) #0 { ; CHECK: f_i16_i32_i32: -; CHECK: mov r12, &g_i16 +; CHECK: mov.w r12, &g_i16 store volatile i16 %a, i16* @g_i16, align 2 -; CHECK: mov r14, &g_i32+2 -; CHECK: mov r13, &g_i32 +; CHECK: mov.w r14, &g_i32+2 +; CHECK: mov.w r13, &g_i32 store volatile i32 %b, i32* @g_i32, align 2 -; CHECK: mov r15, &g_i32 -; CHECK: mov 4(r4), &g_i32+2 +; CHECK: mov.w r15, &g_i32 +; CHECK: mov.w 4(r4), &g_i32+2 store volatile i32 %c, i32* @g_i32, align 2 ret void } define void @f_i16_i32_i16(i16 %a, i32 %b, i16 %c) #0 { ; CHECK: f_i16_i32_i16: -; CHECK: mov r12, &g_i16 +; CHECK: mov.w r12, &g_i16 store volatile i16 %a, i16* @g_i16, align 2 -; CHECK: mov r14, &g_i32+2 -; CHECK: mov r13, &g_i32 +; CHECK: mov.w r14, &g_i32+2 +; CHECK: mov.w r13, &g_i32 store volatile i32 %b, i32* @g_i32, align 2 -; CHECK: mov r15, &g_i16 +; CHECK: mov.w r15, &g_i16 store volatile i16 %c, i16* @g_i16, align 2 ret void } define void @f_i16_i64_i16(i16 %a, i64 %b, i16 %c) #0 { ; CHECK: f_i16_i64_i16: -; CHECK: mov r12, &g_i16 +; CHECK: mov.w r12, &g_i16 store volatile i16 %a, i16* @g_i16, align 2 -;CHECK: mov 10(r4), &g_i64+6 -;CHECK: mov 8(r4), &g_i64+4 -;CHECK: mov 6(r4), &g_i64+2 -;CHECK: mov 4(r4), &g_i64 +;CHECK: mov.w 10(r4), &g_i64+6 +;CHECK: mov.w 8(r4), &g_i64+4 +;CHECK: mov.w 6(r4), &g_i64+2 +;CHECK: mov.w 4(r4), &g_i64 store volatile i64 %b, i64* @g_i64, align 2 -;CHECK: mov r13, &g_i16 +;CHECK: mov.w r13, &g_i16 store volatile i16 %c, i16* @g_i16, align 2 ret void } diff --git a/llvm/test/CodeGen/MSP430/cc_ret.ll b/llvm/test/CodeGen/MSP430/cc_ret.ll index b4bb0554208..937db6dbf3b 100644 --- a/llvm/test/CodeGen/MSP430/cc_ret.ll +++ b/llvm/test/CodeGen/MSP430/cc_ret.ll @@ -8,21 +8,21 @@ entry: ; CHECK: test: ; CHECK: call #f_i16 -; CHECK: mov r12, &g_i16 +; CHECK: mov.w r12, &g_i16 %0 = call i16 @f_i16() store volatile i16 %0, i16* @g_i16 ; CHECK: call #f_i32 -; CHECK: mov r13, &g_i32+2 -; CHECK: mov r12, &g_i32 +; CHECK: mov.w r13, &g_i32+2 +; CHECK: mov.w r12, &g_i32 %1 = call i32 @f_i32() store volatile i32 %1, i32* @g_i32 ; CHECK: call #f_i64 -; CHECK: mov r15, &g_i64+6 -; CHECK: mov r14, &g_i64+4 -; CHECK: mov r13, &g_i64+2 -; CHECK: mov r12, &g_i64 +; CHECK: mov.w r15, &g_i64+6 +; CHECK: mov.w r14, &g_i64+4 +; CHECK: mov.w r13, &g_i64+2 +; CHECK: mov.w r12, &g_i64 %2 = call i64 @f_i64() store volatile i64 %2, i64* @g_i64 @@ -35,25 +35,25 @@ entry: define i16 @f_i16() #0 { ; CHECK: f_i16: -; CHECK: mov #1, r12 +; CHECK: mov.w #1, r12 ; CHECK: ret ret i16 1 } define i32 @f_i32() #0 { ; CHECK: f_i32: -; CHECK: mov #772, r12 -; CHECK: mov #258, r13 +; CHECK: mov.w #772, r12 +; CHECK: mov.w #258, r13 ; CHECK: ret ret i32 16909060 } define i64 @f_i64() #0 { ; CHECK: f_i64: -; CHECK: mov #1800, r12 -; CHECK: mov #1286, r13 -; CHECK: mov #772, r14 -; CHECK: mov #258, r15 +; CHECK: mov.w #1800, r12 +; CHECK: mov.w #1286, r13 +; CHECK: mov.w #772, r14 +; CHECK: mov.w #258, r15 ; CHECK: ret ret i64 72623859790382856 } diff --git a/llvm/test/CodeGen/MSP430/fp.ll b/llvm/test/CodeGen/MSP430/fp.ll index 87c4055829c..2559e23ae1f 100644 --- a/llvm/test/CodeGen/MSP430/fp.ll +++ b/llvm/test/CodeGen/MSP430/fp.ll @@ -6,13 +6,13 @@ target triple = "msp430---elf" define void @fp() nounwind { entry: ; CHECK-LABEL: fp: -; CHECK: push r4 -; CHECK: mov r1, r4 -; CHECK: sub #2, r1 +; CHECK: push.w r4 +; CHECK: mov.w r1, r4 +; CHECK: sub.w #2, r1 %i = alloca i16, align 2 -; CHECK: clr -2(r4) +; CHECK: mov.w #0, -2(r4) store i16 0, i16* %i, align 2 -; CHECK: pop r4 +; CHECK: pop.w r4 ret void } diff --git a/llvm/test/CodeGen/MSP430/jumptable.ll b/llvm/test/CodeGen/MSP430/jumptable.ll index 6121f7ebed6..49f23166a0a 100644 --- a/llvm/test/CodeGen/MSP430/jumptable.ll +++ b/llvm/test/CodeGen/MSP430/jumptable.ll @@ -7,15 +7,15 @@ target triple = "msp430---elf" define i16 @test(i16 %i) #0 { entry: ; CHECK-LABEL: test: -; CHECK: sub #4, r1 -; CHECK-NEXT: mov r12, 0(r1) -; CHECK-NEXT: cmp #4, r12 +; CHECK: sub.w #4, r1 +; CHECK-NEXT: mov.w r12, 0(r1) +; CHECK-NEXT: cmp.w #4, r12 ; CHECK-NEXT: jhs .LBB0_3 %retval = alloca i16, align 2 %i.addr = alloca i16, align 2 store i16 %i, i16* %i.addr, align 2 %0 = load i16, i16* %i.addr, align 2 -; CHECK: add r12, r12 +; CHECK: rla.w r12 ; CHECK-NEXT: br .LJTI0_0(r12) switch i16 %0, label %sw.default [ i16 0, label %sw.bb diff --git a/llvm/test/CodeGen/MSP430/memset.ll b/llvm/test/CodeGen/MSP430/memset.ll index 0f83b607820..10b506c60d9 100644 --- a/llvm/test/CodeGen/MSP430/memset.ll +++ b/llvm/test/CodeGen/MSP430/memset.ll @@ -9,9 +9,9 @@ define void @test() nounwind { entry: ; CHECK-LABEL: test: %0 = load i8*, i8** @buf, align 2 -; CHECK: mov &buf, r12 -; CHECK-NEXT: mov #5, r13 -; CHECK-NEXT: mov #128, r14 +; CHECK: mov.w &buf, r12 +; CHECK-NEXT: mov.w #5, r13 +; CHECK-NEXT: mov.w #128, r14 ; CHECK-NEXT: call #memset call void @llvm.memset.p0i8.i16(i8* %0, i8 5, i16 128, i1 false) ret void diff --git a/llvm/test/CodeGen/MSP430/misched-msp430.ll b/llvm/test/CodeGen/MSP430/misched-msp430.ll index f44f10ccd3e..3d18fa005a6 100644 --- a/llvm/test/CodeGen/MSP430/misched-msp430.ll +++ b/llvm/test/CodeGen/MSP430/misched-msp430.ll @@ -10,7 +10,7 @@ target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16" ; only verifies that the code generator ran successfully. ; ; CHECK-LABEL: @f -; CHECK: mov &y, &x +; CHECK: mov.w &y, &x ; CHECK: ret define void @f() { entry: diff --git a/llvm/test/CodeGen/MSP430/postinc.ll b/llvm/test/CodeGen/MSP430/postinc.ll index 20ee8fb3c85..75a927f33fc 100644 --- a/llvm/test/CodeGen/MSP430/postinc.ll +++ b/llvm/test/CodeGen/MSP430/postinc.ll @@ -12,7 +12,7 @@ for.body: ; preds = %for.body, %entry %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1] %arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1] ; CHECK-LABEL: add: -; CHECK: add @r{{[0-9]+}}+, r{{[0-9]+}} +; CHECK: add.w @r{{[0-9]+}}+, r{{[0-9]+}} %tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1] %add = add i16 %tmp4, %sum.09 ; <i16> [#uses=2] %inc = add i16 %i.010, 1 ; <i16> [#uses=2] @@ -34,7 +34,7 @@ for.body: ; preds = %for.body, %entry %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1] %arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1] ; CHECK-LABEL: sub: -; CHECK: sub @r{{[0-9]+}}+, r{{[0-9]+}} +; CHECK: sub.w @r{{[0-9]+}}+, r{{[0-9]+}} %tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1] %add = sub i16 %tmp4, %sum.09 ; <i16> [#uses=2] %inc = add i16 %i.010, 1 ; <i16> [#uses=2] @@ -56,7 +56,7 @@ for.body: ; preds = %for.body, %entry %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1] %arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1] ; CHECK-LABEL: or: -; CHECK: bis @r{{[0-9]+}}+, r{{[0-9]+}} +; CHECK: bis.w @r{{[0-9]+}}+, r{{[0-9]+}} %tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1] %add = or i16 %tmp4, %sum.09 ; <i16> [#uses=2] %inc = add i16 %i.010, 1 ; <i16> [#uses=2] @@ -78,7 +78,7 @@ for.body: ; preds = %for.body, %entry %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1] %arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1] ; CHECK-LABEL: xor: -; CHECK: xor @r{{[0-9]+}}+, r{{[0-9]+}} +; CHECK: xor.w @r{{[0-9]+}}+, r{{[0-9]+}} %tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1] %add = xor i16 %tmp4, %sum.09 ; <i16> [#uses=2] %inc = add i16 %i.010, 1 ; <i16> [#uses=2] @@ -100,7 +100,7 @@ for.body: ; preds = %for.body, %entry %sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1] %arrayidx = getelementptr i16, i16* %a, i16 %i.010 ; <i16*> [#uses=1] ; CHECK-LABEL: and: -; CHECK: and @r{{[0-9]+}}+, r{{[0-9]+}} +; CHECK: and.w @r{{[0-9]+}}+, r{{[0-9]+}} %tmp4 = load i16, i16* %arrayidx ; <i16> [#uses=1] %add = and i16 %tmp4, %sum.09 ; <i16> [#uses=2] %inc = add i16 %i.010, 1 ; <i16> [#uses=2] diff --git a/llvm/test/CodeGen/MSP430/select-use-sr.ll b/llvm/test/CodeGen/MSP430/select-use-sr.ll index 159fc93db5a..3f67fb85f79 100644 --- a/llvm/test/CodeGen/MSP430/select-use-sr.ll +++ b/llvm/test/CodeGen/MSP430/select-use-sr.ll @@ -6,8 +6,8 @@ target triple = "msp430" ; Test that CMP instruction is not removed by MachineCSE. ; ; CHECK-LABEL: @f -; CHECK: cmp r15, r13 -; CHECK: cmp r15, r13 +; CHECK: cmp.w r15, r13 +; CHECK: cmp.w r15, r13 ; CHECK-NEXT: jeq .LBB0_2 define i16 @f(i16, i16, i16, i16) { entry: diff --git a/llvm/test/CodeGen/MSP430/setcc.ll b/llvm/test/CodeGen/MSP430/setcc.ll index 52baf642903..6e2ec8ea3ea 100644 --- a/llvm/test/CodeGen/MSP430/setcc.ll +++ b/llvm/test/CodeGen/MSP430/setcc.ll @@ -9,10 +9,10 @@ define i16 @sccweqand(i16 %a, i16 %b) nounwind { ret i16 %t3 } ; CHECK-LABEL: sccweqand: -; CHECK: bit r13, r12 -; CHECK: mov r2, r12 -; CHECK: rra r12 -; CHECK: and #1, r12 +; CHECK: bit.w r13, r12 +; CHECK: mov.w r2, r12 +; CHECK: rra.w r12 +; CHECK: and.w #1, r12 define i16 @sccwneand(i16 %a, i16 %b) nounwind { %t1 = and i16 %a, %b @@ -21,9 +21,9 @@ define i16 @sccwneand(i16 %a, i16 %b) nounwind { ret i16 %t3 } ; CHECK-LABEL: sccwneand: -; CHECK: bit r13, r12 -; CHECK: mov r2, r12 -; CHECK: and #1, r12 +; CHECK: bit.w r13, r12 +; CHECK: mov.w r2, r12 +; CHECK: and.w #1, r12 define i16 @sccwne(i16 %a, i16 %b) nounwind { %t1 = icmp ne i16 %a, %b @@ -31,11 +31,11 @@ define i16 @sccwne(i16 %a, i16 %b) nounwind { ret i16 %t2 } ; CHECK-LABEL:sccwne: -; CHECK: cmp r13, r12 -; CHECK: mov r2, r13 -; CHECK: rra r13 -; CHECK: mov #1, r12 -; CHECK: bic r13, r12 +; CHECK: cmp.w r13, r12 +; CHECK: mov.w r2, r13 +; CHECK: rra.w r13 +; CHECK: mov.w #1, r12 +; CHECK: bic.w r13, r12 define i16 @sccweq(i16 %a, i16 %b) nounwind { %t1 = icmp eq i16 %a, %b @@ -43,10 +43,10 @@ define i16 @sccweq(i16 %a, i16 %b) nounwind { ret i16 %t2 } ; CHECK-LABEL:sccweq: -; CHECK: cmp r13, r12 -; CHECK: mov r2, r12 -; CHECK: rra r12 -; CHECK: and #1, r12 +; CHECK: cmp.w r13, r12 +; CHECK: mov.w r2, r12 +; CHECK: rra.w r12 +; CHECK: and.w #1, r12 define i16 @sccwugt(i16 %a, i16 %b) nounwind { %t1 = icmp ugt i16 %a, %b @@ -54,9 +54,9 @@ define i16 @sccwugt(i16 %a, i16 %b) nounwind { ret i16 %t2 } ; CHECK-LABEL:sccwugt: -; CHECK: cmp r12, r13 -; CHECK: mov #1, r12 -; CHECK: bic r2, r12 +; CHECK: cmp.w r12, r13 +; CHECK: mov.w #1, r12 +; CHECK: bic.w r2, r12 define i16 @sccwuge(i16 %a, i16 %b) nounwind { %t1 = icmp uge i16 %a, %b @@ -64,9 +64,9 @@ define i16 @sccwuge(i16 %a, i16 %b) nounwind { ret i16 %t2 } ; CHECK-LABEL:sccwuge: -; CHECK: cmp r13, r12 -; CHECK: mov r2, r12 -; CHECK: and #1, r12 +; CHECK: cmp.w r13, r12 +; CHECK: mov.w r2, r12 +; CHECK: and.w #1, r12 define i16 @sccwult(i16 %a, i16 %b) nounwind { %t1 = icmp ult i16 %a, %b @@ -74,9 +74,9 @@ define i16 @sccwult(i16 %a, i16 %b) nounwind { ret i16 %t2 } ; CHECK-LABEL:sccwult: -; CHECK: cmp r13, r12 -; CHECK: mov #1, r12 -; CHECK: bic r2, r12 +; CHECK: cmp.w r13, r12 +; CHECK: mov.w #1, r12 +; CHECK: bic.w r2, r12 define i16 @sccwule(i16 %a, i16 %b) nounwind { %t1 = icmp ule i16 %a, %b @@ -84,9 +84,9 @@ define i16 @sccwule(i16 %a, i16 %b) nounwind { ret i16 %t2 } ; CHECK-LABEL:sccwule: -; CHECK: cmp r12, r13 -; CHECK: mov r2, r12 -; CHECK: and #1, r12 +; CHECK: cmp.w r12, r13 +; CHECK: mov.w r2, r12 +; CHECK: and.w #1, r12 define i16 @sccwsgt(i16 %a, i16 %b) nounwind { %t1 = icmp sgt i16 %a, %b diff --git a/llvm/test/CodeGen/MSP430/shifts.ll b/llvm/test/CodeGen/MSP430/shifts.ll index 6d4050f42be..22ae59ef4b0 100644 --- a/llvm/test/CodeGen/MSP430/shifts.ll +++ b/llvm/test/CodeGen/MSP430/shifts.ll @@ -21,7 +21,7 @@ entry: define zeroext i8 @shl8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone { entry: ; CHECK: shl8 -; CHECK: add.b +; CHECK: rla.b %shl = shl i8 %a, %cnt ret i8 %shl } @@ -29,7 +29,7 @@ entry: define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone { entry: ; CHECK-LABEL: lshr16: -; CHECK: rrc +; CHECK: rrc.w %shr = lshr i16 %a, %cnt ret i16 %shr } @@ -37,7 +37,7 @@ entry: define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone { entry: ; CHECK-LABEL: ashr16: -; CHECK: rra +; CHECK: rra.w %shr = ashr i16 %a, %cnt ret i16 %shr } @@ -45,7 +45,7 @@ entry: define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone { entry: ; CHECK-LABEL: shl16: -; CHECK: add +; CHECK: rla.w %shl = shl i16 %a, %cnt ret i16 %shl } diff --git a/llvm/test/CodeGen/MSP430/struct-return.ll b/llvm/test/CodeGen/MSP430/struct-return.ll index a52ea1b702a..c28bf06af43 100644 --- a/llvm/test/CodeGen/MSP430/struct-return.ll +++ b/llvm/test/CodeGen/MSP430/struct-return.ll @@ -9,14 +9,14 @@ target triple = "msp430---elf" define %s @fred() #0 { ; CHECK-LABEL: fred: -; CHECK: mov #2314, 14(r12) -; CHECK: mov #2828, 12(r12) -; CHECK: mov #3342, 10(r12) -; CHECK: mov #3840, 8(r12) -; CHECK: mov #258, 6(r12) -; CHECK: mov #772, 4(r12) -; CHECK: mov #1286, 2(r12) -; CHECK: mov #1800, 0(r12) +; CHECK: mov.w #2314, 14(r12) +; CHECK: mov.w #2828, 12(r12) +; CHECK: mov.w #3342, 10(r12) +; CHECK: mov.w #3840, 8(r12) +; CHECK: mov.w #258, 6(r12) +; CHECK: mov.w #772, 4(r12) +; CHECK: mov.w #1286, 2(r12) +; CHECK: mov.w #1800, 0(r12) ret %s {i64 72623859790382856, i64 651345242494996224} } diff --git a/llvm/test/CodeGen/MSP430/struct_layout.ll b/llvm/test/CodeGen/MSP430/struct_layout.ll index 4c5a131acca..60ae9f09b4e 100644 --- a/llvm/test/CodeGen/MSP430/struct_layout.ll +++ b/llvm/test/CodeGen/MSP430/struct_layout.ll @@ -5,7 +5,7 @@ target triple = "msp430" %struct.X = type { i8 } ; CHECK-LABEL: @foo -; CHECK: sub #4, r1 +; CHECK: sub.w #4, r1 ; CHECK: mov.b #1, 3(r1) define void @foo() { %1 = alloca %struct.X @@ -21,7 +21,7 @@ define void @foo() { } ; CHECK-LABEL: @bar -; CHECK: sub #4, r1 +; CHECK: sub.w #4, r1 ; CHECK: mov.b #1, 3(r1) define void @bar() { %1 = alloca [3 x %struct.X] @@ -40,8 +40,8 @@ define void @bar() { %struct.Y = type { i8, i16 } ; CHECK-LABEL: @baz -; CHECK: sub #8, r1 -; CHECK: mov #2, 6(r1) +; CHECK: sub.w #8, r1 +; CHECK: mov.w #2, 6(r1) define void @baz() { %1 = alloca %struct.Y, align 2 %2 = alloca %struct.Y, align 2 diff --git a/llvm/test/CodeGen/MSP430/transient-stack-alignment.ll b/llvm/test/CodeGen/MSP430/transient-stack-alignment.ll index a2ddf8a0b08..cca83509cf4 100644 --- a/llvm/test/CodeGen/MSP430/transient-stack-alignment.ll +++ b/llvm/test/CodeGen/MSP430/transient-stack-alignment.ll @@ -5,11 +5,11 @@ target triple = "msp430---elf" define void @test() #0 { ; CHECK-LABEL: test: -; CHECK: sub #2, r1 +; CHECK: sub.w #2, r1 %1 = alloca i8, align 1 -; CHECK-NEXT: clr.b 1(r1) +; CHECK-NEXT: mov.b #0, 1(r1) store i8 0, i8* %1, align 1 -; CHECK-NEXT: add #2, r1 +; CHECK-NEXT: add.w #2, r1 ; CHECK-NEXT: ret ret void } diff --git a/llvm/test/CodeGen/MSP430/vararg.ll b/llvm/test/CodeGen/MSP430/vararg.ll index edb61d2221e..3501861f575 100644 --- a/llvm/test/CodeGen/MSP430/vararg.ll +++ b/llvm/test/CodeGen/MSP430/vararg.ll @@ -10,12 +10,12 @@ declare void @llvm.va_copy(i8*, i8*) nounwind define void @va_start(i16 %a, ...) nounwind { entry: ; CHECK-LABEL: va_start: -; CHECK: sub #2, r1 +; CHECK: sub.w #2, r1 %vl = alloca i8*, align 2 %vl1 = bitcast i8** %vl to i8* -; CHECK-NEXT: mov r1, [[REG:r[0-9]+]] -; CHECK-NEXT: add #6, [[REG]] -; CHECK-NEXT: mov [[REG]], 0(r1) +; CHECK-NEXT: mov.w r1, [[REG:r[0-9]+]] +; CHECK-NEXT: add.w #6, [[REG]] +; CHECK-NEXT: mov.w [[REG]], 0(r1) call void @llvm.va_start(i8* %vl1) call void @llvm.va_end(i8* %vl1) ret void @@ -26,11 +26,11 @@ entry: ; CHECK-LABEL: va_arg: %vl.addr = alloca i8*, align 2 store i8* %vl, i8** %vl.addr, align 2 -; CHECK: mov r12, [[REG:r[0-9]+]] -; CHECK-NEXT: incd [[REG]] -; CHECK-NEXT: mov [[REG]], 0(r1) +; CHECK: mov.w r12, [[REG:r[0-9]+]] +; CHECK-NEXT: add.w #2, [[REG]] +; CHECK-NEXT: mov.w [[REG]], 0(r1) %0 = va_arg i8** %vl.addr, i16 -; CHECK-NEXT: mov 0(r12), r12 +; CHECK-NEXT: mov.w 0(r12), r12 ret i16 %0 } @@ -39,11 +39,11 @@ entry: ; CHECK-LABEL: va_copy: %vl.addr = alloca i8*, align 2 %vl2 = alloca i8*, align 2 -; CHECK-DAG: mov r12, 2(r1) +; CHECK-DAG: mov.w r12, 2(r1) store i8* %vl, i8** %vl.addr, align 2 %0 = bitcast i8** %vl2 to i8* %1 = bitcast i8** %vl.addr to i8* -; CHECK-DAG: mov r12, 0(r1) +; CHECK-DAG: mov.w r12, 0(r1) call void @llvm.va_copy(i8* %0, i8* %1) ret void } diff --git a/llvm/test/MC/Disassembler/MSP430/lit.local.cfg b/llvm/test/MC/Disassembler/MSP430/lit.local.cfg deleted file mode 100644 index b1cf1fbd21d..00000000000 --- a/llvm/test/MC/Disassembler/MSP430/lit.local.cfg +++ /dev/null @@ -1,3 +0,0 @@ -if not 'MSP430' in config.root.targets: - config.unsupported = True - diff --git a/llvm/test/MC/Disassembler/MSP430/msp430.txt b/llvm/test/MC/Disassembler/MSP430/msp430.txt deleted file mode 100644 index c7d6ff576da..00000000000 --- a/llvm/test/MC/Disassembler/MSP430/msp430.txt +++ /dev/null @@ -1,27 +0,0 @@ -# RUN: llvm-mc -disassemble %s -triple=msp430 | FileCheck %s -0x0f 0x47 # CHECK: mov r7, r15 -0x2f 0x48 # CHECK: mov @r8, r15 -0x3f 0x48 # CHECK: mov @r8+, r15 -0x0f 0x43 # CHECK: clr r15 -0x08 0x57 # CHECK: add r7, r8 -0x28 0x57 # CHECK: add @r7, r8 -0x38 0x57 # CHECK: add @r7+, r8 -0x87 0x12 # CHECK: call r7 -0x00 0x47 # CHECK: br r7 -0x39 0xb2 # CHECK: bit #8, r9 - -0xfe 0x3f # CHECK: jmp $-2 -0xfe 0x23 # CHECK: jne $-2 - -0x3f 0x40 0x2a 0x00 # CHECK: mov #42, r15 -0x1f 0x48 0x2a 0x00 # CHECK: mov 42(r8), r15 -0x1f 0x42 0x2a 0x00 # CHECK: mov &42, r15 -0x1f 0x40 0x2a 0x00 # CHECK: mov 42, r15 -0xb0 0x12 0x81 0x01 # CHECK: call #385 -0x97 0x12 0x06 0x00 # CHECK: call 6(r7) -0xa7 0xb2 0x02 0x00 # CHECK: bit #34, 2(r7) -0xa9 0x57 0x08 0x00 # CHECK: add @r7, 8(r9) -0xb7 0xe7 0xfe 0xff # CHECK: xor @r7+, -2(r7) - -0xbf 0x40 0x2a 0x00 0x0c 0x00 # CHECK: mov #42, 12(r15) -0x9a 0xb9 0x10 0x00 0x08 0x00 # CHECK: bit 16(r9), 8(r10) diff --git a/llvm/test/MC/MSP430/addrmode.s b/llvm/test/MC/MSP430/addrmode.s deleted file mode 100644 index 46051c00fed..00000000000 --- a/llvm/test/MC/MSP430/addrmode.s +++ /dev/null @@ -1,110 +0,0 @@ -; RUN: llvm-mc -triple msp430 -show-encoding < %s | FileCheck %s - -foo: - mov r8, r15 - mov disp+2(r8), r15 - mov disp+2, r15 - mov &disp+2, r15 - mov @r8, r15 - mov @r8+, r15 - mov #disp+2, r15 - -; CHECK: mov r8, r15 ; encoding: [0x0f,0x48] -; CHECK: mov disp+2(r8), r15 ; encoding: [0x1f,0x48,A,A] -; CHECK: mov disp+2, r15 ; encoding: [0x1f,0x40,A,A] -; CHECK: mov &disp+2, r15 ; encoding: [0x1f,0x42,A,A] -; CHECK: mov @r8, r15 ; encoding: [0x2f,0x48] -; CHECK: mov @r8+, r15 ; encoding: [0x3f,0x48] -; CHECK: mov #disp+2, r15 ; encoding: [0x3f,0x40,A,A] - - mov #42, r15 - mov #42, 12(r15) - mov #42, &disp - mov disp, disp+2 - -; CHECK: mov #42, r15 ; encoding: [0x3f,0x40,0x2a,0x00] -; CHECK: mov #42, 12(r15) ; encoding: [0xbf,0x40,0x2a,0x00,0x0c,0x00] -; CHECK: mov #42, &disp ; encoding: [0xb2,0x40,0x2a,0x00,A,A] -; CHECK: mov disp, disp+2 ; encoding: [0x90,0x40,A,A,B,B] - - add r7, r8 - add 6(r7), r8 - add &disp, r8 - add disp, r8 - add @r9, r8 - add @r9+, r8 - add #42, r8 - -; CHECK: add r7, r8 ; encoding: [0x08,0x57] -; CHECK: add 6(r7), r8 ; encoding: [0x18,0x57,0x06,0x00] -; CHECK: add &disp, r8 ; encoding: [0x18,0x52,A,A] -; CHECK: add disp, r8 ; encoding: [0x18,0x50,A,A] -; CHECK: add @r9, r8 ; encoding: [0x28,0x59] -; CHECK: add @r9+, r8 ; encoding: [0x38,0x59] -; CHECK: add #42, r8 ; encoding: [0x38,0x50,0x2a,0x00] - - add r7, 6(r5) - add 6(r7), 6(r5) - add &disp, 6(r5) - add disp, 6(r5) - add @r9, 6(r5) - add @r9+, 6(r5) - add #42, 6(r5) - -; CHECK: add r7, 6(r5) ; encoding: [0x85,0x57,0x06,0x00] -; CHECK: add 6(r7), 6(r5) ; encoding: [0x95,0x57,0x06,0x00,0x06,0x00] -; CHECK: add &disp, 6(r5) ; encoding: [0x95,0x52,A,A,0x06,0x00] -; CHECK: add disp, 6(r5) ; encoding: [0x95,0x50,A,A,0x06,0x00] -; CHECK: add @r9, 6(r5) ; encoding: [0xa5,0x59,0x06,0x00] -; CHECK: add @r9+, 6(r5) ; encoding: [0xb5,0x59,0x06,0x00] -; CHECK: add #42, 6(r5) ; encoding: [0xb5,0x50,0x2a,0x00,0x06,0x00] - - add r7, &disp - add 6(r7), &disp - add &disp, &disp - add disp, &disp - add @r9, &disp - add @r9+, &disp - add #42, &disp - -; CHECK: add r7, &disp ; encoding: [0x82,0x57,A,A] -; CHECK: add 6(r7), &disp ; encoding: [0x92,0x57,0x06,0x00,A,A] -; CHECK: add &disp, &disp ; encoding: [0x92,0x52,A,A,B,B] -; CHECK: add disp, &disp ; encoding: [0x92,0x50,A,A,B,B] -; CHECK: add @r9, &disp ; encoding: [0xa2,0x59,A,A] -; CHECK: add @r9+, &disp ; encoding: [0xb2,0x59,A,A] -; CHECK: add #42, &disp ; encoding: [0xb2,0x50,0x2a,0x00,A,A] - - add r7, disp - add 6(r7), disp - add &disp, disp - add disp, disp - add @r9, disp - add @r9+, disp - add #42, disp - -; CHECK: add r7, disp ; encoding: [0x80,0x57,A,A] -; CHECK: add 6(r7), disp ; encoding: [0x90,0x57,0x06,0x00,A,A] -; CHECK: add &disp, disp ; encoding: [0x90,0x52,A,A,B,B] -; CHECK: add disp, disp ; encoding: [0x90,0x50,A,A,B,B] -; CHECK: add @r9, disp ; encoding: [0xa0,0x59,A,A] -; CHECK: add @r9+, disp ; encoding: [0xb0,0x59,A,A] -; CHECK: add #42, disp ; encoding: [0xb0,0x50,0x2a,0x00,A,A] - - call r7 - call 6(r7) - call disp+6(r7) - call &disp - call disp - call #disp - -; CHECK: call r7 ; encoding: [0x87,0x12] -; CHECK: call 6(r7) ; encoding: [0x97,0x12,0x06,0x00] -; CHECK: call disp+6(r7) ; encoding: [0x97,0x12,A,A] -; CHECK: call &disp ; encoding: [0x92,0x12,A,A] -; CHECK: call disp ; encoding: [0x90,0x12,A,A] -; CHECK: call #disp ; encoding: [0xb0,0x12,A,A] - -disp: - .word 0xcafe - .word 0xbabe diff --git a/llvm/test/MC/MSP430/altreg.s b/llvm/test/MC/MSP430/altreg.s deleted file mode 100644 index fe1e3a43772..00000000000 --- a/llvm/test/MC/MSP430/altreg.s +++ /dev/null @@ -1,7 +0,0 @@ -; RUN: llvm-mc -triple msp430 -show-encoding < %s | FileCheck %s - mov pc, r0 ; CHECK: mov r0, r0 - mov sp, r1 ; CHECK: mov r1, r1 - mov sr, r2 ; CHECK: mov r2, r2 - mov cg, r3 ; CHECK: mov r3, r3 - mov fp, r4 ; CHECK: mov r4, r4 - bic #8, SR ; CHECK: dint diff --git a/llvm/test/MC/MSP430/const.s b/llvm/test/MC/MSP430/const.s deleted file mode 100644 index f5cca109a50..00000000000 --- a/llvm/test/MC/MSP430/const.s +++ /dev/null @@ -1,10 +0,0 @@ -; RUN: llvm-mc -triple msp430 -show-encoding < %s | FileCheck %s - mov #4, r15 ; CHECK: mov #4, r15 ; encoding: [0x2f,0x42] - mov #8, r15 ; CHECK: mov #8, r15 ; encoding: [0x3f,0x42] - mov #0, r15 ; CHECK: clr r15 ; encoding: [0x0f,0x43] - mov #1, r15 ; CHECK: mov #1, r15 ; encoding: [0x1f,0x43] - mov #2, r15 ; CHECK: mov #2, r15 ; encoding: [0x2f,0x43] - mov #-1, r7 ; CHECK: mov #-1, r7 ; encoding: [0x37,0x43] - - push #8 ; CHECK: push #8 ; encoding: [0x32,0x12] - push #42 ; CHECK: push #42 ; encoding: [0x30,0x12,0x2a,0x00] diff --git a/llvm/test/MC/MSP430/invalid.s b/llvm/test/MC/MSP430/invalid.s deleted file mode 100644 index 2815b520dd5..00000000000 --- a/llvm/test/MC/MSP430/invalid.s +++ /dev/null @@ -1,19 +0,0 @@ -; RUN: not llvm-mc -triple msp430 < %s 2>&1 | FileCheck %s -foo: - ;; invalid operand count - mov r7 ; CHECK: :[[@LINE]]:3: error: too few operands for instruction - - ;; invalid destination addressing modes - mov r7, @r15 ; CHECK: :[[@LINE]]:14: error: invalid operand for instruction - mov r7, @r15+ ; CHECK: :[[@LINE]]:14: error: invalid operand for instruction - mov r7, #0 ; CHECK: :[[@LINE]]:14: error: invalid operand for instruction - mov r7, #123 ; CHECK: :[[@LINE]]:14: error: invalid operand for instruction - - ;; invalid byte instructions - swpb.b r7 ; CHECK: :[[@LINE]]:3: error: invalid instruction mnemonic - sxt.b r7 ; CHECK: :[[@LINE]]:3: error: invalid instruction mnemonic - call.b r7 ; CHECK: :[[@LINE]]:3: error: invalid instruction mnemonic - - ;; invalid conditional jump offsets - jmp -513 ; CHECK: :[[@LINE]]:10: error: invalid jump offset - jmp 512 ; CHECK: :[[@LINE]]:10: error: invalid jump offset diff --git a/llvm/test/MC/MSP430/lit.local.cfg b/llvm/test/MC/MSP430/lit.local.cfg deleted file mode 100644 index b1cf1fbd21d..00000000000 --- a/llvm/test/MC/MSP430/lit.local.cfg +++ /dev/null @@ -1,3 +0,0 @@ -if not 'MSP430' in config.root.targets: - config.unsupported = True - diff --git a/llvm/test/MC/MSP430/opcode.s b/llvm/test/MC/MSP430/opcode.s deleted file mode 100644 index 14655fe091f..00000000000 --- a/llvm/test/MC/MSP430/opcode.s +++ /dev/null @@ -1,163 +0,0 @@ -; RUN: llvm-mc -triple msp430 -show-encoding %s \ -; RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s - -; RUN: llvm-mc -triple msp430 -filetype=obj %s \ -; RUN: | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INST %s - - ;; IForm8 instructions - mov.b r7, r8 ; CHECK-INST: mov.b r7, r8 - ; CHECK: encoding: [0x48,0x47] - add.b r7, r8 ; CHECK-INST: add.b r7, r8 - ; CHECK: encoding: [0x48,0x57] - addc.b r7, r8 ; CHECK-INST: addc.b r7, r8 - ; CHECK: encoding: [0x48,0x67] - subc.b r7, r8 ; CHECK-INST: subc.b r7, r8 - ; CHECK: encoding: [0x48,0x77] - sub.b r7, r8 ; CHECK-INST: sub.b r7, r8 - ; CHECK: encoding: [0x48,0x87] - cmp.b r7, r8 ; CHECK-INST: cmp.b r7, r8 - ; CHECK: encoding: [0x48,0x97] - dadd.b r7, r8 ; CHECK-INST: dadd.b r7, r8 - ; CHECK: encoding: [0x48,0xa7] - bit.b r7, r8 ; CHECK-INST: bit.b r7, r8 - ; CHECK: encoding: [0x48,0xb7] - bic.b r7, r8 ; CHECK-INST: bic.b r7, r8 - ; CHECK: encoding: [0x48,0xc7] - bis.b r7, r8 ; CHECK-INST: bis.b r7, r8 - ; CHECK: encoding: [0x48,0xd7] - xor.b r7, r8 ; CHECK-INST: xor.b r7, r8 - ; CHECK: encoding: [0x48,0xe7] - and.b r7, r8 ; CHECK-INST: and.b r7, r8 - ; CHECK: encoding: [0x48,0xf7] - - ;; IForm16 instructions - mov r7, r8 ; CHECK-INST: mov r7, r8 - ; CHECK: encoding: [0x08,0x47] - add r7, r8 ; CHECK-INST: add r7, r8 - ; CHECK: encoding: [0x08,0x57] - addc r7, r8 ; CHECK-INST: addc r7, r8 - ; CHECK: encoding: [0x08,0x67] - subc r7, r8 ; CHECK-INST: subc r7, r8 - ; CHECK: encoding: [0x08,0x77] - sub r7, r8 ; CHECK-INST: sub r7, r8 - ; CHECK: encoding: [0x08,0x87] - cmp r7, r8 ; CHECK-INST: cmp r7, r8 - ; CHECK: encoding: [0x08,0x97] - dadd r7, r8 ; CHECK-INST: dadd r7, r8 - ; CHECK: encoding: [0x08,0xa7] - bit r7, r8 ; CHECK-INST: bit r7, r8 - ; CHECK: encoding: [0x08,0xb7] - bic r7, r8 ; CHECK-INST: bic r7, r8 - ; CHECK: encoding: [0x08,0xc7] - bis r7, r8 ; CHECK-INST: bis r7, r8 - ; CHECK: encoding: [0x08,0xd7] - xor r7, r8 ; CHECK-INST: xor r7, r8 - ; CHECK: encoding: [0x08,0xe7] - and r7, r8 ; CHECK-INST: and r7, r8 - ; CHECK: encoding: [0x08,0xf7] - - ;; IIForm8 instructions - rrc.b r7 ; CHECK-INST: rrc.b r7 - ; CHECK: encoding: [0x47,0x10] - rra.b r7 ; CHECK-INST: rra.b r7 - ; CHECK: encoding: [0x47,0x11] - push.b r7 ; CHECK-INST: push.b r7 - ; CHECK: encoding: [0x47,0x12] - - ;; IIForm16 instructions - rrc r7 ; CHECK-INST: rrc r7 - ; CHECK: encoding: [0x07,0x10] - swpb r7 ; CHECK-INST: swpb r7 - ; CHECK: encoding: [0x87,0x10] - rra r7 ; CHECK-INST: rra r7 - ; CHECK: encoding: [0x07,0x11] - sxt r7 ; CHECK-INST: sxt r7 - ; CHECK: encoding: [0x87,0x11] - push r7 ; CHECK-INST: push r7 - ; CHECK: encoding: [0x07,0x12] - call r7 ; CHECK-INST: call r7 - ; CHECK: encoding: [0x87,0x12] - reti ; CHECK-INST: reti - ; CHECK: encoding: [0x00,0x13] - - ;; CJForm instructions - jnz -2 ; CHECK-INST: jne $-2 - ; CHECK: encoding: [0xfe,0x23] - jne -2 ; CHECK-INST: jne $-2 - ; CHECK: encoding: [0xfe,0x23] - jeq -2 ; CHECK-INST: jeq $-2 - ; CHECK: encoding: [0xfe,0x27] - jz -2 ; CHECK-INST: jeq $-2 - ; CHECK: encoding: [0xfe,0x27] - jnc -2 ; CHECK-INST: jlo $-2 - ; CHECK: encoding: [0xfe,0x2b] - jlo -2 ; CHECK-INST: jlo $-2 - ; CHECK: encoding: [0xfe,0x2b] - jc -2 ; CHECK-INST: jhs $-2 - ; CHECK: encoding: [0xfe,0x2f] - jhs -2 ; CHECK-INST: jhs $-2 - ; CHECK: encoding: [0xfe,0x2f] - jn -2 ; CHECK-INST: jn $-2 - ; CHECK: encoding: [0xfe,0x33] - jge -2 ; CHECK-INST: jge $-2 - ; CHECK: encoding: [0xfe,0x37] - jl -2 ; CHECK-INST: jl $-2 - ; CHECK: encoding: [0xfe,0x3b] - jmp $-2 ; CHECK-INST: jmp $-2 - ; CHECK: encoding: [0xfe,0x3f] - - ;; Emulated arithmetic instructions - adc r7 ; CHECK-INST: adc r7 - ; CHECK: encoding: [0x07,0x63] - dadc r7 ; CHECK-INST: dadc r7 - ; CHECK: encoding: [0x07,0xa3] - dec r7 ; CHECK-INST: dec r7 - ; CHECK: encoding: [0x17,0x83] - decd r7 ; CHECK-INST: decd r7 - ; CHECK: encoding: [0x27,0x83] - inc r7 ; CHECK-INST: inc r7 - ; CHECK: encoding: [0x17,0x53] - incd r7 ; CHECK-INST: incd r7 - ; CHECK: encoding: [0x27,0x53] - sbc r7 ; CHECK-INST: sbc r7 - ; CHECK: encoding: [0x07,0x73] - - ;; Emulated logical instructions - inv r7 ; CHECK-INST: inv r7 - ; CHECK: encoding: [0x37,0xe3] - rla r7 ; CHECK-INST: add r7, r7 - ; CHECK: encoding: [0x07,0x57] - rlc r7 ; CHECK-INST: addc r7, r7 - ; CHECK: encoding: [0x07,0x67] - - ;; Emulated program flow control instructions - br r7 ; CHECK-INST: br r7 - ; CHECK: encoding: [0x00,0x47] - dint ; CHECK-INST: dint - ; CHECK: encoding: [0x32,0xc2] - eint ; CHECK-INST: eint - ; CHECK: encoding: [0x32,0xd2] - nop ; CHECK-INST: nop - ; CHECK: encoding: [0x03,0x43] - ret ; CHECK-INST: ret - ; CHECK: encoding: [0x30,0x41] - - ;; Emulated data instruction - clr r7 ; CHECK-INST: clr r7 - ; CHECK: encoding: [0x07,0x43] - clrc ; CHECK-INST: clrc - ; CHECK: encoding: [0x12,0xc3] - clrn ; CHECK-INST: clrn - ; CHECK: encoding: [0x22,0xc2] - clrz ; CHECK-INST: clrz - ; CHECK: encoding: [0x22,0xc3] - pop r7 ; CHECK-INST: pop r7 - ; CHECK: encoding: [0x37,0x41] - setc ; CHECK-INST: setc - ; CHECK: encoding: [0x12,0xd3] - setn ; CHECK-INST: setn - ; CHECK: encoding: [0x22,0xd2] - setz ; CHECK-INST: setz - ; CHECK: encoding: [0x22,0xd3] - tst r7 ; CHECK-INST: tst r7 - ; CHECK: encoding: [0x07,0x93] diff --git a/llvm/test/MC/MSP430/reloc.s b/llvm/test/MC/MSP430/reloc.s deleted file mode 100644 index 42dd64a43c5..00000000000 --- a/llvm/test/MC/MSP430/reloc.s +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: llvm-mc -triple msp430 -show-encoding < %s | FileCheck %s - - mov disp+2(r8), r15 -; CHECK: mov disp+2(r8), r15 ; encoding: [0x1f,0x48,A,A] -; CHECK: ; fixup A - offset: 2, value: disp+2, kind: fixup_16_byte - - mov disp+2, r15 -; CHECK: mov disp+2, r15 ; encoding: [0x1f,0x40,A,A] -; CHECK: ; fixup A - offset: 2, value: disp+2, kind: fixup_16_pcrel_byte - - mov &disp+2, r15 -; CHECK: mov &disp+2, r15 ; encoding: [0x1f,0x42,A,A] -; CHECK: ; fixup A - offset: 2, value: disp+2, kind: fixup_16 - - mov disp, disp+2 -; CHECK: mov disp, disp+2 ; encoding: [0x90,0x40,A,A,B,B] -; CHECK: ; fixup A - offset: 2, value: disp, kind: fixup_16_pcrel_byte -; CHECK: ; fixup B - offset: 4, value: disp+2, kind: fixup_16_pcrel_byte - - jmp foo -; CHECK: jmp foo ; encoding: [A,0b001111AA] -; CHECK: ; fixup A - offset: 0, value: foo, kind: fixup_10_pcrel |
