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-rw-r--r--llvm/test/MC/ARM/basic-arm-instructions.s158
-rw-r--r--llvm/test/MC/ARM/diagnostics.s80
-rw-r--r--llvm/test/MC/ARM/thumb-diagnostics.s2
-rw-r--r--llvm/test/MC/Disassembler/ARM/arm-tests.txt2
-rw-r--r--llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt110
5 files changed, 345 insertions, 7 deletions
diff --git a/llvm/test/MC/ARM/basic-arm-instructions.s b/llvm/test/MC/ARM/basic-arm-instructions.s
index df5ecbb131c..06d92a2199c 100644
--- a/llvm/test/MC/ARM/basic-arm-instructions.s
+++ b/llvm/test/MC/ARM/basic-arm-instructions.s
@@ -16,6 +16,9 @@ _func:
@ ADC (immediate)
@------------------------------------------------------------------------------
adc r1, r2, #0xf
+ adc r7, r8, #42, #2
+ adc r7, r8, #-2147483638
+ adc r7, r8, #40, #2
adc r1, r2, #0xf0
adc r1, r2, #0xf00
adc r1, r2, #0xf000
@@ -25,20 +28,24 @@ _func:
adc r1, r2, #0xf0000000
adc r1, r2, #0xf000000f
adcs r1, r2, #0xf00
+ adcs r7, r8, #40, #2
adcseq r1, r2, #0xf00
adceq r1, r2, #0xf00
@ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2]
+@ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2]
+@ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2]
+@ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2]
@ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2]
@ CHECK: adc r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0xe2]
@ CHECK: adc r1, r2, #61440 @ encoding: [0x0f,0x1a,0xa2,0xe2]
@ CHECK: adc r1, r2, #983040 @ encoding: [0x0f,0x18,0xa2,0xe2]
@ CHECK: adc r1, r2, #15728640 @ encoding: [0x0f,0x16,0xa2,0xe2]
@ CHECK: adc r1, r2, #251658240 @ encoding: [0x0f,0x14,0xa2,0xe2]
-@ CHECK: adc r1, r2, #4026531840 @ encoding: [0x0f,0x12,0xa2,0xe2]
-@ CHECK: adc r1, r2, #4026531855 @ encoding: [0xff,0x12,0xa2,0xe2]
-
+@ CHECK: adc r1, r2, #-268435456 @ encoding: [0x0f,0x12,0xa2,0xe2]
+@ CHECK: adc r1, r2, #-268435441 @ encoding: [0xff,0x12,0xa2,0xe2]
@ CHECK: adcs r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0xe2]
+@ CHECK: adcs r7, r8, #40, #2 @ encoding: [0x28,0x71,0xb8,0xe2]
@ CHECK: adcseq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0x02]
@ CHECK: adceq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0x02]
@@ -162,6 +169,9 @@ Lforward:
@ ADD
@------------------------------------------------------------------------------
add r4, r5, #0xf000
+ add r7, r8, #42, #2
+ add r7, r8, #-2147483638
+ add r7, r8, #40, #2
add r4, r5, r6
add r4, r5, r6, lsl #5
add r4, r5, r6, lsr #5
@@ -196,6 +206,9 @@ Lforward:
add r0, pc, #(Lback - .)
@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2]
+@ CHECK: add r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe2]
+@ CHECK: add r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe2]
+@ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2]
@ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0]
@ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0]
@ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0]
@@ -237,9 +250,23 @@ Lforward:
@ CHECK: add r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x81,0xe0]
@------------------------------------------------------------------------------
+@ ADDS
+@------------------------------------------------------------------------------
+ adds r7, r8, #42, #2
+ adds r7, r8, #-2147483638
+ adds r7, r8, #40, #2
+
+@ CHECK: adds r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x98,0xe2]
+@ CHECK: adds r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x98,0xe2]
+@ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2]
+
+@------------------------------------------------------------------------------
@ AND
@------------------------------------------------------------------------------
and r10, r1, #0xf
+ and r7, r8, #42, #2
+ and r7, r8, #-2147483638
+ and r7, r8, #40, #2
and r10, r1, r6
and r10, r1, r6, lsl #10
and r10, r1, r6, lsr #10
@@ -268,6 +295,9 @@ Lforward:
and r10, r1, rrx
@ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2]
+@ CHECK: and r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x08,0xe2]
+@ CHECK: and r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x08,0xe2]
+@ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2]
@ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0]
@ CHECK: and r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0x01,0xe0]
@ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0]
@@ -354,6 +384,9 @@ Lforward:
@ BIC
@------------------------------------------------------------------------------
bic r10, r1, #0xf
+ bic r7, r8, #42, #2
+ bic r7, r8, #-2147483638
+ bic r7, r8, #40, #2
bic r10, r1, r6
bic r10, r1, r6, lsl #10
bic r10, r1, r6, lsr #10
@@ -368,6 +401,9 @@ Lforward:
@ destination register is optional
bic r1, #0xf
+ bic r7, #42, #2
+ bic r7, #-2147483638
+ bic r7, #40, #2
bic r10, r1
bic r10, r1, lsl #10
bic r10, r1, lsr #10
@@ -381,6 +417,9 @@ Lforward:
bic r10, r1, rrx
@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3]
+@ CHECK: bic r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe3]
+@ CHECK: bic r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe3]
+@ CHECK: bic r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe3]
@ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1]
@ CHECK: bic r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0xc1,0xe1]
@ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1]
@@ -395,6 +434,9 @@ Lforward:
@ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3]
+@ CHECK: bic r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe3]
+@ CHECK: bic r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe3]
+@ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3]
@ CHECK: bic r10, r10, r1 @ encoding: [0x01,0xa0,0xca,0xe1]
@ CHECK: bic r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0xca,0xe1]
@ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1]
@@ -511,6 +553,9 @@ Lforward:
@ CMN
@------------------------------------------------------------------------------
cmn r1, #0xf
+ cmn r7, #42, #2
+ cmn r7, #-2147483638
+ cmn r7, #40, #2
cmn r1, r6
cmn r1, r6, lsl #10
cmn r1, r6, lsr #10
@@ -524,6 +569,9 @@ Lforward:
cmn r1, r6, rrx
@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3]
+@ CHECK: cmn r7, #-2147483638 @ encoding: [0x2a,0x01,0x77,0xe3]
+@ CHECK: cmn r7, #-2147483638 @ encoding: [0x2a,0x01,0x77,0xe3]
+@ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3]
@ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1]
@ CHECK: cmn r1, r6, lsl #10 @ encoding: [0x06,0x05,0x71,0xe1]
@ CHECK: cmn r1, r6, lsr #10 @ encoding: [0x26,0x05,0x71,0xe1]
@@ -540,6 +588,9 @@ Lforward:
@ CMP
@------------------------------------------------------------------------------
cmp r1, #0xf
+ cmp r7, #42, #2
+ cmp r7, #-2147483638
+ cmp r7, #40, #2
cmp r1, r6
cmp r1, r6, lsl #10
cmp r1, r6, lsr #10
@@ -555,6 +606,9 @@ Lforward:
cmp lr, #0
@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3]
+@ CHECK: cmp r7, #-2147483638 @ encoding: [0x2a,0x01,0x57,0xe3]
+@ CHECK: cmp r7, #-2147483638 @ encoding: [0x2a,0x01,0x57,0xe3]
+@ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3]
@ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1]
@ CHECK: cmp r1, r6, lsl #10 @ encoding: [0x06,0x05,0x51,0xe1]
@ CHECK: cmp r1, r6, lsr #10 @ encoding: [0x26,0x05,0x51,0xe1]
@@ -740,6 +794,9 @@ Lforward:
@ EOR
@------------------------------------------------------------------------------
eor r4, r5, #0xf000
+ eor r7, r8, #42, #2
+ eor r7, r8, #-2147483638
+ eor r7, r8, #40, #2
eor r4, r5, r6
eor r4, r5, r6, lsl #5
eor r4, r5, r6, lsr #5
@@ -767,6 +824,9 @@ Lforward:
eor r4, r5, rrx
@ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2]
+@ CHECK: eor r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x28,0xe2]
+@ CHECK: eor r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x28,0xe2]
+@ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2]
@ CHECK: eor r4, r5, r6 @ encoding: [0x06,0x40,0x25,0xe0]
@ CHECK: eor r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x25,0xe0]
@ CHECK: eor r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x25,0xe0]
@@ -1036,6 +1096,14 @@ Lforward:
mov r3, #7
mov r4, #0xff0
mov r5, #0xff0000
+ mov r7, #0, #2
+ mov r7, #42, #0
+ mov r7, #40, #2
+ mov r7, #42, #10
+ mov r7, #42, #30
+ mov r7, #42, #2
+ mov r7, #-2147483638
+ mov pc, #42, #2
mov r6, #0xffff
movw r9, #0xffff
movs r3, #7
@@ -1045,6 +1113,14 @@ Lforward:
@ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3]
@ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3]
@ CHECK: mov r5, #16711680 @ encoding: [0xff,0x58,0xa0,0xe3]
+@ CHECK: mov r7, #0, #2 @ encoding: [0x00,0x71,0xa0,0xe3]
+@ CHECK: mov r7, #42 @ encoding: [0x2a,0x70,0xa0,0xe3]
+@ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3]
+@ CHECK: mov r7, #176160768 @ encoding: [0x2a,0x75,0xa0,0xe3]
+@ CHECK: mov r7, #42, #30 @ encoding: [0x2a,0x7f,0xa0,0xe3]
+@ CHECK: mov r7, #-2147483638 @ encoding: [0x2a,0x71,0xa0,0xe3]
+@ CHECK: mov r7, #-2147483638 @ encoding: [0x2a,0x71,0xa0,0xe3]
+@ CHECK: mov pc, #2147483658 @ encoding: [0x2a,0xf1,0xa0,0xe3]
@ CHECK: movw r6, #65535 @ encoding: [0xff,0x6f,0x0f,0xe3]
@ CHECK: movw r9, #65535 @ encoding: [0xff,0x9f,0x0f,0xe3]
@ CHECK: movs r3, #7 @ encoding: [0x07,0x30,0xb0,0xe3]
@@ -1151,6 +1227,9 @@ Lforward:
msr spsr_fc, #5
msr SPSR_fsxc, #5
msr cpsr_fsxc, #5
+ msr APSR_nzcvq, #42, #2
+ msr apsr_nzcvqg, #2147483658
+ msr SPSR_fsxc, #40, #2
@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
@ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3]
@@ -1166,6 +1245,9 @@ Lforward:
@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3]
@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3]
@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3]
+@ CHECK: msr APSR_nzcvq, #2147483658 @ encoding: [0x2a,0xf1,0x28,0xe3]
+@ CHECK: msr APSR_nzcvqg, #2147483658 @ encoding: [0x2a,0xf1,0x2c,0xe3]
+@ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
msr apsr, r0
msr apsr_g, r0
@@ -1218,6 +1300,9 @@ Lforward:
mvn r3, #7
mvn r4, #0xff0
mvn r5, #0xff0000
+ mvn r7, #42, #2
+ mvn r7, #-2147483638
+ mvn r7, #40, #2
mvns r3, #7
mvneq r4, #0xff0
mvnseq r5, #0xff0000
@@ -1225,6 +1310,9 @@ Lforward:
@ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3]
@ CHECK: mvn r4, #4080 @ encoding: [0xff,0x4e,0xe0,0xe3]
@ CHECK: mvn r5, #16711680 @ encoding: [0xff,0x58,0xe0,0xe3]
+@ CHECK: mvn r7, #-2147483638 @ encoding: [0x2a,0x71,0xe0,0xe3]
+@ CHECK: mvn r7, #-2147483638 @ encoding: [0x2a,0x71,0xe0,0xe3]
+@ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3]
@ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3]
@ CHECK: mvneq r4, #4080 @ encoding: [0xff,0x4e,0xe0,0x03]
@ CHECK: mvnseq r5, #16711680 @ encoding: [0xff,0x58,0xf0,0x03]
@@ -1291,6 +1379,9 @@ Lforward:
@ ORR
@------------------------------------------------------------------------------
orr r4, r5, #0xf000
+ orr r7, r8, #42, #2
+ orr r7, r8, #-2147483638
+ orr r7, r8, #40, #2
orr r4, r5, r6
orr r4, r5, r6, lsl #5
orr r4, r5, r6, lsr #5
@@ -1318,6 +1409,9 @@ Lforward:
orr r4, r5, rrx
@ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3]
+@ CHECK: orr r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe3]
+@ CHECK: orr r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe3]
+@ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3]
@ CHECK: orr r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe1]
@ CHECK: orr r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe1]
@ CHECK: orr r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe1]
@@ -1576,6 +1670,9 @@ Lforward:
@ RSB
@------------------------------------------------------------------------------
rsb r4, r5, #0xf000
+ rsb r7, r8, #42, #2
+ rsb r7, r8, #-2147483638
+ rsb r7, r8, #40, #2
rsb r4, r5, r6
rsb r4, r5, r6, lsl #5
rsblo r4, r5, r6, lsr #5
@@ -1603,6 +1700,9 @@ Lforward:
rsb r4, r5, rrx
@ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2]
+@ CHECK: rsb r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x68,0xe2]
+@ CHECK: rsb r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x68,0xe2]
+@ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2]
@ CHECK: rsb r4, r5, r6 @ encoding: [0x06,0x40,0x65,0xe0]
@ CHECK: rsb r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x65,0xe0]
@ CHECK: rsblo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x65,0x30]
@@ -1629,9 +1729,23 @@ Lforward:
@ CHECK: rsb r4, r4, r5, rrx @ encoding: [0x65,0x40,0x64,0xe0]
@------------------------------------------------------------------------------
+@ RSBS
+@------------------------------------------------------------------------------
+ rsbs r7, r8, #42, #2
+ rsbs r7, r8, #-2147483638
+ rsbs r7, r8, #40, #2
+
+@ CHECK: rsbs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x78,0xe2]
+@ CHECK: rsbs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x78,0xe2]
+@ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2]
+
+@------------------------------------------------------------------------------
@ RSC
@------------------------------------------------------------------------------
rsc r4, r5, #0xf000
+ rsc r7, r8, #42, #2
+ rsc r7, r8, #-2147483638
+ rsc r7, r8, #40, #2
rsc r4, r5, r6
rsc r4, r5, r6, lsl #5
rsclo r4, r5, r6, lsr #5
@@ -1658,6 +1772,9 @@ Lforward:
rsc r6, r7, ror r9
@ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2]
+@ CHECK: rsc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xe8,0xe2]
+@ CHECK: rsc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xe8,0xe2]
+@ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2]
@ CHECK: rsc r4, r5, r6 @ encoding: [0x06,0x40,0xe5,0xe0]
@ CHECK: rsc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xe5,0xe0]
@ CHECK: rsclo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xe5,0x30]
@@ -1734,6 +1851,9 @@ Lforward:
@ SBC
@------------------------------------------------------------------------------
sbc r4, r5, #0xf000
+ sbc r7, r8, #42, #2
+ sbc r7, r8, #-2147483638
+ sbc r7, r8, #40, #2
sbc r4, r5, r6
sbc r4, r5, r6, lsl #5
sbc r4, r5, r6, lsr #5
@@ -1759,6 +1879,9 @@ Lforward:
sbc r6, r7, ror r9
@ CHECK: sbc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xc5,0xe2]
+@ CHECK: sbc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe2]
+@ CHECK: sbc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe2]
+@ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2]
@ CHECK: sbc r4, r5, r6 @ encoding: [0x06,0x40,0xc5,0xe0]
@ CHECK: sbc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xc5,0xe0]
@ CHECK: sbc r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xc5,0xe0]
@@ -2389,6 +2512,9 @@ Lforward:
@ SUB
@------------------------------------------------------------------------------
sub r4, r5, #0xf000
+ sub r7, r8, #42, #2
+ sub r7, r8, #-2147483638
+ sub r7, r8, #40, #2
sub r4, r5, r6
sub r4, r5, r6, lsl #5
sub r4, r5, r6, lsr #5
@@ -2414,6 +2540,9 @@ Lforward:
sub r6, r7, ror r9
@ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2]
+@ CHECK: sub r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x48,0xe2]
+@ CHECK: sub r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x48,0xe2]
+@ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2]
@ CHECK: sub r4, r5, r6 @ encoding: [0x06,0x40,0x45,0xe0]
@ CHECK: sub r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x45,0xe0]
@ CHECK: sub r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x45,0xe0]
@@ -2445,6 +2574,17 @@ Lforward:
@ CHECK: sub r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x41,0xe0]
@------------------------------------------------------------------------------
+@ SUBS
+@------------------------------------------------------------------------------
+ subs r7, r8, #42, #2
+ subs r7, r8, #-2147483638
+ subs r7, r8, #40, #2
+
+@ CHECK: subs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x58,0xe2]
+@ CHECK: subs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x58,0xe2]
+@ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2]
+
+@------------------------------------------------------------------------------
@ SVC
@------------------------------------------------------------------------------
svc #16
@@ -2566,6 +2706,9 @@ Lforward:
@ TEQ
@------------------------------------------------------------------------------
teq r5, #0xf000
+ teq r7, #42, #2
+ teq r7, #-2147483638
+ teq r7, #40, #2
teq r4, r5
teq r4, r5, lsl #5
teq r4, r5, lsr #5
@@ -2578,6 +2721,9 @@ Lforward:
teq r6, r7, ror r9
@ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3]
+@ CHECK: teq r7, #-2147483638 @ encoding: [0x2a,0x01,0x37,0xe3]
+@ CHECK: teq r7, #-2147483638 @ encoding: [0x2a,0x01,0x37,0xe3]
+@ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3]
@ CHECK: teq r4, r5 @ encoding: [0x05,0x00,0x34,0xe1]
@ CHECK: teq r4, r5, lsl #5 @ encoding: [0x85,0x02,0x34,0xe1]
@ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1]
@@ -2594,6 +2740,9 @@ Lforward:
@ TST
@------------------------------------------------------------------------------
tst r5, #0xf000
+ tst r7, #42, #2
+ tst r7, #-2147483638
+ tst r7, #40, #2
tst r4, r5
tst r4, r5, lsl #5
tst r4, r5, lsr #5
@@ -2606,6 +2755,9 @@ Lforward:
tst r6, r7, ror r9
@ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3]
+@ CHECK: tst r7, #-2147483638 @ encoding: [0x2a,0x01,0x17,0xe3]
+@ CHECK: tst r7, #-2147483638 @ encoding: [0x2a,0x01,0x17,0xe3]
+@ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3]
@ CHECK: tst r4, r5 @ encoding: [0x05,0x00,0x14,0xe1]
@ CHECK: tst r4, r5, lsl #5 @ encoding: [0x85,0x02,0x14,0xe1]
@ CHECK: tst r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x14,0xe1]
diff --git a/llvm/test/MC/ARM/diagnostics.s b/llvm/test/MC/ARM/diagnostics.s
index 6b9574b7553..6f66dc3b4d0 100644
--- a/llvm/test/MC/ARM/diagnostics.s
+++ b/llvm/test/MC/ARM/diagnostics.s
@@ -621,3 +621,83 @@ foo2:
@ CHECK-ERRORS: error: destination register and base register can't be identical
@ CHECK-ERRORS: ldrsb r0, [r0], r1
@ CHECK-ERRORS: ^
+
+ @ Out of range modified immediate values
+ mov r5, #-256, #6
+ mov r6, #42, #7
+ mvn r5, #256, #6
+ mvn r6, #42, #298
+ cmp r5, #65535, #6
+ cmp r6, #42, #31
+ cmn r5, #-1, #6
+ cmn r6, #42, #32
+ msr APSR_nzcvq, #-128, #2
+ msr apsr_nzcvqg, #0, #1
+ adc r7, r8, #-256, #2
+ adc r7, r8, #128, #1
+ sbc r7, r8, #-256, #2
+ sbc r7, r8, #128, #1
+ add r7, r8, #-2149, #0
+ add r7, r8, #100, #1
+ sub r7, r8, #-2149, #0
+ sub r7, r8, #100, #1
+ and r7, r8, #-2149, #0
+ and r7, r8, #100, #1
+ orr r7, r8, #-2149, #0
+ orr r7, r8, #100, #1
+ eor r7, r8, #-2149, #0
+ eor r7, r8, #100, #1
+ bic r7, r8, #-2149, #0
+ bic r7, r8, #100, #1
+ rsb r7, r8, #-2149, #0
+ rsb r7, r8, #100, #1
+ adds r7, r8, #-2149, #0
+ adds r7, r8, #100, #1
+ subs r7, r8, #-2149, #0
+ subs r7, r8, #100, #1
+ rsbs r7, r8, #-2149, #0
+ rsbs r7, r8, #100, #1
+ rsc r7, r8, #-2149, #0
+ rsc r7, r8, #100, #1
+ TST r7, #-2149, #0
+ TST r7, #100, #1
+ TEQ r7, #-2149, #0
+ TEQ r7, #100, #1
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
+@ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
+@ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
diff --git a/llvm/test/MC/ARM/thumb-diagnostics.s b/llvm/test/MC/ARM/thumb-diagnostics.s
index 2a791324704..d2261293378 100644
--- a/llvm/test/MC/ARM/thumb-diagnostics.s
+++ b/llvm/test/MC/ARM/thumb-diagnostics.s
@@ -206,7 +206,7 @@ error: invalid operand for instruction
@ CHECK-ERRORS: error: instruction requires: thumb2
@ CHECK-ERRORS: add sp, sp, #512
@ CHECK-ERRORS: ^
-@ CHECK-ERRORS: error: instruction requires: arm-mode
+@ CHECK-ERRORS: error: instruction requires: thumb2
@ CHECK-ERRORS: add r2, sp, #1024
@ CHECK-ERRORS: ^
diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt
index e82f75a6f9f..008bb1154e5 100644
--- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt
@@ -1,6 +1,6 @@
# RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9 | FileCheck %s
-# CHECK: addpl r4, pc, #318767104
+# CHECK: addpl r4, pc, #76, #10
0x4c 0x45 0x8f 0x52
# CHECK: b #0
diff --git a/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt
index 8bcf4e6e3fa..335e69fe241 100644
--- a/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt
+++ b/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt
@@ -10,9 +10,12 @@
# CHECK: adc r1, r2, #983040
# CHECK: adc r1, r2, #15728640
# CHECK: adc r1, r2, #251658240
-# CHECK: adc r1, r2, #4026531840
-# CHECK: adc r1, r2, #4026531855
+# CHECK: adc r1, r2, #-268435456
+# CHECK: adc r1, r2, #-268435441
+# CHECK: adc r7, r8, #-2147483638
+# CHECK: adc r7, r8, #40, #2
# CHECK: adcs r1, r2, #3840
+# CHECK: adcs r7, r8, #40, #2
# CHECK: adcseq r1, r2, #3840
# CHECK: adceq r1, r2, #3840
@@ -25,8 +28,11 @@
0x0f 0x14 0xa2 0xe2
0x0f 0x12 0xa2 0xe2
0xff 0x12 0xa2 0xe2
+0x2a 0x71 0xa8 0xe2
+0x28 0x71 0xa8 0xe2
0x0f 0x1c 0xb2 0xe2
+0x28 0x71 0xb8 0xe2
0x0f 0x1c 0xb2 0x02
0x0f 0x1c 0xa2 0x02
@@ -112,6 +118,8 @@
# ADD
#------------------------------------------------------------------------------
# CHECK: add r4, r5, #61440
+# CHECK: add r7, r8, #-2147483638
+# CHECK: add r7, r8, #40, #2
# CHECK: add r4, r5, r6
# CHECK: add r4, r5, r6, lsl #5
# CHECK: add r4, r5, r6, lsr #5
@@ -138,6 +146,8 @@
# CHECK: add r4, r4, r5, rrx
0x0f 0x4a 0x85 0xe2
+0x2a 0x71 0x88 0xe2
+0x28 0x71 0x88 0xe2
0x06 0x40 0x85 0xe0
0x86 0x42 0x85 0xe0
0xa6 0x42 0x85 0xe0
@@ -165,6 +175,15 @@
0x65 0x40 0x84 0xe0
#------------------------------------------------------------------------------
+# ADDS
+#------------------------------------------------------------------------------
+# CHECK: adds r7, r8, #-2147483638
+# CHECK: adds r7, r8, #40, #2
+
+0x2a 0x71 0x98 0xe2
+0x28 0x71 0x98 0xe2
+
+#------------------------------------------------------------------------------
# ADR
#------------------------------------------------------------------------------
# CHECK: add r2, pc, #3
@@ -183,6 +202,8 @@
# AND
#------------------------------------------------------------------------------
# CHECK: and r10, r1, #15
+# CHECK: and r7, r8, #-2147483638
+# CHECK: and r7, r8, #40, #2
# CHECK: and r10, r1, r6
# CHECK: and r10, r1, r6, lsl #10
# CHECK: and r10, r1, r6, lsr #10
@@ -209,6 +230,8 @@
# CHECK: and r10, r10, r1, rrx
0x0f 0xa0 0x01 0xe2
+0x2a 0x71 0x08 0xe2
+0x28 0x71 0x08 0xe2
0x06 0xa0 0x01 0xe0
0x06 0xa5 0x01 0xe0
0x26 0xa5 0x01 0xe0
@@ -262,6 +285,8 @@
# BIC
#------------------------------------------------------------------------------
# CHECK: bic r10, r1, #15
+# CHECK: bic r7, r8, #-2147483638
+# CHECK: bic r7, r8, #40, #2
# CHECK: bic r10, r1, r6
# CHECK: bic r10, r1, r6, lsl #10
# CHECK: bic r10, r1, r6, lsr #10
@@ -288,6 +313,8 @@
# CHECK: bic r10, r10, r1, rrx
0x0f 0xa0 0xc1 0xe3
+0x2a 0x71 0xc8 0xe3
+0x28 0x71 0xc8 0xe3
0x06 0xa0 0xc1 0xe1
0x06 0xa5 0xc1 0xe1
0x26 0xa5 0xc1 0xe1
@@ -393,6 +420,8 @@
# CMN
#------------------------------------------------------------------------------
# CHECK: cmn r1, #15
+# CHECK: cmn r7, #40, #2
+# CHECK: cmn r7, #-2147483638
# CHECK: cmn r1, r6
# CHECK: cmn r1, r6, lsl #10
# CHECK: cmn r1, r6, lsr #10
@@ -406,6 +435,8 @@
# CHECK: cmn r1, r6, rrx
0x0f 0x00 0x71 0xe3
+0x28 0x01 0x77 0xe3
+0x2a 0x01 0x77 0xe3
0x06 0x00 0x71 0xe1
0x06 0x05 0x71 0xe1
0x26 0x05 0x71 0xe1
@@ -422,6 +453,8 @@
# CMP
#------------------------------------------------------------------------------
# CHECK: cmp r1, #15
+# CHECK: cmp r7, #40, #2
+# CHECK: cmp r7, #-2147483638
# CHECK: cmp r1, r6
# CHECK: cmp r1, r6, lsl #10
# CHECK: cmp r1, r6, lsr #10
@@ -435,6 +468,8 @@
# CHECK: cmp r1, r6, rrx
0x0f 0x00 0x51 0xe3
+0x28 0x01 0x57 0xe3
+0x2a 0x01 0x57 0xe3
0x06 0x00 0x51 0xe1
0x06 0x05 0x51 0xe1
0x26 0x05 0x51 0xe1
@@ -556,6 +591,8 @@
# EOR
#------------------------------------------------------------------------------
# CHECK: eor r4, r5, #61440
+# CHECK: eor r7, r8, #-2147483638
+# CHECK: eor r7, r8, #40, #2
# CHECK: eor r4, r5, r6
# CHECK: eor r4, r5, r6, lsl #5
# CHECK: eor r4, r5, r6, lsr #5
@@ -582,6 +619,8 @@
# CHECK: eor r4, r4, r5, rrx
0x0f 0x4a 0x25 0xe2
+0x2a 0x71 0x28 0xe2
+0x28 0x71 0x28 0xe2
0x06 0x40 0x25 0xe0
0x86 0x42 0x25 0xe0
0xa6 0x42 0x25 0xe0
@@ -714,10 +753,15 @@
# CHECK: mov r4, #4080
# CHECK: mov r5, #16711680
# CHECK: mov sp, #35
+# CHECK: mov r9, #240, #30
+# CHECK: mov r7, #-2147483638
+# CHECK: mov pc, #2147483658
# CHECK: movw r6, #65535
# CHECK: movw r9, #65535
# CHECK: movw sp, #1193
# CHECK: movs r3, #7
+# CHECK: movs r11, #99
+# CHECK: movs r11, #240, #30
# CHECK: moveq r4, #4080
# CHECK: movseq r5, #16711680
@@ -725,10 +769,15 @@
0xff 0x4e 0xa0 0xe3
0xff 0x58 0xa0 0xe3
0x23 0xd0 0xa0 0xe3
+0xf0 0x9f 0xa0 0xe3
+0x2a 0x71 0xa0 0xe3
+0x2a 0xf1 0xa0 0xe3
0xff 0x6f 0x0f 0xe3
0xff 0x9f 0x0f 0xe3
0xa9 0xd4 0x00 0xe3
0x07 0x30 0xb0 0xe3
+0x63 0xb0 0xb0 0xe3
+0xf0 0xbf 0xb0 0xe3
0xff 0x4e 0xa0 0x03
0xff 0x58 0xb0 0x03
@@ -810,6 +859,8 @@
# CHECK: msr SPSR_fc, #5
# CHECK: msr SPSR_fsxc, #5
# CHECK: msr CPSR_fsxc, #5
+# CHECK: msr APSR_nzcvq, #2147483658
+# CHECK: msr SPSR_fsxc, #40, #2
0x05 0xf0 0x29 0xe3
0x05 0xf0 0x24 0xe3
@@ -825,6 +876,8 @@
0x05 0xf0 0x69 0xe3
0x05 0xf0 0x6f 0xe3
0x05 0xf0 0x2f 0xe3
+0x2a 0xf1 0x28 0xe3
+0x28 0xf1 0x6f 0xe3
# CHECK: msr CPSR_fc, r0
# CHECK: msr APSR_g, r0
@@ -877,14 +930,22 @@
# CHECK: mvn r3, #7
# CHECK: mvn r4, #4080
# CHECK: mvn r5, #16711680
+# CHECK: mvn r7, #40, #2
+# CHECK: mvn r7, #-2147483638
# CHECK: mvns r3, #7
+# CHECK: mvns r11, #240, #30
+# CHECK: mvns r11, #-2147483638
# CHECK: mvneq r4, #4080
# CHECK: mvnseq r5, #16711680
0x07 0x30 0xe0 0xe3
0xff 0x4e 0xe0 0xe3
0xff 0x58 0xe0 0xe3
+0x28 0x71 0xe0 0xe3
+0x2a 0x71 0xe0 0xe3
0x07 0x30 0xf0 0xe3
+0xf0 0xbf 0xf0 0xe3
+0x2a 0xb1 0xf0 0xe3
0xff 0x4e 0xe0 0x03
0xff 0x58 0xf0 0x03
@@ -940,6 +1001,8 @@
# ORR
#------------------------------------------------------------------------------
# CHECK: orr r4, r5, #61440
+# CHECK: orr r7, r8, #-2147483638
+# CHECK: orr r7, r8, #40, #2
# CHECK: orr r4, r5, r6
# CHECK: orr r4, r5, r6, lsl #5
# CHECK: orr r4, r5, r6, lsr #5
@@ -966,6 +1029,8 @@
# CHECK: orr r4, r4, r5, rrx
0x0f 0x4a 0x85 0xe3
+0x2a 0x71 0x88 0xe3
+0x28 0x71 0x88 0xe3
0x06 0x40 0x85 0xe1
0x86 0x42 0x85 0xe1
0xa6 0x42 0x85 0xe1
@@ -1204,6 +1269,8 @@
# RSB
#------------------------------------------------------------------------------
# CHECK: rsb r4, r5, #61440
+# CHECK: rsb r7, r8, #-2147483638
+# CHECK: rsb r7, r8, #40, #2
# CHECK: rsb r4, r5, r6
# CHECK: rsb r4, r5, r6, lsl #5
# CHECK: rsblo r4, r5, r6, lsr #5
@@ -1230,6 +1297,8 @@
# CHECK: rsb r4, r4, r5, rrx
0x0f 0x4a 0x65 0xe2
+0x2a 0x71 0x68 0xe2
+0x28 0x71 0x68 0xe2
0x06 0x40 0x65 0xe0
0x86 0x42 0x65 0xe0
0xa6 0x42 0x65 0x30
@@ -1256,9 +1325,20 @@
0x65 0x40 0x64 0xe0
#------------------------------------------------------------------------------
+# RSBS
+#------------------------------------------------------------------------------
+# CHECK: rsbs r7, r8, #-2147483638
+# CHECK: rsbs r7, r8, #40, #2
+
+0x2a 0x71 0x78 0xe2
+0x28 0x71 0x78 0xe2
+
+#------------------------------------------------------------------------------
# RSC
#------------------------------------------------------------------------------
# CHECK: rsc r4, r5, #61440
+# CHECK: rsc r7, r8, #-2147483638
+# CHECK: rsc r7, r8, #40, #2
# CHECK: rsc r4, r5, r6
# CHECK: rsc r4, r5, r6, lsl #5
# CHECK: rsclo r4, r5, r6, lsr #5
@@ -1283,6 +1363,8 @@
# CHECK: rsc r6, r6, r7, ror r9
0x0f 0x4a 0xe5 0xe2
+0x2a 0x71 0xe8 0xe2
+0x28 0x71 0xe8 0xe2
0x06 0x40 0xe5 0xe0
0x86 0x42 0xe5 0xe0
0xa6 0x42 0xe5 0x30
@@ -1357,6 +1439,8 @@
# SBC
#------------------------------------------------------------------------------
# CHECK: sbc r4, r5, #61440
+# CHECK: sbc r7, r8, #-2147483638
+# CHECK: sbc r7, r8, #40, #2
# CHECK: sbc r4, r5, r6
# CHECK: sbc r4, r5, r6, lsl #5
# CHECK: sbc r4, r5, r6, lsr #5
@@ -1381,6 +1465,8 @@
# CHECK: sbc r6, r6, r7, ror r9
0x0f 0x4a 0xc5 0xe2
+0x2a 0x71 0xc8 0xe2
+0x28 0x71 0xc8 0xe2
0x06 0x40 0xc5 0xe0
0x86 0x42 0xc5 0xe0
0xa6 0x42 0xc5 0xe0
@@ -1868,6 +1954,8 @@
# SUB
#------------------------------------------------------------------------------
# CHECK: sub r4, r5, #61440
+# CHECK: sub r7, r8, #-2147483638
+# CHECK: sub r7, r8, #40, #2
# CHECK: sub r4, r5, r6
# CHECK: sub r4, r5, r6, lsl #5
# CHECK: sub r4, r5, r6, lsr #5
@@ -1892,6 +1980,8 @@
# CHECK: sub r6, r6, r7, ror r9
0x0f 0x4a 0x45 0xe2
+0x2a 0x71 0x48 0xe2
+0x28 0x71 0x48 0xe2
0x06 0x40 0x45 0xe0
0x86 0x42 0x45 0xe0
0xa6 0x42 0x45 0xe0
@@ -1916,6 +2006,14 @@
0x57 0x69 0x46 0xe0
0x77 0x69 0x46 0xe0
+#------------------------------------------------------------------------------
+# SUBS
+#------------------------------------------------------------------------------
+# CHECK: subs r7, r8, #-2147483638
+# CHECK: subs r7, r8, #40, #2
+
+0x2a 0x71 0x58 0xe2
+0x28 0x71 0x58 0xe2
#------------------------------------------------------------------------------
# SVC
@@ -2044,6 +2142,8 @@
# TEQ
#------------------------------------------------------------------------------
# CHECK: teq r5, #61440
+# CHECK: teq r7, #-2147483638
+# CHECK: teq r7, #40, #2
# CHECK: teq r4, r5
# CHECK: teq r4, r5, lsl #5
# CHECK: teq r4, r5, lsr #5
@@ -2056,6 +2156,8 @@
# CHECK: teq r6, r7, ror r9
0x0f 0x0a 0x35 0xe3
+0x2a 0x01 0x37 0xe3
+0x28 0x01 0x37 0xe3
0x05 0x00 0x34 0xe1
0x85 0x02 0x34 0xe1
0xa5 0x02 0x34 0xe1
@@ -2072,6 +2174,8 @@
# TST
#------------------------------------------------------------------------------
# CHECK: tst r5, #61440
+# CHECK: tst r7, #-2147483638
+# CHECK: tst r7, #40, #2
# CHECK: tst r4, r5
# CHECK: tst r4, r5, lsl #5
# CHECK: tst r4, r5, lsr #5
@@ -2084,6 +2188,8 @@
# CHECK: tst r6, r7, ror r9
0x0f 0x0a 0x15 0xe3
+0x2a 0x01 0x17 0xe3
+0x28 0x01 0x17 0xe3
0x05 0x00 0x14 0xe1
0x85 0x02 0x14 0xe1
0xa5 0x02 0x14 0xe1
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