summaryrefslogtreecommitdiffstats
path: root/llvm/test
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir44
1 files changed, 44 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
index 7d0ec021239..e9c165b892b 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-instructionselect.mir
@@ -150,6 +150,7 @@
define void @phi() { ret void }
+ define void @select() { ret void }
...
---
@@ -2874,3 +2875,46 @@ body: |
%s0 = COPY %2
RET_ReallyLR implicit %s0
...
+
+---
+# CHECK-LABEL: name: select
+name: select
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+# CHECK: registers:
+# CHECK-NEXT: - { id: 0, class: gpr32 }
+# CHECK-NEXT: - { id: 1, class: gpr32 }
+# CHECK-NEXT: - { id: 2, class: gpr32 }
+# CHECK-NEXT: - { id: 3, class: gpr32 }
+# CHECK-NEXT: - { id: 4, class: gpr64 }
+# CHECK-NEXT: - { id: 5, class: gpr64 }
+# CHECK-NEXT: - { id: 6, class: gpr64 }
+registers:
+ - { id: 0, class: gpr }
+ - { id: 1, class: gpr }
+ - { id: 2, class: gpr }
+ - { id: 3, class: gpr }
+ - { id: 4, class: gpr }
+ - { id: 5, class: gpr }
+ - { id: 6, class: gpr }
+
+# CHECK: body:
+# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK: %3 = CSELWr %1, %2, 1, implicit %nzcv
+# CHECK: %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK: %6 = CSELXr %4, %5, 1, implicit %nzcv
+body: |
+ bb.0:
+ liveins: %w0, %w1, %w2
+ %0(s1) = COPY %w0
+
+ %1(s32) = COPY %w1
+ %2(s32) = COPY %w2
+ %3(s32) = G_SELECT %0, %1, %2
+
+ %4(s64) = COPY %x0
+ %5(s64) = COPY %x1
+ %6(s64) = G_SELECT %0, %4, %5
+...
OpenPOWER on IntegriCloud