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-rw-r--r--llvm/test/Transforms/InstCombine/signed-truncation-check.ll19
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/signed-truncation-check.ll b/llvm/test/Transforms/InstCombine/signed-truncation-check.ll
index 66f04d5e61e..37de08b1996 100644
--- a/llvm/test/Transforms/InstCombine/signed-truncation-check.ll
+++ b/llvm/test/Transforms/InstCombine/signed-truncation-check.ll
@@ -101,6 +101,25 @@ define i1 @positive_with_aggressive_icmp(i32 %arg) {
; I'm sure there is a bunch more patterns possible :/
+; This used to trigger an assert, because the icmp's are not direct
+; operands of the and.
+define i1 @positive_with_extra_and(i32 %arg, i1 %z) {
+; CHECK-LABEL: @positive_with_extra_and(
+; CHECK-NEXT: [[T1:%.*]] = icmp sgt i32 [[ARG:%.*]], -1
+; CHECK-NEXT: [[T2:%.*]] = add i32 [[ARG]], 128
+; CHECK-NEXT: [[T3:%.*]] = icmp ult i32 [[T2]], 256
+; CHECK-NEXT: [[T4:%.*]] = and i1 [[T1]], [[Z:%.*]]
+; CHECK-NEXT: [[T5:%.*]] = and i1 [[T3]], [[T4]]
+; CHECK-NEXT: ret i1 [[T5]]
+;
+ %t1 = icmp sgt i32 %arg, -1
+ %t2 = add i32 %arg, 128
+ %t3 = icmp ult i32 %t2, 256
+ %t4 = and i1 %t1, %z
+ %t5 = and i1 %t3, %t4
+ ret i1 %t5
+}
+
; ============================================================================ ;
; Vector tests
; ============================================================================ ;
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