4 files changed, 198 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll b/llvm/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll
new file mode 100644
index 00000000000..7c5ea031ffa
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/hwloop-pos-ivbump1.ll
@@ -0,0 +1,45 @@
+;RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Test that a hardware loop is not generaetd due to a potential
+; underflow.
+
+; CHECK-NOT: loop0
+
+define i32 @main() #0 {
+entry:
+  br label %while.cond.outer
+
+while.cond.outer.loopexit:
+  %.lcssa = phi i32 [ %0, %for.body.preheader ]
+  br label %while.cond.outer
+
+while.cond.outer:
+  %i.0.ph = phi i32 [ 0, %entry ], [ 3, %while.cond.outer.loopexit ]
+  %j.0.ph = phi i32 [ 0, %entry ], [ %.lcssa, %while.cond.outer.loopexit ]
+  %k.0.ph = phi i32 [ 0, %entry ], [ 1, %while.cond.outer.loopexit ]
+  br label %while.cond
+
+while.cond:
+  %i.0 = phi i32 [ %i.0.ph, %while.cond.outer ], [ %inc, %for.body.preheader ]
+  %j.0 = phi i32 [ %j.0.ph, %while.cond.outer ], [ %0, %for.body.preheader ]
+  %inc = add nsw i32 %i.0, 1
+  %cmp = icmp slt i32 %i.0, 4
+  br i1 %cmp, label %for.body.preheader, label %while.end
+
+for.body.preheader:
+  %0 = add i32 %j.0, 3
+  %cmp5 = icmp eq i32 %inc, 3
+  br i1 %cmp5, label %while.cond.outer.loopexit, label %while.cond
+
+while.end:
+  %k.0.ph.lcssa = phi i32 [ %k.0.ph, %while.cond ]
+  %inc.lcssa = phi i32 [ %inc, %while.cond ]
+  %j.0.lcssa = phi i32 [ %j.0, %while.cond ]
+  %cmp6 = icmp ne i32 %inc.lcssa, 5
+  %cmp7 = icmp ne i32 %j.0.lcssa, 12
+  %or.cond = or i1 %cmp6, %cmp7
+  %cmp9 = icmp ne i32 %k.0.ph.lcssa, 1
+  %or.cond12 = or i1 %or.cond, %cmp9
+  %locflg.0 = zext i1 %or.cond12 to i32
+  ret i32 %locflg.0
+}
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-recursion.ll b/llvm/test/CodeGen/Hexagon/hwloop-recursion.ll
new file mode 100644
index 00000000000..8ab2dc37d02
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/hwloop-recursion.ll
@@ -0,0 +1,64 @@
+; RUN: llc -O2 -march=hexagon -mcpu=hexagonv5 < %s
+; REQUIRES: asserts
+; Check for successful compilation.
+
+@c = common global i32 0, align 4
+@e = common global i32 0, align 4
+@g = common global i32* null, align 4
+@a = common global i32 0, align 4
+@b = common global i32 0, align 4
+@h = common global i32* null, align 4
+@d = common global i32 0, align 4
+@f = common global i32 0, align 4
+
+define i32 @fn1([0 x i32]* nocapture readnone %p1) #0 {
+entry:
+  %0 = load i32*, i32** @h, align 4
+  %1 = load i32*, i32** @g, align 4
+  %.pre = load i32, i32* @c, align 4
+  br label %for.cond
+
+for.cond:
+  %2 = phi i32 [ %10, %if.end ], [ %.pre, %entry ]
+  store i32 %2, i32* @e, align 4
+  %tobool5 = icmp eq i32 %2, 0
+  br i1 %tobool5, label %for.end, label %for.body.lr.ph
+
+for.body.lr.ph:
+  %3 = sub i32 -5, %2
+  %4 = urem i32 %3, 5
+  %5 = sub i32 %3, %4
+  br label %for.body
+
+for.body:
+  %add6 = phi i32 [ %2, %for.body.lr.ph ], [ %add, %for.body ]
+  %6 = load i32, i32* %1, align 4
+  store i32 %6, i32* @a, align 4
+  %add = add nsw i32 %add6, 5
+  %tobool = icmp eq i32 %add, 0
+  br i1 %tobool, label %for.cond1.for.end_crit_edge, label %for.body
+
+for.cond1.for.end_crit_edge:
+  %7 = add i32 %2, 5
+  %8 = add i32 %7, %5
+  store i32 %8, i32* @e, align 4
+  br label %for.end
+
+for.end:
+  %9 = load i32, i32* @b, align 4
+  %tobool2 = icmp eq i32 %9, 0
+  br i1 %tobool2, label %if.end, label %if.then
+
+if.then:
+  store i32 0, i32* %0, align 4
+  %.pre7 = load i32, i32* @c, align 4
+  br label %if.end
+
+if.end:
+  %10 = phi i32 [ %2, %for.end ], [ %.pre7, %if.then ]
+  store i32 %10, i32* @d, align 4
+  %11 = load i32, i32* @f, align 4
+  %inc = add nsw i32 %11, 1
+  store i32 %inc, i32* @f, align 4
+  br label %for.cond
+}
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-wrap.ll b/llvm/test/CodeGen/Hexagon/hwloop-wrap.ll
new file mode 100644
index 00000000000..e0f6a87fd2e
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/hwloop-wrap.ll
@@ -0,0 +1,22 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
+
+; We shouldn't generate a hardware loop in this case because the initial
+; value may be zero, which means the endloop instruction will not decrement
+; the loop counter, and the loop will execute only once.
+
+; CHECK-NOT: loop0
+
+define void @foo(i32 %count, i32 %v) #0 {
+entry:
+  br label %do.body
+
+do.body:
+  %count.addr.0 = phi i32 [ %count, %entry ], [ %dec, %do.body ]
+  tail call void asm sideeffect "nop", ""() #1
+  %dec = add i32 %count.addr.0, -1
+  %cmp = icmp eq i32 %dec, 0
+  br i1 %cmp, label %do.end, label %do.body
+
+do.end:
+  ret void
+}
diff --git a/llvm/test/CodeGen/Hexagon/hwloop-wrap2.ll b/llvm/test/CodeGen/Hexagon/hwloop-wrap2.ll
new file mode 100644
index 00000000000..50675d6b681
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/hwloop-wrap2.ll
@@ -0,0 +1,67 @@
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s | FileCheck %s
+
+; Test that we do not generate a hardware loop due to a potential underflow.
+
+; CHECK-NOT: loop0
+
+%struct.3 = type { i8*, i8, i8, i32, i32, i16, i16, i16, i16, i16, i16, i16, %struct.2* }
+%struct.2 = type { i16, i16, i16, i16, %struct.1* }
+%struct.1 = type { %struct.1*, %struct.0*, i32, i32, i16, [2 x i16], [2 x i16], i16 }
+%struct.0 = type { %struct.0*, i32, i32, i32, i32, i32, i32, i16, i16, i16, i8, i8, i8, i8 }
+
+@pairArray = external global i32**
+@carray = external global %struct.3**
+
+define void @test() #0 {
+entry:
+  %0 = load i32**, i32*** @pairArray, align 4
+  %1 = load %struct.3**, %struct.3*** @carray, align 4
+  br i1 undef, label %for.end110, label %for.body
+
+for.body:
+  %row.0199 = phi i32 [ %inc109, %for.inc108 ], [ 1, %entry ]
+  %arrayidx = getelementptr inbounds i32*, i32** %0, i32 %row.0199
+  %2 = load i32*, i32** %arrayidx, align 4
+  br i1 undef, label %for.body48, label %for.inc108
+
+for.cond45:
+  %cmp46 = icmp sgt i32 %dec58, 0
+  br i1 %cmp46, label %for.body48, label %for.inc108
+
+for.body48:
+  %i.1190 = phi i32 [ %dec58, %for.cond45 ], [ 0, %for.body ]
+  %arrayidx50 = getelementptr inbounds i32, i32* %2, i32 %i.1190
+  %3 = load i32, i32* %arrayidx50, align 4
+  %cmp53 = icmp slt i32 %3, 0
+  %dec58 = add nsw i32 %i.1190, -1
+  br i1 %cmp53, label %for.end59, label %for.cond45
+
+for.end59:
+  %cmp60 = icmp slt i32 %i.1190, 0
+  br i1 %cmp60, label %if.then65, label %for.inc108
+
+if.then65:
+  br label %for.body80
+
+for.body80:
+  %j.1196.in = phi i32 [ %j.1196, %for.body80 ], [ %i.1190, %if.then65 ]
+  %j.1196 = add nsw i32 %j.1196.in, 1
+  %arrayidx81 = getelementptr inbounds i32, i32* %2, i32 %j.1196
+  %4 = load i32, i32* %arrayidx81, align 4
+  %arrayidx82 = getelementptr inbounds %struct.3*, %struct.3** %1, i32 %4
+  %5 = load %struct.3*, %struct.3** %arrayidx82, align 4
+  %cxcenter83 = getelementptr inbounds %struct.3, %struct.3* %5, i32 0, i32 3
+  store i32 0, i32* %cxcenter83, align 4
+  %6 = load i32, i32* %arrayidx81, align 4
+  %arrayidx87 = getelementptr inbounds i32, i32* %2, i32 %j.1196.in
+  store i32 %6, i32* %arrayidx87, align 4
+  %exitcond = icmp eq i32 %j.1196, 0
+  br i1 %exitcond, label %for.inc108, label %for.body80
+
+for.inc108:
+  %inc109 = add nsw i32 %row.0199, 1
+  br i1 undef, label %for.body, label %for.end110
+
+for.end110:
+  ret void
+}