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-rw-r--r--llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir3
-rw-r--r--llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir3
-rw-r--r--llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir1
3 files changed, 5 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
index 781cb5d8243..09d0b96164d 100644
--- a/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDDWRdPtrQ.mir
@@ -12,6 +12,7 @@
---
name: test_lddwrdptrq
+tracksRegLiveness: true
body: |
bb.0.entry:
@@ -20,5 +21,5 @@ body: |
; CHECK: ldd r30, Y+10
; CHECK-NEXT: ldd r31, Y+11
- early-clobber %r31r30 = LDDWRdPtrQ %r29r28, 10
+ early-clobber %r31r30 = LDDWRdPtrQ undef %r29r28, 10
...
diff --git a/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir b/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
index 472f498b912..7d3251adbda 100644
--- a/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/LDDWRdYQ.mir
@@ -12,6 +12,7 @@
---
name: test_lddwrdyq
+tracksRegLiveness: true
body: |
bb.0.entry:
@@ -20,5 +21,5 @@ body: |
; CHECK: ldd r30, Y+1
; CHECK-NEXT: ldd r31, Y+2
- early-clobber %r31r30 = LDDWRdYQ %r29r28, 1
+ early-clobber %r31r30 = LDDWRdYQ undef %r29r28, 1
...
diff --git a/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir b/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir
index 5ed95ad76a7..52945e6cf84 100644
--- a/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir
+++ b/llvm/test/CodeGen/AVR/pseudo/expand-lddw-dst-src-same.mir
@@ -18,6 +18,7 @@
...
---
name: test_lddw
+tracksRegLiveness: true
stack:
- { id: 0, type: spill-slot, offset: -4, size: 1, alignment: 1, callee-saved-register: '%r28' }
body: |
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