diff options
Diffstat (limited to 'llvm/test')
35 files changed, 643 insertions, 428 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt deleted file mode 100644 index 1b669389e7b..00000000000 --- a/llvm/test/MC/Disassembler/Mips/mips4/valid-xfail-mips4.txt +++ /dev/null @@ -1,38 +0,0 @@ -# RUN: llvm-mc %s -triple=mips64-unknown-linux -disassemble -mcpu=mips4 | FileCheck %s -# XFAIL: * -0x46 0x2f 0x79 0x32 # CHECK: c.eq.d $fcc1, $f15, $f15 -0x46 0x11 0xc5 0x32 # CHECK: c.eq.s $fcc5, $f24, $f17 -0x46 0x35 0x5c 0x30 # CHECK: c.f.d $fcc4, $f11, $f21 -0x46 0x07 0xf4 0x30 # CHECK: c.f.s $fcc4, $f30, $f7 -0x46 0x21 0x94 0x3e # CHECK: c.le.d $fcc4, $f18, $f1 -0x46 0x04 0xc6 0x3e # CHECK: c.le.s $fcc6, $f24, $f4 -0x46 0x23 0x4b 0x3c # CHECK: c.lt.d $fcc3, $f9, $f3 -0x46 0x0e 0x8a 0x3c # CHECK: c.lt.s $fcc2, $f17, $f14 -0x46 0x30 0xad 0x3d # CHECK: c.nge.d $fcc5, $f21, $f16 -0x46 0x08 0x5b 0x3d # CHECK: c.nge.s $fcc3, $f11, $f8 -0x46 0x17 0xfa 0x3b # CHECK: c.ngl.s $fcc2, $f31, $f23 -0x46 0x17 0x92 0x39 # CHECK: c.ngle.s $fcc2, $f18, $f23 -0x46 0x27 0xc4 0x3f # CHECK: c.ngt.d $fcc4, $f24, $f7 -0x46 0x0d 0x45 0x3f # CHECK: c.ngt.s $fcc5, $f8, $f13 -0x46 0x3f 0x82 0x36 # CHECK: c.ole.d $fcc2, $f16, $f31 -0x46 0x14 0x3b 0x36 # CHECK: c.ole.s $fcc3, $f7, $f20 -0x46 0x3c 0x9c 0x34 # CHECK: c.olt.d $fcc4, $f19, $f28 -0x46 0x07 0xa6 0x34 # CHECK: c.olt.s $fcc6, $f20, $f7 -0x46 0x27 0xfc 0x3a # CHECK: c.seq.d $fcc4, $f31, $f7 -0x46 0x19 0x0f 0x3a # CHECK: c.seq.s $fcc7, $f1, $f25 -0x46 0x39 0x6c 0x33 # CHECK: c.ueq.d $fcc4, $f13, $f25 -0x46 0x1e 0x1e 0x33 # CHECK: c.ueq.s $fcc6, $f3, $f30 -0x46 0x32 0xcf 0x37 # CHECK: c.ule.d $fcc7, $f25, $f18 -0x46 0x1e 0xaf 0x37 # CHECK: c.ule.s $fcc7, $f21, $f30 -0x46 0x31 0x36 0x35 # CHECK: c.ult.d $fcc6, $f6, $f17 -0x46 0x0a 0xc7 0x35 # CHECK: c.ult.s $fcc7, $f24, $f10 -0x46 0x38 0xbe 0x31 # CHECK: c.un.d $fcc6, $f23, $f24 -0x46 0x04 0xf1 0x31 # CHECK: c.un.s $fcc1, $f30, $f4 -0x4e 0x74 0xd4 0xa1 # CHECK: madd.d $f18, $f19, $f26, $f20 -0x4f 0xf9 0x98 0x60 # CHECK: madd.s $f1, $f31, $f19, $f25 -0x4c 0x32 0xfa 0xa9 # CHECK: msub.d $f10, $f1, $f31, $f18 -0x4e 0x70 0x53 0x28 # CHECK: msub.s $f12, $f19, $f10, $f16 -0x4d 0x33 0x74 0xb1 # CHECK: nmadd.d $f18, $f9, $f14, $f19 -0x4c 0xac 0xc8 0x30 # CHECK: nmadd.s $f0, $f5, $f25, $f12 -0x4d 0x1e 0x87 0xb9 # CHECK: nmsub.d $f30, $f8, $f16, $f30 -0x4f 0x04 0x98 0x78 # CHECK: nmsub.s $f1, $f24, $f19, $f4 diff --git a/llvm/test/MC/Mips/micromips/valid.s b/llvm/test/MC/Mips/micromips/valid.s index c1efc4d0904..cf19a959683 100644 --- a/llvm/test/MC/Mips/micromips/valid.s +++ b/llvm/test/MC/Mips/micromips/valid.s @@ -210,6 +210,42 @@ recip.s $f2, $f4 # CHECK: recip.s $f2, $f4 # encoding: [0x54,0x recip.d $f2, $f4 # CHECK: recip.d $f2, $f4 # encoding: [0x54,0x44,0x52,0x3b] rsqrt.s $f3, $f5 # CHECK: rsqrt.s $f3, $f5 # encoding: [0x54,0x65,0x02,0x3b] rsqrt.d $f2, $f4 # CHECK: rsqrt.d $f2, $f4 # encoding: [0x54,0x44,0x42,0x3b] +c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x55,0xce,0x24,0xbc] +c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x56,0x38,0xa0,0xbc] +c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x56,0x8a,0x84,0x3c] +c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x54,0xfe,0x80,0x3c] +c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x54,0x12,0x87,0xbc] +c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x54,0x98,0xc3,0xbc] +c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x54,0x48,0x67,0x3c] +c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x55,0xd1,0x43,0x3c] +c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x56,0x14,0xa7,0x7c] +c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x55,0x0b,0x63,0x7c] +c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x56,0xff,0x42,0xfc] +c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x56,0xf2,0x42,0x7c] +c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x57,0x9c,0x06,0xfc] +c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x56,0x00,0x06,0x7c] +c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x54,0xd8,0x87,0xfc] +c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x55,0xa8,0xa3,0xfc] +c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x57,0xd0,0x45,0xbc] +c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x56,0x87,0x61,0xbc] +c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x57,0x92,0x85,0x3c] +c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x54,0xf4,0xc1,0x3c] +c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x54,0xde,0x86,0xbc] +c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x57,0x21,0xe2,0xbc] +c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x54,0x1e,0x06,0x3c] +c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x56,0xce,0x02,0x3c] +c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x57,0x0c,0x84,0xfc] +c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x57,0xc3,0xc0,0xfc] +c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x56,0x58,0xe5,0xfc] +c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x57,0xd5,0xe1,0xfc] +c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x56,0x06,0xc5,0x7c] +c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x55,0x58,0xe1,0x7c] +c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x57,0x16,0xc4,0x7c] +c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x54,0x9e,0x20,0x7c] +bc1t 8 # CHECK: bc1t 8 # encoding: [0x43,0xa0,0x00,0x04] +bc1f 16 # CHECK: bc1f 16 # encoding: [0x43,0x80,0x00,0x08] +bc1t $fcc1, 4 # CHECK: bc1t $fcc1, 4 # encoding: [0x43,0xa0,0x00,0x02] +bc1f $fcc2, -20 # CHECK: bc1f $fcc2, -20 # encoding: [0x43,0x80,0xff,0xf6] sync # CHECK: sync # encoding: [0x00,0x00,0x6b,0x7c] sync 0 # CHECK: sync 0 # encoding: [0x00,0x00,0x6b,0x7c] sync 1 # CHECK: sync 1 # encoding: [0x00,0x01,0x6b,0x7c] diff --git a/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s index cc4f56b7595..98f34d857a5 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips4-wrong-error.s @@ -6,8 +6,8 @@ # RUN: FileCheck %s < %t1 .set noat - bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ldc2 $8,-21181($at) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset ldc2 $20,-1024($s2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offset ldl $24,-4167($24) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips1/invalid-mips4.s b/llvm/test/MC/Mips/mips1/invalid-mips4.s index 4d5a173b157..e99fb6628e6 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips4.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips4.s @@ -5,8 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat - bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -53,19 +53,19 @@ ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f26,$f20,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s index 18c0b61ff55..0564c1a250c 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s @@ -44,3 +44,35 @@ pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.s $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.s $fcc6, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.s $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.s $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.d $fcc4, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.d $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.d $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.d $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.d $fcc3, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.d $fcc6, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.d $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.d $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.d $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.d $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5.s b/llvm/test/MC/Mips/mips1/invalid-mips5.s index 6096c3e87b2..f909c07f15f 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips5.s @@ -5,8 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat - bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.w.d $f11,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -52,19 +52,19 @@ luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f10,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f10,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips2/invalid-mips32.s b/llvm/test/MC/Mips/mips2/invalid-mips32.s index 1e451fd2466..bd02882de39 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips32.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips32.s @@ -5,8 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat - bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level clo $11,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -20,19 +20,19 @@ maddu $24,$s2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -41,3 +41,35 @@ mtc0 $9,$29,3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mul $s0,$s4,$at # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sync 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs + c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.s $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.s $fcc6, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.s $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.s $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.d $fcc4, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.d $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.d $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.d $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.d $fcc3, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.d $fcc6, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.d $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.d $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.d $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.d $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level diff --git a/llvm/test/MC/Mips/mips2/invalid-mips32r2.s b/llvm/test/MC/Mips/mips2/invalid-mips32r2.s index 6dc8159a9ac..383430d3aa0 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips32r2.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips32r2.s @@ -5,12 +5,44 @@ # RUN: FileCheck %s < %t1 .set noat - bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level clo $t3,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled clz $sp,$gp # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.l.d $f24,$f15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.l.s $f11,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.s $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.s $fcc6, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.s $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.s $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.d $fcc4, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.d $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.d $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.d $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.d $fcc3, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.d $fcc6, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.d $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.d $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.d $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.d $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level deret # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled di $s8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled di # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -29,19 +61,19 @@ mfc0 $a2,$14,1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled mfhc1 $s8,$f24 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$t1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s index ef5657833ca..5ced993c2e1 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips4-wrong-error.s @@ -6,8 +6,8 @@ # RUN: FileCheck %s < %t1 .set noat - bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level scd $15,-8243($sp) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 9-bit signed offset sdl $a3,-20961($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction sdr $11,-20423($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips2/invalid-mips4.s b/llvm/test/MC/Mips/mips2/invalid-mips4.s index f14ae8c3065..123235eb00b 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips4.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips4.s @@ -5,8 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat - bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -50,19 +50,19 @@ lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwu $s3,-24086($v1) # CHECK: :[[@LINE]]:23: error: expected memory with 12-bit signed offset movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips2/invalid-mips5.s b/llvm/test/MC/Mips/mips2/invalid-mips5.s index 8f460c7b273..ea563372fc1 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips5.s @@ -5,8 +5,8 @@ # RUN: FileCheck %s < %t1 .set noat - bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled ceil.l.s $f18,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.d.l $f4,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -48,19 +48,19 @@ luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$a0,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf $gp,$a0,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -71,3 +71,36 @@ sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.s $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.s $fcc6, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.s $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.s $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.d $fcc4, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.d $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.d $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.d $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.d $fcc3, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.d $fcc6, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.d $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.d $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.d $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.d $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + diff --git a/llvm/test/MC/Mips/mips3/invalid-mips4-wrong-error.s b/llvm/test/MC/Mips/mips3/invalid-mips4-wrong-error.s deleted file mode 100644 index c9af39a46fe..00000000000 --- a/llvm/test/MC/Mips/mips3/invalid-mips4-wrong-error.s +++ /dev/null @@ -1,10 +0,0 @@ -# Instructions that are invalid and are correctly rejected but use the wrong -# error message at the moment. -# -# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips3 \ -# RUN: 2>%t1 -# RUN: FileCheck %s < %t1 - - .set noat - bc1fl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1tl $fcc7,27 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips3/invalid-mips4.s b/llvm/test/MC/Mips/mips3/invalid-mips4.s index 9cd92d39e31..e95ca00d803 100644 --- a/llvm/test/MC/Mips/mips3/invalid-mips4.s +++ b/llvm/test/MC/Mips/mips3/invalid-mips4.s @@ -5,26 +5,58 @@ # RUN: FileCheck %s < %t1 .set noat - bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level ldxc1 $f8,$s7($15) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$10($14) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$12($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.s $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.s $fcc6, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.s $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.s $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.d $fcc4, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.d $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.d $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.d $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.d $fcc3, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.d $fcc6, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.d $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.d $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.d $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.d $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level diff --git a/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s index cf809d3af2d..6cfd1625d12 100644 --- a/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s @@ -44,3 +44,4 @@ pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction + diff --git a/llvm/test/MC/Mips/mips3/invalid-mips5.s b/llvm/test/MC/Mips/mips3/invalid-mips5.s index 307eee82075..f851e1304ba 100644 --- a/llvm/test/MC/Mips/mips3/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips3/invalid-mips5.s @@ -5,28 +5,61 @@ # RUN: FileCheck %s < %t1 .set noat - bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level ldxc1 $f8,$s7($t3) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled lwxc1 $f12,$s1($s8) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf $gp,$8,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf $gp,$8,$fcc7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.d $f6,$f11,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.d $f6,$f11,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movf.s $f23,$f5,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movf.s $f23,$f5,$fcc6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn $v1,$s1,$s0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.d $f27,$f21,$k0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movn.s $f12,$f0,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt $zero,$s4,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt $zero,$s4,$fcc5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.d $f0,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movt.s $f30,$f2,$fcc0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction + movt.s $f30,$f2,$fcc1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$a6($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.s $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.s $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.s $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.s $fcc3, $f7, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.s $fcc6, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.s $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.s $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.s $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.s $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.s $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.eq.d $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.f.d $fcc4, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.le.d $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.lt.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.nge.d $fcc3, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngl.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngle.d $fcc2, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ngt.d $fcc5, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ole.d $fcc3, $f8, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.olt.d $fcc6, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.seq.d $fcc7, $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.sf.d $fcc4, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ueq.d $fcc6, $f3, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ule.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.ult.d $fcc7, $f2, $f6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + c.un.d $fcc1, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level + diff --git a/llvm/test/MC/Mips/mips32/valid-xfail.s b/llvm/test/MC/Mips/mips32/valid-xfail.s index d680740babf..5b48896cc00 100644 --- a/llvm/test/MC/Mips/mips32/valid-xfail.s +++ b/llvm/test/MC/Mips/mips32/valid-xfail.s @@ -7,32 +7,20 @@ # XFAIL: * .set noat - c.eq.d $fcc1,$f15,$f15 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.s $fcc3,$f11,$f8 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.s $fcc7,$f1,$f25 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.s $fcc1,$f30,$f4 + c.eq.ps $fcc5,$f0,$f9 + c.f.ps $fcc6,$f11,$f11 + c.le.ps $fcc1,$f7,$f20 + c.lt.ps $f19,$f5 + c.nge.ps $f1,$f26 + c.ngl.ps $f21,$f30 + c.ngle.ps $fcc7,$f12,$f20 + c.ngt.ps $fcc5,$f30,$f6 + c.ole.ps $fcc7,$f21,$f8 + c.olt.ps $fcc3,$f7,$f16 + c.seq.ps $fcc6,$f31,$f14 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.ps $fcc1,$f5,$f29 + c.ule.ps $fcc6,$f17,$f3 + c.ult.ps $fcc7,$f14,$f0 + c.un.ps $fcc4,$f2,$f26 rorv $13,$a3,$s5 diff --git a/llvm/test/MC/Mips/mips32/valid.s b/llvm/test/MC/Mips/mips32/valid.s index c24abe31fbd..4685a1f3696 100644 --- a/llvm/test/MC/Mips/mips32/valid.s +++ b/llvm/test/MC/Mips/mips32/valid.s @@ -41,10 +41,38 @@ a: bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 diff --git a/llvm/test/MC/Mips/mips32r2/valid-xfail.s b/llvm/test/MC/Mips/mips32r2/valid-xfail.s index 6fab97f7a62..acd7802628d 100644 --- a/llvm/test/MC/Mips/mips32r2/valid-xfail.s +++ b/llvm/test/MC/Mips/mips32r2/valid-xfail.s @@ -12,50 +12,22 @@ addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 cfcmsa $s6,$19 diff --git a/llvm/test/MC/Mips/mips32r2/valid.s b/llvm/test/MC/Mips/mips32r2/valid.s index 8cde9dc5c80..3cd6a09fdd8 100644 --- a/llvm/test/MC/Mips/mips32r2/valid.s +++ b/llvm/test/MC/Mips/mips32r2/valid.s @@ -41,10 +41,38 @@ a: bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 diff --git a/llvm/test/MC/Mips/mips32r3/valid-xfail.s b/llvm/test/MC/Mips/mips32r3/valid-xfail.s index a442beb6198..d8e760fb807 100644 --- a/llvm/test/MC/Mips/mips32r3/valid-xfail.s +++ b/llvm/test/MC/Mips/mips32r3/valid-xfail.s @@ -12,50 +12,22 @@ addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 cfcmsa $s6,$19 diff --git a/llvm/test/MC/Mips/mips32r3/valid.s b/llvm/test/MC/Mips/mips32r3/valid.s index 67820bdde99..b69a78776a4 100644 --- a/llvm/test/MC/Mips/mips32r3/valid.s +++ b/llvm/test/MC/Mips/mips32r3/valid.s @@ -41,10 +41,38 @@ a: bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 diff --git a/llvm/test/MC/Mips/mips32r5/valid-xfail.s b/llvm/test/MC/Mips/mips32r5/valid-xfail.s index 33ea7c46358..b0c0861465b 100644 --- a/llvm/test/MC/Mips/mips32r5/valid-xfail.s +++ b/llvm/test/MC/Mips/mips32r5/valid-xfail.s @@ -12,50 +12,22 @@ addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 cfcmsa $s6,$19 diff --git a/llvm/test/MC/Mips/mips32r5/valid.s b/llvm/test/MC/Mips/mips32r5/valid.s index e53b7f3177c..5ac82e7fe98 100644 --- a/llvm/test/MC/Mips/mips32r5/valid.s +++ b/llvm/test/MC/Mips/mips32r5/valid.s @@ -41,10 +41,38 @@ a: bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 diff --git a/llvm/test/MC/Mips/mips4/valid-xfail.s b/llvm/test/MC/Mips/mips4/valid-xfail.s index 21129bb9dbc..b55e21083b0 100644 --- a/llvm/test/MC/Mips/mips4/valid-xfail.s +++ b/llvm/test/MC/Mips/mips4/valid-xfail.s @@ -7,31 +7,19 @@ # XFAIL: * .set noat - c.eq.d $fcc1,$f15,$f15 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.s $fcc3,$f11,$f8 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.s $fcc7,$f1,$f25 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.s $fcc1,$f30,$f4 + c.eq.ps $fcc5,$f0,$f9 + c.f.ps $fcc6,$f11,$f11 + c.le.ps $fcc1,$f7,$f20 + c.lt.ps $f19,$f5 + c.nge.ps $f1,$f26 + c.ngl.ps $f21,$f30 + c.ngle.ps $fcc7,$f12,$f20 + c.ngt.ps $fcc5,$f30,$f6 + c.ole.ps $fcc7,$f21,$f8 + c.olt.ps $fcc3,$f7,$f16 + c.seq.ps $fcc6,$f31,$f14 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.ps $fcc1,$f5,$f29 + c.ule.ps $fcc6,$f17,$f3 + c.ult.ps $fcc7,$f14,$f0 + c.un.ps $fcc4,$f2,$f26 diff --git a/llvm/test/MC/Mips/mips4/valid.s b/llvm/test/MC/Mips/mips4/valid.s index 62cd3905d4e..69cea599e74 100644 --- a/llvm/test/MC/Mips/mips4/valid.s +++ b/llvm/test/MC/Mips/mips4/valid.s @@ -41,10 +41,38 @@ a: bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 diff --git a/llvm/test/MC/Mips/mips5/valid-xfail.s b/llvm/test/MC/Mips/mips5/valid-xfail.s index 8517315780e..2c6711b47d3 100644 --- a/llvm/test/MC/Mips/mips5/valid-xfail.s +++ b/llvm/test/MC/Mips/mips5/valid-xfail.s @@ -10,50 +10,22 @@ abs.ps $f22,$f8 add.ps $f25,$f27,$f13 alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 diff --git a/llvm/test/MC/Mips/mips5/valid.s b/llvm/test/MC/Mips/mips5/valid.s index 77204f99608..85fdfb507aa 100644 --- a/llvm/test/MC/Mips/mips5/valid.s +++ b/llvm/test/MC/Mips/mips5/valid.s @@ -41,10 +41,38 @@ a: bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 diff --git a/llvm/test/MC/Mips/mips64/valid-xfail.s b/llvm/test/MC/Mips/mips64/valid-xfail.s index c7513bf5d7e..9bf899c2270 100644 --- a/llvm/test/MC/Mips/mips64/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64/valid-xfail.s @@ -13,50 +13,22 @@ alnv.ob $v31,$v23,$v30,$at alnv.ob $v8,$v17,$v30,$a1 alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 diff --git a/llvm/test/MC/Mips/mips64/valid.s b/llvm/test/MC/Mips/mips64/valid.s index f34bfafa8fc..716488df7b5 100644 --- a/llvm/test/MC/Mips/mips64/valid.s +++ b/llvm/test/MC/Mips/mips64/valid.s @@ -41,10 +41,38 @@ a: bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 diff --git a/llvm/test/MC/Mips/mips64r2/valid-xfail.s b/llvm/test/MC/Mips/mips64r2/valid-xfail.s index d55d1fb9a19..90cd760712c 100644 --- a/llvm/test/MC/Mips/mips64r2/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r2/valid-xfail.s @@ -12,50 +12,22 @@ addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s index 500a7577179..656b76c758e 100644 --- a/llvm/test/MC/Mips/mips64r2/valid.s +++ b/llvm/test/MC/Mips/mips64r2/valid.s @@ -41,10 +41,38 @@ a: bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 diff --git a/llvm/test/MC/Mips/mips64r3/valid-xfail.s b/llvm/test/MC/Mips/mips64r3/valid-xfail.s index 2f38e73e442..15c59f3f896 100644 --- a/llvm/test/MC/Mips/mips64r3/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r3/valid-xfail.s @@ -15,50 +15,22 @@ alnv.ob $v31,$v23,$v30,$at alnv.ob $v8,$v17,$v30,$a1 alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 diff --git a/llvm/test/MC/Mips/mips64r3/valid.s b/llvm/test/MC/Mips/mips64r3/valid.s index 8e2343b0ad1..52d44da8f56 100644 --- a/llvm/test/MC/Mips/mips64r3/valid.s +++ b/llvm/test/MC/Mips/mips64r3/valid.s @@ -41,10 +41,38 @@ a: bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 diff --git a/llvm/test/MC/Mips/mips64r5/valid-xfail.s b/llvm/test/MC/Mips/mips64r5/valid-xfail.s index 44ff4ee9fc0..1ba984bdf90 100644 --- a/llvm/test/MC/Mips/mips64r5/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r5/valid-xfail.s @@ -15,50 +15,22 @@ alnv.ob $v31,$v23,$v30,$at alnv.ob $v8,$v17,$v30,$a1 alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 diff --git a/llvm/test/MC/Mips/mips64r5/valid.s b/llvm/test/MC/Mips/mips64r5/valid.s index f31374f9fce..f400436b696 100644 --- a/llvm/test/MC/Mips/mips64r5/valid.s +++ b/llvm/test/MC/Mips/mips64r5/valid.s @@ -41,10 +41,38 @@ a: bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 |
