summaryrefslogtreecommitdiffstats
path: root/llvm/test
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/test')
-rw-r--r--llvm/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir26
1 files changed, 26 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir b/llvm/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir
new file mode 100644
index 00000000000..fc19173a176
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/fast-regalloc-empty-bb-with-liveins.mir
@@ -0,0 +1,26 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple aarch64-apple-ios -run-pass regallocfast -o - %s | FileCheck %s
+# This test used to crash the fast register alloc.
+# Basically, when a basic block has liveins, the fast regalloc
+# was deferencing the begin iterator of this block. However,
+# when this block is empty and it will just crashed!
+---
+name: crashing
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: crashing
+ ; CHECK: bb.0:
+ ; CHECK: successors: %bb.1(0x80000000)
+ ; CHECK: liveins: %x0, %x1
+ ; CHECK: bb.1:
+ ; CHECK: renamable %w0 = MOVi32imm -1
+ ; CHECK: RET_ReallyLR implicit killed %w0
+ bb.1:
+ liveins: %x0, %x1
+
+ bb.2:
+ %0:gpr32 = MOVi32imm -1
+ %w0 = COPY %0
+ RET_ReallyLR implicit %w0
+
+...
OpenPOWER on IntegriCloud