4 files changed, 1067 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/RISCV/bare-select.ll b/llvm/test/CodeGen/RISCV/bare-select.ll
index 3b7287ff679..59add65d1db 100644
--- a/llvm/test/CodeGen/RISCV/bare-select.ll
+++ b/llvm/test/CodeGen/RISCV/bare-select.ll
@@ -15,3 +15,17 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) {
   %1 = select i1 %a, i32 %b, i32 %c
   ret i32 %1
 }
+
+define float @bare_select_float(i1 %a, float %b, float %c) {
+; RV32I-LABEL: bare_select_float:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    bnez a0, .LBB1_2
+; RV32I-NEXT:  # %bb.1:
+; RV32I-NEXT:    mv a1, a2
+; RV32I-NEXT:  .LBB1_2:
+; RV32I-NEXT:    mv a0, a1
+; RV32I-NEXT:    ret
+  %1 = select i1 %a, float %b, float %c
+  ret float %1
+}
diff --git a/llvm/test/CodeGen/RISCV/float-br-fcmp.ll b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
new file mode 100644
index 00000000000..c4924037911
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/float-br-fcmp.ll
@@ -0,0 +1,534 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IF %s
+
+declare void @abort()
+declare void @exit(i32)
+declare float @dummy(float)
+
+define void @br_fcmp_false(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_false:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    addi a0, zero, 1
+; RV32IF-NEXT:    bnez a0, .LBB0_2
+; RV32IF-NEXT:  # %bb.1: # %if.then
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB0_2: # %if.else
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp false float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.then:
+  ret void
+if.else:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_oeq(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_oeq:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    feq.s a0, ft1, ft0
+; RV32IF-NEXT:    bnez a0, .LBB1_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB1_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp oeq float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+; TODO: generated code quality for this is very poor due to
+; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
+; expansion.
+define void @br_fcmp_oeq_alt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_oeq_alt:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    feq.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    beqz a0, .LBB2_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB2_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp oeq float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.then:
+  tail call void @abort()
+  unreachable
+if.else:
+  ret void
+}
+
+define void @br_fcmp_ogt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ogt:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    flt.s a0, ft1, ft0
+; RV32IF-NEXT:    bnez a0, .LBB3_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB3_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp ogt float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_oge(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_oge:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fle.s a0, ft1, ft0
+; RV32IF-NEXT:    bnez a0, .LBB4_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB4_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp oge float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_olt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_olt:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    flt.s a0, ft1, ft0
+; RV32IF-NEXT:    bnez a0, .LBB5_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB5_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp olt float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_ole(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ole:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    fle.s a0, ft1, ft0
+; RV32IF-NEXT:    bnez a0, .LBB6_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB6_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp ole float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+; TODO: feq.s+sltiu+bne -> feq.s+beq
+define void @br_fcmp_one(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_one:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    feq.s a0, ft1, ft1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    and a0, a1, a0
+; RV32IF-NEXT:    feq.s a1, ft0, ft1
+; RV32IF-NEXT:    not a1, a1
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    and a0, a1, a0
+; RV32IF-NEXT:    bnez a0, .LBB7_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB7_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp one float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_ord(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ord:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    feq.s a0, ft0, ft0
+; RV32IF-NEXT:    and a0, a0, a1
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB8_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB8_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp ord float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_ueq(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ueq:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    feq.s a0, ft1, ft0
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    feq.s a2, ft1, ft1
+; RV32IF-NEXT:    and a1, a2, a1
+; RV32IF-NEXT:    seqz a1, a1
+; RV32IF-NEXT:    or a0, a0, a1
+; RV32IF-NEXT:    bnez a0, .LBB9_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB9_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp ueq float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_ugt(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ugt:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    fle.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB10_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB10_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp ugt float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_uge(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_uge:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    flt.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB11_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB11_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp uge float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_ult(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ult:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fle.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB12_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB12_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp ult float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_ule(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_ule:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    flt.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB13_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB13_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp ule float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_une(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_une:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    feq.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB14_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB14_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp une float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_uno(float %a, float %b) nounwind {
+; TODO: sltiu+bne -> beq
+; RV32IF-LABEL: br_fcmp_uno:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    feq.s a0, ft0, ft0
+; RV32IF-NEXT:    and a0, a0, a1
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    bnez a0, .LBB15_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB15_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp uno float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+define void @br_fcmp_true(float %a, float %b) nounwind {
+; RV32IF-LABEL: br_fcmp_true:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    addi a0, zero, 1
+; RV32IF-NEXT:    bnez a0, .LBB16_2
+; RV32IF-NEXT:  # %bb.1: # %if.else
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB16_2: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+  %1 = fcmp true float %a, %b
+  br i1 %1, label %if.then, label %if.else
+if.else:
+  ret void
+if.then:
+  tail call void @abort()
+  unreachable
+}
+
+; This test exists primarily to trigger RISCVInstrInfo::storeRegToStackSlot
+; and RISCVInstrInfo::loadRegFromStackSlot
+define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
+; TODO: addi %lo(.LCPI17_0) should be merged in to the following flw
+; RV32IF-LABEL: br_fcmp_store_load_stack_slot:
+; RV32IF:       # %bb.0: # %entry
+; RV32IF-NEXT:    addi sp, sp, -16
+; RV32IF-NEXT:    sw ra, 12(sp)
+; RV32IF-NEXT:    sw s1, 8(sp)
+; RV32IF-NEXT:    lui a0, %hi(dummy)
+; RV32IF-NEXT:    addi s1, a0, %lo(dummy)
+; RV32IF-NEXT:    mv a0, zero
+; RV32IF-NEXT:    jalr s1
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    lui a0, %hi(.LCPI17_0)
+; RV32IF-NEXT:    addi a0, a0, %lo(.LCPI17_0)
+; RV32IF-NEXT:    flw ft1, 0(a0)
+; RV32IF-NEXT:    fsw ft1, 4(sp)
+; RV32IF-NEXT:    feq.s a0, ft0, ft1
+; RV32IF-NEXT:    beqz a0, .LBB17_3
+; RV32IF-NEXT:  # %bb.1: # %if.end
+; RV32IF-NEXT:    mv a0, zero
+; RV32IF-NEXT:    jalr s1
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    flw ft1, 4(sp)
+; RV32IF-NEXT:    feq.s a0, ft0, ft1
+; RV32IF-NEXT:    beqz a0, .LBB17_3
+; RV32IF-NEXT:  # %bb.2: # %if.end4
+; RV32IF-NEXT:    mv a0, zero
+; RV32IF-NEXT:    lw s1, 8(sp)
+; RV32IF-NEXT:    lw ra, 12(sp)
+; RV32IF-NEXT:    addi sp, sp, 16
+; RV32IF-NEXT:    ret
+; RV32IF-NEXT:  .LBB17_3: # %if.then
+; RV32IF-NEXT:    lui a0, %hi(abort)
+; RV32IF-NEXT:    addi a0, a0, %lo(abort)
+; RV32IF-NEXT:    jalr a0
+entry:
+  %call = call float @dummy(float 0.000000e+00)
+  %cmp = fcmp une float %call, 0.000000e+00
+  br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+  call void @abort()
+  unreachable
+
+if.end:
+  %call1 = call float @dummy(float 0.000000e+00)
+  %cmp2 = fcmp une float %call1, 0.000000e+00
+  br i1 %cmp2, label %if.then3, label %if.end4
+
+if.then3:
+  call void @abort()
+  unreachable
+
+if.end4:
+  ret i32 0
+}
diff --git a/llvm/test/CodeGen/RISCV/float-fcmp.ll b/llvm/test/CodeGen/RISCV/float-fcmp.ll
new file mode 100644
index 00000000000..c8942a90eb7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/float-fcmp.ll
@@ -0,0 +1,215 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IF %s
+
+define i32 @fcmp_false(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_false:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    mv a0, zero
+; RV32IF-NEXT:    ret
+  %1 = fcmp false float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_oeq(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_oeq:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    feq.s a0, ft1, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp oeq float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ogt(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ogt:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    flt.s a0, ft1, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp ogt float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_oge(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_oge:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fle.s a0, ft1, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp oge float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_olt(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_olt:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    flt.s a0, ft1, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp olt float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ole(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ole:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    fle.s a0, ft1, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp ole float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_one(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_one:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    feq.s a0, ft1, ft1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    and a0, a1, a0
+; RV32IF-NEXT:    feq.s a1, ft0, ft1
+; RV32IF-NEXT:    not a1, a1
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    and a0, a1, a0
+; RV32IF-NEXT:    ret
+  %1 = fcmp one float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ord(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ord:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    feq.s a0, ft0, ft0
+; RV32IF-NEXT:    and a0, a0, a1
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    ret
+  %1 = fcmp ord float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ueq(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ueq:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    feq.s a0, ft1, ft0
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    feq.s a2, ft1, ft1
+; RV32IF-NEXT:    and a1, a2, a1
+; RV32IF-NEXT:    seqz a1, a1
+; RV32IF-NEXT:    or a0, a0, a1
+; RV32IF-NEXT:    ret
+  %1 = fcmp ueq float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ugt(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ugt:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    fle.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    ret
+  %1 = fcmp ugt float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_uge(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_uge:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    flt.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    ret
+  %1 = fcmp uge float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ult(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ult:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fle.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    ret
+  %1 = fcmp ult float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ule(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_ule:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    flt.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    ret
+  %1 = fcmp ule float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_une(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_une:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    feq.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    ret
+  %1 = fcmp une float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_uno(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_uno:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    feq.s a0, ft0, ft0
+; RV32IF-NEXT:    and a0, a0, a1
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    ret
+  %1 = fcmp uno float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_true(float %a, float %b) nounwind {
+; RV32IF-LABEL: fcmp_true:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    addi a0, zero, 1
+; RV32IF-NEXT:    ret
+  %1 = fcmp true float %a, %b
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
diff --git a/llvm/test/CodeGen/RISCV/float-select-fcmp.ll b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
new file mode 100644
index 00000000000..59d4a3f078b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/float-select-fcmp.ll
@@ -0,0 +1,304 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
+; RUN:   | FileCheck -check-prefix=RV32IF %s
+
+define float @select_fcmp_false(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_false:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    mv a0, a1
+; RV32IF-NEXT:    ret
+  %1 = fcmp false float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_oeq(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_oeq:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    feq.s a0, ft0, ft1
+; RV32IF-NEXT:    bnez a0, .LBB1_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB1_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp oeq float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_ogt(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ogt:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    flt.s a0, ft1, ft0
+; RV32IF-NEXT:    bnez a0, .LBB2_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB2_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp ogt float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_oge(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_oge:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fle.s a0, ft1, ft0
+; RV32IF-NEXT:    bnez a0, .LBB3_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB3_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp oge float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_olt(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_olt:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    flt.s a0, ft0, ft1
+; RV32IF-NEXT:    bnez a0, .LBB4_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB4_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp olt float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_ole(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ole:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fle.s a0, ft0, ft1
+; RV32IF-NEXT:    bnez a0, .LBB5_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB5_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp ole float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_one(float %a, float %b) nounwind {
+; TODO: feq.s+sltiu+bne sequence could be optimised
+; RV32IF-LABEL: select_fcmp_one:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    feq.s a0, ft1, ft1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    and a0, a1, a0
+; RV32IF-NEXT:    feq.s a1, ft0, ft1
+; RV32IF-NEXT:    not a1, a1
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    and a0, a1, a0
+; RV32IF-NEXT:    bnez a0, .LBB6_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB6_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp one float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_ord(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ord:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    feq.s a0, ft1, ft1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    and a0, a1, a0
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB7_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB7_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp ord float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_ueq(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ueq:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    feq.s a0, ft1, ft1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    and a0, a1, a0
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    feq.s a1, ft0, ft1
+; RV32IF-NEXT:    or a0, a1, a0
+; RV32IF-NEXT:    bnez a0, .LBB8_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB8_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp ueq float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_ugt(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ugt:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fle.s a0, ft0, ft1
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB9_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB9_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp ugt float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_uge(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_uge:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    flt.s a0, ft0, ft1
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB10_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB10_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp uge float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_ult(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ult:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fle.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB11_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB11_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp ult float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_ule(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_ule:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    flt.s a0, ft1, ft0
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB12_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB12_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp ule float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_une(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_une:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    feq.s a0, ft0, ft1
+; RV32IF-NEXT:    xori a0, a0, 1
+; RV32IF-NEXT:    bnez a0, .LBB13_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB13_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp une float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_uno(float %a, float %b) nounwind {
+; TODO: sltiu+bne could be optimized
+; RV32IF-LABEL: select_fcmp_uno:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a0
+; RV32IF-NEXT:    fmv.w.x ft1, a1
+; RV32IF-NEXT:    feq.s a0, ft1, ft1
+; RV32IF-NEXT:    feq.s a1, ft0, ft0
+; RV32IF-NEXT:    and a0, a1, a0
+; RV32IF-NEXT:    seqz a0, a0
+; RV32IF-NEXT:    bnez a0, .LBB14_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    fmv.s ft0, ft1
+; RV32IF-NEXT:  .LBB14_2:
+; RV32IF-NEXT:    fmv.x.w a0, ft0
+; RV32IF-NEXT:    ret
+  %1 = fcmp uno float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+define float @select_fcmp_true(float %a, float %b) nounwind {
+; RV32IF-LABEL: select_fcmp_true:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    ret
+  %1 = fcmp true float %a, %b
+  %2 = select i1 %1, float %a, float %b
+  ret float %2
+}
+
+; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
+define i32 @i32_select_fcmp_oeq(float %a, float %b, i32 %c, i32 %d) nounwind {
+; RV32IF-LABEL: i32_select_fcmp_oeq:
+; RV32IF:       # %bb.0:
+; RV32IF-NEXT:    fmv.w.x ft0, a1
+; RV32IF-NEXT:    fmv.w.x ft1, a0
+; RV32IF-NEXT:    feq.s a0, ft1, ft0
+; RV32IF-NEXT:    bnez a0, .LBB16_2
+; RV32IF-NEXT:  # %bb.1:
+; RV32IF-NEXT:    mv a2, a3
+; RV32IF-NEXT:  .LBB16_2:
+; RV32IF-NEXT:    mv a0, a2
+; RV32IF-NEXT:    ret
+  %1 = fcmp oeq float %a, %b
+  %2 = select i1 %1, i32 %c, i32 %d
+  ret i32 %2
+}