diff options
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 8 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir | 29 |
2 files changed, 37 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll index 0194fa058e2..e40199d82c9 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll @@ -71,6 +71,14 @@ define void @odd_type(i42* %addr) { ret void } +; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: %vreg1<def>(<7 x s32>) = G_LOAD %vreg0; mem:LD28[%addr](align=32) (in function: odd_vector) +; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for odd_vector +; FALLBACK-WITH-REPORT-OUT-LABEL: odd_vector: +define void @odd_vector(<7 x i32>* %addr) { + %vec = load <7 x i32>, <7 x i32>* %addr + ret void +} + ; RegBankSelect crashed when given invalid mappings, and AArch64's ; implementation produce valid-but-nonsense mappings for G_SEQUENCE. ; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to map instruction diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir new file mode 100644 index 00000000000..9928ea54d2c --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-nonpowerof2eltsvec.mir @@ -0,0 +1,29 @@ +# RUN: llc -O0 -run-pass=legalizer -global-isel %s -o - | FileCheck %s + +--- | + target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + target triple = "aarch64--" + define void @test_legalize_merge_v3s32() { + ret void + } +... +--- +name: test_legalize_merge_v3s32 +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } + - { id: 3, class: _ } +body: | + bb.0: + liveins: %w0, %w1, %w2 + ; CHECK-LABEL: name: test_legalize_merge_v3s32 + ; CHECK: [[ARG1:%[0-9]+]](s32) = COPY %w0 + ; CHECK: [[ARG2:%[0-9]+]](s32) = COPY %w1 + ; CHECK: [[ARG3:%[0-9]+]](s32) = COPY %w2 + ; CHECK: (<3 x s32>) = G_MERGE_VALUES [[ARG1]](s32), [[ARG2]](s32), [[ARG3]](s32) + %0(s32) = COPY %w0 + %1(s32) = COPY %w1 + %2(s32) = COPY %w2 + %3(<3 x s32>) = G_MERGE_VALUES %0(s32), %1(s32), %2(s32) +... |
