diff options
Diffstat (limited to 'llvm/test')
13 files changed, 327 insertions, 102 deletions
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll index 57b826452ef..213833c56fc 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll @@ -1622,9 +1622,7 @@ define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) { ; CHECK-LABEL: name: test_shufflevector_s32_v2s32 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $w0 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF -; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 -; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C0]](s32), [[C0]](s32) -; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>) +; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], shufflemask(0, 0) ; CHECK: $d0 = COPY [[VEC]](<2 x s32>) %vec = insertelement <1 x i32> undef, i32 %arg, i32 0 %res = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer @@ -1634,25 +1632,40 @@ define <2 x i32> @test_shufflevector_s32_v2s32(i32 %arg) { define i32 @test_shufflevector_v2s32_s32(<2 x i32> %arg) { ; CHECK-LABEL: name: test_shufflevector_v2s32_s32 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0 -; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF -; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 -; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[C1]](s32) +; CHECK: [[RES:%[0-9]+]]:_(s32) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(1) ; CHECK: $w0 = COPY [[RES]](s32) %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <1 x i32> <i32 1> %res = extractelement <1 x i32> %vec, i32 0 ret i32 %res } -define <2 x i32> @test_shufflevector_v2s32_v2s32(<2 x i32> %arg) { -; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32 +define <2 x i32> @test_shufflevector_v2s32_v2s32_undef(<2 x i32> %arg) { +; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_undef +; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0 +; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF +; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(undef, undef) +; CHECK: $d0 = COPY [[VEC]](<2 x s32>) + %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> undef + ret <2 x i32> %res +} + +define <2 x i32> @test_shufflevector_v2s32_v2s32_undef_0(<2 x i32> %arg) { +; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_undef_0 +; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0 +; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF +; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(undef, 0) +; CHECK: $d0 = COPY [[VEC]](<2 x s32>) + %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 undef, i32 0> + ret <2 x i32> %res +} + +define <2 x i32> @test_shufflevector_v2s32_v2s32_0_undef(<2 x i32> %arg) { +; CHECK-LABEL: name: test_shufflevector_v2s32_v2s32_0_undef ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF -; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 -; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 -; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C0]](s32) -; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<2 x s32>) +; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(0, undef) ; CHECK: $d0 = COPY [[VEC]](<2 x s32>) - %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 1, i32 0> + %res = shufflevector <2 x i32> %arg, <2 x i32> undef, <2 x i32> <i32 0, i32 undef> ret <2 x i32> %res } @@ -1660,10 +1673,7 @@ define i32 @test_shufflevector_v2s32_v3s32(<2 x i32> %arg) { ; CHECK-LABEL: name: test_shufflevector_v2s32_v3s32 ; CHECK: [[ARG:%[0-9]+]]:_(<2 x s32>) = COPY $d0 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF -; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 -; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 -; CHECK-DAG: [[MASK:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C0]](s32), [[C1]](s32) -; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>) +; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<2 x s32>), [[UNDEF]], shufflemask(1, 0, 1) ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>) %vec = shufflevector <2 x i32> %arg, <2 x i32> undef, <3 x i32> <i32 1, i32 0, i32 1> %res = extractelement <3 x i32> %vec, i32 0 @@ -1674,12 +1684,7 @@ define <4 x i32> @test_shufflevector_v2s32_v4s32(<2 x i32> %arg1, <2 x i32> %arg ; CHECK-LABEL: name: test_shufflevector_v2s32_v4s32 ; CHECK: [[ARG1:%[0-9]+]]:_(<2 x s32>) = COPY $d0 ; CHECK: [[ARG2:%[0-9]+]]:_(<2 x s32>) = COPY $d1 -; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 -; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 -; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 -; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 -; CHECK: [[MASK:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C0]](s32), [[C1]](s32), [[C2]](s32), [[C3]](s32) -; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], [[MASK]](<4 x s32>) +; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[ARG1]](<2 x s32>), [[ARG2]], shufflemask(0, 1, 2, 3) ; CHECK: $q0 = COPY [[VEC]](<4 x s32>) %res = shufflevector <2 x i32> %arg1, <2 x i32> %arg2, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ret <4 x i32> %res @@ -1689,10 +1694,7 @@ define <2 x i32> @test_shufflevector_v4s32_v2s32(<4 x i32> %arg) { ; CHECK-LABEL: name: test_shufflevector_v4s32_v2s32 ; CHECK: [[ARG:%[0-9]+]]:_(<4 x s32>) = COPY $q0 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF -; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 -; CHECK-DAG: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 -; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C3]](s32) -; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>) +; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](<4 x s32>), [[UNDEF]], shufflemask(1, 3) ; CHECK: $d0 = COPY [[VEC]](<2 x s32>) %res = shufflevector <4 x i32> %arg, <4 x i32> undef, <2 x i32> <i32 1, i32 3> ret <2 x i32> %res @@ -1703,24 +1705,7 @@ define <16 x i8> @test_shufflevector_v8s8_v16s8(<8 x i8> %arg1, <8 x i8> %arg2) ; CHECK-LABEL: name: test_shufflevector_v8s8_v16s8 ; CHECK: [[ARG1:%[0-9]+]]:_(<8 x s8>) = COPY $d0 ; CHECK: [[ARG2:%[0-9]+]]:_(<8 x s8>) = COPY $d1 -; CHECK: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 -; CHECK: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 -; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 -; CHECK: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 9 -; CHECK: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 -; CHECK: [[C10:%[0-9]+]]:_(s32) = G_CONSTANT i32 10 -; CHECK: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 -; CHECK: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 11 -; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 -; CHECK: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 12 -; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 5 -; CHECK: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 13 -; CHECK: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 6 -; CHECK: [[C14:%[0-9]+]]:_(s32) = G_CONSTANT i32 14 -; CHECK: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 7 -; CHECK: [[C15:%[0-9]+]]:_(s32) = G_CONSTANT i32 15 -; CHECK: [[MASK:%[0-9]+]]:_(<16 x s32>) = G_BUILD_VECTOR [[C0]](s32), [[C8]](s32), [[C1]](s32), [[C9]](s32), [[C2]](s32), [[C10]](s32), [[C3]](s32), [[C11]](s32), [[C4]](s32), [[C12]](s32), [[C5]](s32), [[C13]](s32), [[C6]](s32), [[C14]](s32), [[C7]](s32), [[C15]](s32) -; CHECK: [[VEC:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], [[MASK]](<16 x s32>) +; CHECK: [[VEC:%[0-9]+]]:_(<16 x s8>) = G_SHUFFLE_VECTOR [[ARG1]](<8 x s8>), [[ARG2]], shufflemask(0, 8, 1, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15) ; CHECK: $q0 = COPY [[VEC]](<16 x s8>) %res = shufflevector <8 x i8> %arg1, <8 x i8> %arg2, <16 x i32> <i32 0, i32 8, i32 1, i32 9, i32 2, i32 10, i32 3, i32 11, i32 4, i32 12, i32 5, i32 13, i32 6, i32 14, i32 7, i32 15> ret <16 x i8> %res diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir index 4dbaae13a7b..73872091aff 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir @@ -12,16 +12,12 @@ body: | ; CHECK: liveins: $q0, $q1 ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) - ; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], [[BUILD_VECTOR]](<4 x s32>) + ; CHECK: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[COPY1]], shufflemask(0, 0, 0, 0) ; CHECK: $q0 = COPY [[SHUF]](<4 x s32>) ; CHECK: RET_ReallyLR implicit $q0 %0:_(<4 x s32>) = COPY $q0 %1:_(<4 x s32>) = COPY $q1 - %4:_(s32) = G_CONSTANT i32 0 - %3:_(<4 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32), %4(s32), %4(s32) - %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>) + %2:_(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 0, 0, 0) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -38,16 +34,12 @@ body: | ; CHECK: liveins: $q0, $q1 ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 - ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 - ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32) - ; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[COPY1]], [[BUILD_VECTOR]](<2 x s32>) + ; CHECK: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s64>), [[COPY1]], shufflemask(0, 0) ; CHECK: $q0 = COPY [[SHUF]](<2 x s64>) ; CHECK: RET_ReallyLR implicit $q0 %0:_(<2 x s64>) = COPY $q0 %1:_(<2 x s64>) = COPY $q1 - %4:_(s32) = G_CONSTANT i32 0 - %3:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32) - %2:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, %3(<2 x s32>) + %2:_(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(0, 0) $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir index a6cf1d6fd81..452c2158080 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir @@ -424,7 +424,7 @@ # DEBUG-NEXT: G_EXTRACT_VECTOR_ELT (opcode {{[0-9]+}}): 3 type indices, 0 imm indices # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected -# DEBUG-NEXT: G_SHUFFLE_VECTOR (opcode {{[0-9]+}}): 3 type indices, 0 imm indices +# DEBUG-NEXT: G_SHUFFLE_VECTOR (opcode {{[0-9]+}}): 2 type indices, 0 imm indices # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected # DEBUG-NEXT: G_CTTZ (opcode {{[0-9]+}}): 2 type indices, 0 imm indices diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir b/llvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir index b62f569dc4d..bb8f6a775eb 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/opt-shuffle-splat.mir @@ -19,9 +19,8 @@ body: | %0:gpr(s32) = COPY $w0 %2:fpr(<4 x s32>) = G_IMPLICIT_DEF %3:gpr(s32) = G_CONSTANT i32 0 - %5:fpr(<4 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32), %3(s32), %3(s32) %1:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) - %4:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, %5(<4 x s32>) + %4:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 @@ -45,9 +44,8 @@ body: | %0:gpr(s64) = COPY $x0 %2:fpr(<2 x s64>) = G_IMPLICIT_DEF %3:gpr(s32) = G_CONSTANT i32 0 - %5:fpr(<2 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32) %1:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) - %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, %5(<2 x s32>) + %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -73,9 +71,8 @@ body: | %0:fpr(s32) = COPY $s0 %2:fpr(<4 x s32>) = G_IMPLICIT_DEF %3:gpr(s32) = G_CONSTANT i32 0 - %5:fpr(<4 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32), %3(s32), %3(s32) %1:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %2, %0(s32), %3(s32) - %4:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, %5(<4 x s32>) + %4:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %1(<4 x s32>), %2, shufflemask(0, 0, 0, 0) $q0 = COPY %4(<4 x s32>) RET_ReallyLR implicit $q0 @@ -101,9 +98,8 @@ body: | %0:fpr(s64) = COPY $d0 %2:fpr(<2 x s64>) = G_IMPLICIT_DEF %3:gpr(s32) = G_CONSTANT i32 0 - %5:fpr(<2 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32) %1:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) - %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, %5(<2 x s32>) + %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 0) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -132,10 +128,9 @@ body: | %2:fpr(<2 x s64>) = G_IMPLICIT_DEF %6:fpr(<2 x s64>) = COPY %2 %3:gpr(s32) = G_CONSTANT i32 0 - %5:fpr(<2 x s32>) = G_BUILD_VECTOR %3(s32), %3(s32) %1:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %6, %0(s64), %3(s32) %7:fpr(<2 x s64>) = COPY %1 - %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %7(<2 x s64>), %2, %5(<2 x s32>) + %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %7(<2 x s64>), %2, shufflemask(0, 0) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 @@ -164,9 +159,7 @@ body: | %0:gpr(s64) = COPY $x0 %2:fpr(<2 x s64>) = G_IMPLICIT_DEF %3:gpr(s32) = G_CONSTANT i32 0 - %6:gpr(s32) = G_CONSTANT i32 1 - %5:fpr(<2 x s32>) = G_BUILD_VECTOR %3(s32), %6(s32) %1:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %2, %0(s64), %3(s32) - %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, %5(<2 x s32>) + %4:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %1(<2 x s64>), %2, shufflemask(0, 1) $q0 = COPY %4(<2 x s64>) RET_ReallyLR implicit $q0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir index 20f3c38005d..aeb618d0c46 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-shuffle-vector.mir @@ -61,10 +61,7 @@ body: | ; CHECK: RET_ReallyLR implicit $d0 %0:fpr(<2 x s32>) = COPY $d0 %1:fpr(<2 x s32>) = COPY $d1 - %4:gpr(s32) = G_CONSTANT i32 1 - %5:gpr(s32) = G_CONSTANT i32 0 - %3:fpr(<2 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32) - %2:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, %3(<2 x s32>) + %2:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 0) $d0 = COPY %2(<2 x s32>) RET_ReallyLR implicit $d0 @@ -95,11 +92,7 @@ body: | ; CHECK: RET_ReallyLR implicit $q0 %0:fpr(<4 x s32>) = COPY $q0 %1:fpr(<4 x s32>) = COPY $q1 - %4:gpr(s32) = G_CONSTANT i32 0 - %5:gpr(s32) = G_CONSTANT i32 1 - %6:gpr(s32) = G_CONSTANT i32 3 - %3:fpr(<4 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32), %6(s32), %4(s32) - %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>) + %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(0, 1, 3, 0) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -130,12 +123,7 @@ body: | ; CHECK: RET_ReallyLR implicit $q0 %0:fpr(<4 x s32>) = COPY $q0 %1:fpr(<4 x s32>) = COPY $q1 - %4:gpr(s32) = G_CONSTANT i32 5 - %5:gpr(s32) = G_CONSTANT i32 7 - %6:gpr(s32) = G_CONSTANT i32 1 - %7:gpr(s32) = G_CONSTANT i32 0 - %3:fpr(<4 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32), %6(s32), %7(s32) - %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, %3(<4 x s32>) + %2:fpr(<4 x s32>) = G_SHUFFLE_VECTOR %0(<4 x s32>), %1, shufflemask(5, 7, 1, 0) $q0 = COPY %2(<4 x s32>) RET_ReallyLR implicit $q0 @@ -166,9 +154,7 @@ body: | ; CHECK: RET_ReallyLR implicit $q0 %0:fpr(<2 x s64>) = COPY $q0 %1:fpr(<2 x s64>) = COPY $q1 - %4:gpr(s32) = G_CONSTANT i32 0 - %3:fpr(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32) - %2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, %3(<2 x s32>) + %2:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %0(<2 x s64>), %1, shufflemask(0, 0) $q0 = COPY %2(<2 x s64>) RET_ReallyLR implicit $q0 diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir index 7a973b8804e..b3836579893 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-shufflevec-undef-mask-elt.mir @@ -41,10 +41,7 @@ body: | %6:gpr(s32) = G_IMPLICIT_DEF %7:gpr(s32) = G_IMPLICIT_DEF %2:fpr(<2 x s32>) = G_BUILD_VECTOR %6(s32), %7(s32) - %4:gpr(s32) = G_CONSTANT i32 1 - %5:gpr(s32) = G_IMPLICIT_DEF - %3:fpr(<2 x s32>) = G_BUILD_VECTOR %4(s32), %5(s32) - %1:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, %3(<2 x s32>) + %1:fpr(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1, undef) $d0 = COPY %1(<2 x s32>) RET_ReallyLR implicit $d0 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll index 2677a4cfdb5..5c9fbf1fe21 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll @@ -438,9 +438,7 @@ define i32 @test_shufflevector_s32_v2s32(i32 %arg) { ; CHECK-LABEL: name: test_shufflevector_s32_v2s32 ; CHECK: [[ARG:%[0-9]+]]:_(s32) = COPY $r0 ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF -; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 -; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C0]](s32), [[C0]](s32) -; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], [[MASK]](<2 x s32>) +; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[ARG]](s32), [[UNDEF]], shufflemask(0, 0) ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>) %vec = insertelement <1 x i32> undef, i32 %arg, i32 0 %shuffle = shufflevector <1 x i32> %vec, <1 x i32> undef, <2 x i32> zeroinitializer @@ -455,10 +453,9 @@ define i32 @test_shufflevector_v2s32_v3s32(i32 %arg1, i32 %arg2) { ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF ; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 -; CHECK-DAG: [[MASK:%[0-9]+]]:_(<3 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C0]](s32), [[C1]](s32) ; CHECK-DAG: [[V1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32) ; CHECK-DAG: [[V2:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32) -; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], [[MASK]](<3 x s32>) +; CHECK: [[VEC:%[0-9]+]]:_(<3 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], shufflemask(1, 0, 1) ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<3 x s32>) %v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0 %v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1 @@ -475,10 +472,9 @@ define i32 @test_shufflevector_v2s32_v4s32(i32 %arg1, i32 %arg2) { ; CHECK-DAG: [[UNDEF:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF ; CHECK-DAG: [[C0:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 -; CHECK-DAG: [[MASK:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C0]](s32), [[C0]](s32), [[C0]](s32), [[C0]](s32) ; CHECK-DAG: [[V1:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32) ; CHECK-DAG: [[V2:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32) -; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], [[MASK]](<4 x s32>) +; CHECK: [[VEC:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[V2]](<2 x s32>), [[UNDEF]], shufflemask(0, 0, 0, 0) ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<4 x s32>) %v1 = insertelement <2 x i32> undef, i32 %arg1, i32 0 %v2 = insertelement <2 x i32> %v1, i32 %arg2, i32 1 @@ -498,12 +494,11 @@ define i32 @test_shufflevector_v4s32_v2s32(i32 %arg1, i32 %arg2, i32 %arg3, i32 ; CHECK-DAG: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 ; CHECK-DAG: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 ; CHECK-DAG: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 -; CHECK-DAG: [[MASK:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C3]](s32) ; CHECK-DAG: [[V1:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[UNDEF]], [[ARG1]](s32), [[C0]](s32) ; CHECK-DAG: [[V2:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V1]], [[ARG2]](s32), [[C1]](s32) ; CHECK-DAG: [[V3:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V2]], [[ARG3]](s32), [[C2]](s32) ; CHECK-DAG: [[V4:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[V3]], [[ARG4]](s32), [[C3]](s32) -; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[V4]](<4 x s32>), [[UNDEF]], [[MASK]](<2 x s32>) +; CHECK: [[VEC:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[V4]](<4 x s32>), [[UNDEF]], shufflemask(1, 3) ; CHECK: G_EXTRACT_VECTOR_ELT [[VEC]](<2 x s32>) %v1 = insertelement <4 x i32> undef, i32 %arg1, i32 0 %v2 = insertelement <4 x i32> %v1, i32 %arg2, i32 1 diff --git a/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid0.mir b/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid0.mir new file mode 100644 index 00000000000..9a8f94f754d --- /dev/null +++ b/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid0.mir @@ -0,0 +1,19 @@ +# RUN: not llc -mtriple=aarch64-- -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s + +--- +name: test_missing_comma +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + + ; FIXME: Not ideal error + ; CHECK: [[@LINE+1]]:73: shufflemask should be terminated by ')'. + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1 0) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... diff --git a/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid1.mir b/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid1.mir new file mode 100644 index 00000000000..3b82de57bf6 --- /dev/null +++ b/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid1.mir @@ -0,0 +1,18 @@ +# RUN: not llc -mtriple=aarch64-- -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s + +--- +name: test_missing_lparen +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + + ; CHECK: [[@LINE+1]]:71: expected syntax shufflemask(<integer or undef>, ...) + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask 1, 0) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... diff --git a/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid2.mir b/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid2.mir new file mode 100644 index 00000000000..5d3d62f119e --- /dev/null +++ b/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid2.mir @@ -0,0 +1,18 @@ +# RUN: not llc -mtriple=aarch64-- -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s + +--- +name: test_missing_rparen +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + + ; CHECK: [[@LINE+1]]:75: shufflemask should be terminated by ')'. + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1, 0 + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... diff --git a/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid3.mir b/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid3.mir new file mode 100644 index 00000000000..95b7cfc27d9 --- /dev/null +++ b/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask-invalid3.mir @@ -0,0 +1,18 @@ +# RUN: not llc -mtriple=aarch64-- -run-pass=none -o /dev/null %s 2>&1 | FileCheck %s + +--- +name: test_not_integer +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + + ; CHECK: [[@LINE+1]]:74: expected integer constant + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1, arst) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... diff --git a/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask.mir b/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask.mir new file mode 100644 index 00000000000..4d9cce2945c --- /dev/null +++ b/llvm/test/CodeGen/MIR/AArch64/parse-shufflemask.mir @@ -0,0 +1,175 @@ +# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s +# This test ensures that the MIR parser parses shufflemask correctly + +# CHECK-LABEL: name: test_shuffle_1_0 +# CHECK: G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 0) +--- +name: test_shuffle_1_0 +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1, 0) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... + +# CHECK-LABEL: name: test_shuffle_nospace +# CHECK: G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 0) +--- +name: test_shuffle_nospace +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1,0) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... + +# CHECK-LABEL: name: test_shuffle_0_0 +# CHECK: G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(0, 0) +--- +name: test_shuffle_0_0 +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(0, 0) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... + +# CHECK-LABEL: name: test_shuffle_1_1 +# CHECK: G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1, 1) +--- +name: test_shuffle_1_1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1, 1) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... + +# CHECK-LABEL: name: test_shuffle_undef_undef +# CHECK: G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(undef, undef) + +--- +name: test_shuffle_undef_undef +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(undef, undef) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... + +# CHECK-LABEL: name: test_shuffle_undef_0 +# CHECK: G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(undef, 0) + +--- +name: test_shuffle_undef_0 +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(undef, 0) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... + +# CHECK-LABEL: name: test_shuffle_0_undef +# CHECK: G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(0, undef) + +--- +name: test_shuffle_0_undef +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(0, undef) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... + +# CHECK-LABEL: name: test_shuffle_0 +# CHECK: G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(0) +--- +name: test_shuffle_0 +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(0) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... + +# CHECK-LABEL: name: test_shuffle_1 +# CHECK: G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(1) +--- +name: test_shuffle_1 +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(1) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... + +# CHECK-LABEL: name: test_shuffle_undef +# CHECK: G_SHUFFLE_VECTOR %0(<2 x s32>), %1, shufflemask(undef) +--- +name: test_shuffle_undef +tracksRegLiveness: true +body: | + bb.0: + liveins: $d0 + + %0:_(<2 x s32>) = COPY $d0 + %2:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_SHUFFLE_VECTOR %0(<2 x s32>), %2, shufflemask(undef) + $d0 = COPY %1(<2 x s32>) + RET_ReallyLR implicit $d0 + +... diff --git a/llvm/test/MachineVerifier/test_g_shuffle_vector.mir b/llvm/test/MachineVerifier/test_g_shuffle_vector.mir new file mode 100644 index 00000000000..3c97f532b42 --- /dev/null +++ b/llvm/test/MachineVerifier/test_g_shuffle_vector.mir @@ -0,0 +1,29 @@ +# RUN: not llc -o - -march=arm64 -global-isel -run-pass=none -verify-machineinstrs %s 2>&1 | FileCheck %s +# REQUIRES: aarch64-registered-target +--- +name: g_shuffle_vector +tracksRegLiveness: true +liveins: +body: | + bb.0: + %0:_(<2 x s32>) = G_IMPLICIT_DEF + %1:_(<2 x s32>) = G_IMPLICIT_DEF + %2:_(<4 x s32>) = G_IMPLICIT_DEF + + %3:_(s32) = G_CONSTANT i32 0 + %4:_(s32) = G_CONSTANT i32 1 + %5:_(<2 x s32>) = G_BUILD_VECTOR %3, %4 + + ; CHECK: Bad machine code: Incorrect mask operand type for G_SHUFFLE_VECTOR + %6:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, %2 + + ; CHECK: Bad machine code: Incorrect mask operand type for G_SHUFFLE_VECTOR + %7:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, %5 + + ; CHECK: Bad machine code: Incorrect mask operand type for G_SHUFFLE_VECTOR + %8:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, 0 + + ; CHECK: Bad machine code: Incorrect mask operand type for G_SHUFFLE_VECTOR + %9:_(<4 x s32>) = G_SHUFFLE_VECTOR %0, %1, i32 0 + +... |
