diff options
Diffstat (limited to 'llvm/test')
5 files changed, 39 insertions, 32 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.init.exec.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.init.exec.ll new file mode 100644 index 00000000000..77c2f80ac02 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.init.exec.ll @@ -0,0 +1,2 @@ +; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %S/../llvm.amdgcn.init.exec.ll | FileCheck -check-prefix=GCN %S/../llvm.amdgcn.init.exec.ll +; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %S/../llvm.amdgcn.init.exec.ll | FileCheck -check-prefix=GCN %S/../llvm.amdgcn.init.exec.ll diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.init.exec.wave32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.init.exec.wave32.ll new file mode 100644 index 00000000000..1e8fce0e34f --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.init.exec.wave32.ll @@ -0,0 +1,2 @@ +; Runs original SDAG test with -global-isel +; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %S/../llvm.amdgcn.init.exec.wave32.ll | FileCheck -check-prefixes=GCN,GFX1032 %S/../llvm.amdgcn.init.exec.wave32.ll diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll index fb79ba8ae4a..f3998d9a899 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.ll @@ -1,4 +1,5 @@ -;RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s --check-prefix=GCN +; RUN: llc < %s -march=amdgcn -mcpu=gfx900 -verify-machineinstrs | FileCheck %s --check-prefix=GCN +; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-wavefrontsize32,+wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; GCN-LABEL: {{^}}full_mask: ; GCN: s_mov_b64 exec, -1 @@ -51,7 +52,7 @@ main_body: ; GCN: s_bfm_b64 exec, s1, 0 ; GCN: s_cmp_eq_u32 s1, 64 ; GCN: s_cmov_b64 exec, -1 -; GCN: v_add_u32_e32 v0, s0, v0 +; GCN: v_add{{(_nc)?}}_u32_e32 v0, s0, v0 define amdgpu_ps float @reuse_input(i32 inreg %count, i32 %a) { main_body: call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 19) @@ -65,7 +66,7 @@ main_body: ; GCN: s_bfm_b64 exec, s1, 0 ; GCN: s_cmp_eq_u32 s1, 64 ; GCN: s_cmov_b64 exec, -1 -; GCN: v_add_u32_e32 v0, s0, v0 +; GCN: v_add{{(_nc)?}}_u32_e32 v0, s0, v0 define amdgpu_ps float @reuse_input2(i32 inreg %count, i32 %a) { main_body: %s = add i32 %a, %count diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll new file mode 100644 index 00000000000..3c66f6e01b4 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.init.exec.wave32.ll @@ -0,0 +1,31 @@ +; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX1032 %s + +; GCN-LABEL: {{^}}test_init_exec: +; GFX1032: s_mov_b32 exec_lo, 0x12345 +; GFX1064: s_mov_b64 exec, 0x12345 +; GCN: v_add_f32_e32 v0, +define amdgpu_ps float @test_init_exec(float %a, float %b) { +main_body: + %s = fadd float %a, %b + call void @llvm.amdgcn.init.exec(i64 74565) + ret float %s +} + +; GCN-LABEL: {{^}}test_init_exec_from_input: +; GCN: s_bfe_u32 s0, s3, 0x70008 +; GFX1032: s_bfm_b32 exec_lo, s0, 0 +; GFX1032: s_cmp_eq_u32 s0, 32 +; GFX1032: s_cmov_b32 exec_lo, -1 +; GFX1064: s_bfm_b64 exec, s0, 0 +; GFX1064: s_cmp_eq_u32 s0, 64 +; GFX1064: s_cmov_b64 exec, -1 +; GCN: v_add_f32_e32 v0, +define amdgpu_ps float @test_init_exec_from_input(i32 inreg, i32 inreg, i32 inreg, i32 inreg %count, float %a, float %b) { +main_body: + %s = fadd float %a, %b + call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 8) + ret float %s +} + +declare void @llvm.amdgcn.init.exec(i64) +declare void @llvm.amdgcn.init.exec.from.input(i32, i32) diff --git a/llvm/test/CodeGen/AMDGPU/wave32.ll b/llvm/test/CodeGen/AMDGPU/wave32.ll index a71ca5db765..85c79144d0e 100644 --- a/llvm/test/CodeGen/AMDGPU/wave32.ll +++ b/llvm/test/CodeGen/AMDGPU/wave32.ll @@ -871,33 +871,6 @@ endif: ret void } -; GCN-LABEL: {{^}}test_init_exec: -; GFX1032: s_mov_b32 exec_lo, 0x12345 -; GFX1064: s_mov_b64 exec, 0x12345 -; GCN: v_add_f32_e32 v0, -define amdgpu_ps float @test_init_exec(float %a, float %b) { -main_body: - %s = fadd float %a, %b - call void @llvm.amdgcn.init.exec(i64 74565) - ret float %s -} - -; GCN-LABEL: {{^}}test_init_exec_from_input: -; GCN: s_bfe_u32 s0, s3, 0x70008 -; GFX1032: s_bfm_b32 exec_lo, s0, 0 -; GFX1032: s_cmp_eq_u32 s0, 32 -; GFX1032: s_cmov_b32 exec_lo, -1 -; GFX1064: s_bfm_b64 exec, s0, 0 -; GFX1064: s_cmp_eq_u32 s0, 64 -; GFX1064: s_cmov_b64 exec, -1 -; GCN: v_add_f32_e32 v0, -define amdgpu_ps float @test_init_exec_from_input(i32 inreg, i32 inreg, i32 inreg, i32 inreg %count, float %a, float %b) { -main_body: - %s = fadd float %a, %b - call void @llvm.amdgcn.init.exec.from.input(i32 %count, i32 8) - ret float %s -} - ; GCN-LABEL: {{^}}test_vgprblocks_w32_attr: ; Test that the wave size can be overridden in function attributes and that the block size is correct as a result ; GFX10DEFWAVE: ; VGPRBlocks: 1 @@ -1132,8 +1105,6 @@ declare i32 @llvm.amdgcn.icmp.i32.i32(i32, i32, i32) declare void @llvm.amdgcn.kill(i1) declare i1 @llvm.amdgcn.wqm.vote(i1) declare i1 @llvm.amdgcn.ps.live() -declare void @llvm.amdgcn.init.exec(i64) -declare void @llvm.amdgcn.init.exec.from.input(i32, i32) declare i64 @llvm.cttz.i64(i64, i1) declare i32 @llvm.cttz.i32(i32, i1) |
