diff options
Diffstat (limited to 'llvm/test')
| -rw-r--r-- | llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll | 22 | ||||
| -rw-r--r-- | llvm/test/CodeGen/AArch64/vcvt-oversize.ll | 16 | ||||
| -rw-r--r-- | llvm/test/CodeGen/ARM/vcvt.ll | 4 |
3 files changed, 29 insertions, 13 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll b/llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll index 62596adc743..c4e3e4eae63 100644 --- a/llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll +++ b/llvm/test/CodeGen/AArch64/arm64-convert-v4f64.ll @@ -3,11 +3,11 @@ define <4 x i16> @fptosi_v4f64_to_v4i16(<4 x double>* %ptr) { ; CHECK: fptosi_v4f64_to_v4i16 -; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v1.2d -; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v0.2d -; CHECK-DAG: xtn v[[LHS_NA:[0-9]+]].2s, v[[LHS]].2d -; CHECK-DAG: xtn v[[RHS_NA:[0-9]+]].2s, v[[RHS]].2d -; CHECK: uzp1 v0.4h, v[[RHS_NA]].4h, v[[LHS_NA]].4h +; CHECK-DAG: fcvtzs v[[LHS:[0-9]+]].2d, v0.2d +; CHECK-DAG: fcvtzs v[[RHS:[0-9]+]].2d, v1.2d +; CHECK-DAG: xtn v[[MID:[0-9]+]].2s, v[[LHS]].2d +; CHECK-DAG: xtn2 v[[MID]].4s, v[[RHS]].2d +; CHECK: xtn v0.4h, v[[MID]].4s %tmp1 = load <4 x double>, <4 x double>* %ptr %tmp2 = fptosi <4 x double> %tmp1 to <4 x i16> ret <4 x i16> %tmp2 @@ -19,13 +19,13 @@ define <8 x i8> @fptosi_v4f64_to_v4i8(<8 x double>* %ptr) { ; CHECK-DAG: fcvtzs v[[CONV1:[0-9]+]].2d, v1.2d ; CHECK-DAG: fcvtzs v[[CONV2:[0-9]+]].2d, v2.2d ; CHECK-DAG: fcvtzs v[[CONV3:[0-9]+]].2d, v3.2d -; CHECK-DAG: xtn v[[NA0:[0-9]+]].2s, v[[CONV0]].2d -; CHECK-DAG: xtn v[[NA1:[0-9]+]].2s, v[[CONV1]].2d ; CHECK-DAG: xtn v[[NA2:[0-9]+]].2s, v[[CONV2]].2d -; CHECK-DAG: xtn v[[NA3:[0-9]+]].2s, v[[CONV3]].2d -; CHECK-DAG: uzp1 v[[TMP1:[0-9]+]].4h, v[[CONV1]].4h, v[[CONV0]].4h -; CHECK-DAG: uzp1 v[[TMP2:[0-9]+]].4h, v[[CONV3]].4h, v[[CONV2]].4h -; CHECK: uzp1 v0.8b, v[[TMP2]].8b, v[[TMP1]].8b +; CHECK-DAG: xtn2 v[[NA2]].4s, v[[CONV3]].2d +; CHECK-DAG: xtn v[[NA0:[0-9]+]].2s, v[[CONV0]].2d +; CHECK-DAG: xtn2 v[[NA0]].4s, v[[CONV1]].2d +; CHECK-DAG: xtn v[[TMP1:[0-9]+]].4h, v[[NA0]].4s +; CHECK-DAG: xtn2 v[[TMP1]].8h, v[[NA2]].4s +; CHECK: xtn v0.8b, v[[TMP1]].8h %tmp1 = load <8 x double>, <8 x double>* %ptr %tmp2 = fptosi <8 x double> %tmp1 to <8 x i8> ret <8 x i8> %tmp2 diff --git a/llvm/test/CodeGen/AArch64/vcvt-oversize.ll b/llvm/test/CodeGen/AArch64/vcvt-oversize.ll new file mode 100644 index 00000000000..066a4b66620 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/vcvt-oversize.ll @@ -0,0 +1,16 @@ +; RUN: llc -mtriple=aarch64 < %s | FileCheck %s + +define <8 x i8> @float_to_i8(<8 x float>* %in) { +; CHECK-LABEL: float_to_i8: +; CHECK-DAG: fadd v[[LSB:[0-9]+]].4s, v0.4s, v0.4s +; CHECK-DAG: fadd v[[MSB:[0-9]+]].4s, v1.4s, v1.4s +; CHECK-DAG: fcvtzu v[[LSB2:[0-9]+]].4s, v[[LSB]].4s +; CHECK-DAG: fcvtzu v[[MSB2:[0-9]+]].4s, v[[MSB]].4s +; CHECK-DAG: xtn v[[TMP:[0-9]+]].4h, v[[LSB]].4s +; CHECK-DAG: xtn2 v[[TMP]].8h, v[[MSB]].4s +; CHECK-DAG: xtn v0.8b, v[[TMP]].8h + %l = load <8 x float>, <8 x float>* %in + %scale = fmul <8 x float> %l, <float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0, float 2.0> + %conv = fptoui <8 x float> %scale to <8 x i8> + ret <8 x i8> %conv +} diff --git a/llvm/test/CodeGen/ARM/vcvt.ll b/llvm/test/CodeGen/ARM/vcvt.ll index 0b7ffb8960a..78105f7e0ad 100644 --- a/llvm/test/CodeGen/ARM/vcvt.ll +++ b/llvm/test/CodeGen/ARM/vcvt.ll @@ -180,8 +180,8 @@ define <2 x i64> @fix_float_to_i64(<2 x float> %in) { define <4 x i16> @fix_double_to_i16(<4 x double> %in) { ; CHECK-LABEL: fix_double_to_i16: -; CHECK: vcvt.s32.f64 -; CHECK: vcvt.s32.f64 +; CHECK: vcvt.u32.f64 +; CHECK: vcvt.u32.f64 %scale = fmul <4 x double> %in, <double 2.0, double 2.0, double 2.0, double 2.0> %conv = fptoui <4 x double> %scale to <4 x i16> |
