diff options
Diffstat (limited to 'llvm/test')
26 files changed, 45 insertions, 45 deletions
diff --git a/llvm/test/Analysis/BasicAA/noalias-bugs.ll b/llvm/test/Analysis/BasicAA/noalias-bugs.ll index acb230c45de..71b3c443f54 100644 --- a/llvm/test/Analysis/BasicAA/noalias-bugs.ll +++ b/llvm/test/Analysis/BasicAA/noalias-bugs.ll @@ -24,7 +24,7 @@ define i64 @testcase(%nested * noalias %p1, %nested * noalias %p2, ; CHECK: store i64 2 ; CHECK: load -; CHECK; store i64 1 +; CHECK: store i64 1 store i64 2, i64* %ptr.64, align 8 %r = load i64, i64* %either_ptr.64, align 8 diff --git a/llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll b/llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll index 4703d25a601..1a9074beb40 100644 --- a/llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll +++ b/llvm/test/CodeGen/AArch64/arm64-addr-type-promotion.ll @@ -13,8 +13,8 @@ define zeroext i8 @fullGtU(i32 %i1, i32 %i2) { ; CHECK-NEXT: ldr [[BLOCKBASE:x[0-9]+]], {{\[}}[[ADDR]]] ; CHECK-NEXT: ldrb [[BLOCKVAL1:w[0-9]+]], {{\[}}[[BLOCKBASE]], w0, sxtw] ; CHECK-NEXT: ldrb [[BLOCKVAL2:w[0-9]+]], {{\[}}[[BLOCKBASE]], w1, sxtw] -; CHECK-NEXT cmp [[BLOCKVAL1]], [[BLOCKVAL2]] -; CHECK-NEXT b.ne +; CHECK-NEXT: cmp [[BLOCKVAL1]], [[BLOCKVAL2]] +; CHECK-NEXT: b.ne ; Next BB ; CHECK: add [[BLOCKBASE2:x[0-9]+]], [[BLOCKBASE]], w1, sxtw ; CHECK-NEXT: add [[BLOCKBASE1:x[0-9]+]], [[BLOCKBASE]], w0, sxtw diff --git a/llvm/test/CodeGen/AArch64/arm64-popcnt.ll b/llvm/test/CodeGen/AArch64/arm64-popcnt.ll index d6c9471b7a1..9ee53a0f92e 100644 --- a/llvm/test/CodeGen/AArch64/arm64-popcnt.ll +++ b/llvm/test/CodeGen/AArch64/arm64-popcnt.ll @@ -59,7 +59,7 @@ define i32 @cnt32(i32 %x) nounwind readnone noimplicitfloat { %cnt = tail call i32 @llvm.ctpop.i32(i32 %x) ret i32 %cnt ; CHECK-LABEL: cnt32: -; CHECK-NOT 16b +; CHECK-NOT: 16b ; CHECK: ret } @@ -67,7 +67,7 @@ define i64 @cnt64(i64 %x) nounwind readnone noimplicitfloat { %cnt = tail call i64 @llvm.ctpop.i64(i64 %x) ret i64 %cnt ; CHECK-LABEL: cnt64: -; CHECK-NOT 16b +; CHECK-NOT: 16b ; CHECK: ret } diff --git a/llvm/test/CodeGen/ARM/fold-stack-adjust.ll b/llvm/test/CodeGen/ARM/fold-stack-adjust.ll index 99174213562..614966d4024 100644 --- a/llvm/test/CodeGen/ARM/fold-stack-adjust.ll +++ b/llvm/test/CodeGen/ARM/fold-stack-adjust.ll @@ -62,7 +62,7 @@ define void @check_vfp_fold() minsize { ; ... ; CHECK-NOT: add sp, ; CHECK: vpop {d6, d7, d8, d9} -; CHECKL pop {r[[GLOBREG]], pc} +; CHECK: pop {r[[GLOBREG]], pc} ; iOS uses aligned NEON stores here, which is convenient since we ; want to make sure that works too. diff --git a/llvm/test/CodeGen/NVPTX/vector-call.ll b/llvm/test/CodeGen/NVPTX/vector-call.ll index a03d7fd4191..968d1d4a5f5 100644 --- a/llvm/test/CodeGen/NVPTX/vector-call.ll +++ b/llvm/test/CodeGen/NVPTX/vector-call.ll @@ -4,7 +4,7 @@ target triple = "nvptx-unknown-cuda" declare void @bar(<4 x i32>) -; CHECK-LABEL @foo +; CHECK-LABEL: @foo define void @foo(<4 x i32> %a) { ; CHECK: st.param.v4.b32 tail call void @bar(<4 x i32> %a) diff --git a/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll b/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll index ad8ed38da7f..028006320cb 100644 --- a/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll @@ -10,7 +10,7 @@ define void @main() { } ; CHECK-LABEL: @main -; CHECK-DAG li 4, 0 +; CHECK-DAG: li 4, 0 ; CHECK-DAG: crxor 6, 6, 6 ; CHECK: bl printf diff --git a/llvm/test/CodeGen/PowerPC/rm-zext.ll b/llvm/test/CodeGen/PowerPC/rm-zext.ll index 97c546c0145..df5fe4f7a15 100644 --- a/llvm/test/CodeGen/PowerPC/rm-zext.ll +++ b/llvm/test/CodeGen/PowerPC/rm-zext.ll @@ -9,7 +9,7 @@ entry: %shr2 = lshr i32 %mul, 5 ret i32 %shr2 -; CHECK-LABEL @foo +; CHECK-LABEL: @foo ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 ; CHECK: blr } @@ -23,7 +23,7 @@ entry: %or = or i32 %shr, %shl ret i32 %or -; CHECK-LABEL @test6 +; CHECK-LABEL: @test6 ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 ; CHECK: blr } @@ -34,7 +34,7 @@ entry: %cond = select i1 %cmp, i32 %a, i32 %b ret i32 %cond -; CHECK-LABEL @min +; CHECK-LABEL: @min ; CHECK-NOT: rldicl 3, {{[0-9]+}}, 0, 32 ; CHECK: blr } diff --git a/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll b/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll index 5ec019dfb4a..d1f60da6c74 100644 --- a/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll +++ b/llvm/test/CodeGen/PowerPC/sdiv-pow2.ll @@ -9,7 +9,7 @@ entry: %div = sdiv i32 %a, 8 ret i32 %div -; CHECK-LABEL @foo4 +; CHECK-LABEL: @foo4 ; CHECK: srawi [[REG1:[0-9]+]], 3, 3 ; CHECK: addze [[REG2:[0-9]+]], [[REG1]] ; CHECK: extsw 3, [[REG2]] @@ -22,12 +22,12 @@ entry: %div = sdiv i64 %a, 8 ret i64 %div -; CHECK-LABEL @foo8 +; CHECK-LABEL: @foo8 ; CHECK: sradi [[REG1:[0-9]+]], 3, 3 ; CHECK: addze 3, [[REG1]] ; CHECK: blr -; CHECK-32-LABEL @foo8 +; CHECK-32-LABEL: @foo8 ; CHECK-32-NOT: sradi ; CHECK-32: blr } @@ -58,7 +58,7 @@ entry: ; CHECK: neg 3, [[REG2]] ; CHECK: blr -; CHECK-32-LABEL @foo8n +; CHECK-32-LABEL: @foo8n ; CHECK-32-NOT: sradi ; CHECK-32: blr } diff --git a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll index f7ebf479755..9e79b52c404 100644 --- a/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll +++ b/llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll @@ -14,7 +14,7 @@ define <1 x i128> @increment_by_one(<1 x i128> %x) nounwind { %result = add <1 x i128> %x, <i128 1> ret <1 x i128> %result ; CHECK-LABEL: @increment_by_one -; CHECK vadduqm 2, 2, 3 +; CHECK: vadduqm 2, 2, 3 } define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind { @@ -37,7 +37,7 @@ define <1 x i128> @decrement_by_one(<1 x i128> %x) nounwind { %result = sub <1 x i128> %x, <i128 1> ret <1 x i128> %result ; CHECK-LABEL: @decrement_by_one -; CHECK vsubuqm 2, 2, 3 +; CHECK: vsubuqm 2, 2, 3 } define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind { @@ -46,7 +46,7 @@ define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind { %result = sub <1 x i128> %x, %tmpvec2 ret <1 x i128> %result ; CHECK-LABEL: @decrement_by_val -; CHECK vsubuqm 2, 2, 3 +; CHECK: vsubuqm 2, 2, 3 } declare <1 x i128> @llvm.ppc.altivec.vaddeuqm(<1 x i128> %x, diff --git a/llvm/test/CodeGen/X86/GC/dynamic-frame-size.ll b/llvm/test/CodeGen/X86/GC/dynamic-frame-size.ll index a3583d46a29..9ec9b8b0850 100644 --- a/llvm/test/CodeGen/X86/GC/dynamic-frame-size.ll +++ b/llvm/test/CodeGen/X86/GC/dynamic-frame-size.ll @@ -17,12 +17,12 @@ define void @test(i8* %ptr) gc "erlang" { ; CHECK: .note.gc ; CHECK-NEXT: .align 8 ; safe point count -; CHECK .short 1 -; CHECK .long .Ltmp0 +; CHECK: .short 1 +; CHECK: .long .Ltmp0 ; stack frame size (in words) -; CHECK .short -1 +; CHECK: .short -1 ; stack arity (arguments on the stack) -; CHECK .short 0 +; CHECK: .short 0 ; live root count -; CHECK .short 0 +; CHECK: .short 0 diff --git a/llvm/test/CodeGen/X86/codegen-prepare-cast.ll b/llvm/test/CodeGen/X86/codegen-prepare-cast.ll index 1ab8017e885..c5c2d64f63d 100644 --- a/llvm/test/CodeGen/X86/codegen-prepare-cast.ll +++ b/llvm/test/CodeGen/X86/codegen-prepare-cast.ll @@ -11,7 +11,7 @@ target triple = "x86_64-unknown-linux-gnu" ; CHECK-LABEL: @_Dmain ; CHECK: load i8, i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str, i32 0, i32 0) -; CHECK ret +; CHECK: ret define fastcc i32 @_Dmain(%"char[][]" %unnamed) { entry: %tmp = getelementptr [7 x i8], [7 x i8]* @.str, i32 0, i32 0 ; <i8*> [#uses=1] diff --git a/llvm/test/CodeGen/X86/fma-do-not-commute.ll b/llvm/test/CodeGen/X86/fma-do-not-commute.ll index 1f6a19cfff8..89be0795d20 100644 --- a/llvm/test/CodeGen/X86/fma-do-not-commute.ll +++ b/llvm/test/CodeGen/X86/fma-do-not-commute.ll @@ -6,7 +6,7 @@ target triple = "x86_64-apple-macosx" ; CHECK-LABEL: test1: ; %arg lives in xmm0 and it shouldn't be redefined until it is used in the FMA. -; CHECK-NOT {{.*}}, %xmm0 +; CHECK-NOT: {{.*}}, %xmm0 ; %addr lives in rdi. ; %addr2 lives in rsi. ; CHECK: vmovss (%rsi), [[ADDR2:%xmm[0-9]+]] diff --git a/llvm/test/CodeGen/X86/machine-cp.ll b/llvm/test/CodeGen/X86/machine-cp.ll index aaed0f0a23d..768b9cab6f6 100644 --- a/llvm/test/CodeGen/X86/machine-cp.ll +++ b/llvm/test/CodeGen/X86/machine-cp.ll @@ -83,12 +83,12 @@ while.end: ; preds = %while.body, %entry ; CHECK-NOT: , [[CPY1]] ; CHECK: punpcklbw [[CPY2]], [[CPY2]] ; CHECK-NEXT: punpckhwd [[CPY2]], [[CPY2]] -; CHECK-NEXT pslld $31, [[CPY2]] +; CHECK-NEXT: pslld $31, [[CPY2]] ; Check that CPY1 is not redefined. ; CHECK-NOT: , [[CPY1]] ; CHECK: punpcklbw [[CPY1]], [[CPY1]] ; CHECK-NEXT: punpcklwd [[CPY1]], [[CPY1]] -; CHECK-NEXT pslld $31, [[CPY1]] +; CHECK-NEXT: pslld $31, [[CPY1]] define <16 x float> @foo(<16 x float> %x) { bb: %v3 = icmp slt <16 x i32> undef, zeroinitializer diff --git a/llvm/test/CodeGen/X86/statepoint-invoke.ll b/llvm/test/CodeGen/X86/statepoint-invoke.ll index 81b9ab89ebc..7e35d4f4d38 100644 --- a/llvm/test/CodeGen/X86/statepoint-invoke.ll +++ b/llvm/test/CodeGen/X86/statepoint-invoke.ll @@ -113,7 +113,7 @@ right.relocs: normal_return: ; CHECK-LABEL: %normal_return ; CHECK: cmoveq {{.*}}[[REGVAL2]]{{.*}} - ; CHECK retq + ; CHECK: retq %a1 = phi i64 addrspace(1)* [%val1.relocated, %left.relocs], [%val3.relocated, %right.relocs] %a2 = phi i64 addrspace(1)* [%val2.relocated_left, %left.relocs], [%val2.relocated_right, %right.relocs] %ret = select i1 %cond, i64 addrspace(1)* %a1, i64 addrspace(1)* %a2 diff --git a/llvm/test/DebugInfo/dwarfdump-accel.test b/llvm/test/DebugInfo/dwarfdump-accel.test index c5c3b0154c1..7c183882956 100644 --- a/llvm/test/DebugInfo/dwarfdump-accel.test +++ b/llvm/test/DebugInfo/dwarfdump-accel.test @@ -57,7 +57,7 @@ CHECK-NOT: Magic Check ObjC specific accelerators. CHECK: .apple_objc contents: CHECK: Name{{.*}}"TestInterface" -CHECK-NOT Name +CHECK-NOT: Name CHECK: {Atom[0]: [[READONLY]]} CHECK: {Atom[0]: [[ASSIGN]]} CHECK: {Atom[0]: [[SETASSIGN]]} diff --git a/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s b/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s index 005f27bb398..9b764c18448 100644 --- a/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s +++ b/llvm/test/MC/ARM/basic-arm-instructions-v8.1a.s @@ -37,7 +37,7 @@ //CHECK-V8: vqrdmlsh.f32 q3, q4, q5 //CHECK-V8: ^ //CHECK-V8: error: invalid operand for instruction -//CHECK-V8 vqrdmlsh.f64 d3, d5, d5 +//CHECK-V8: vqrdmlsh.f64 d3, d5, d5 //CHECK-V8: ^ vqrdmlah.s16 d0, d1, d2 diff --git a/llvm/test/MC/AsmParser/macros-darwin-vararg.s b/llvm/test/MC/AsmParser/macros-darwin-vararg.s index 4aa2f4c1d9b..1c3ff69180f 100644 --- a/llvm/test/MC/AsmParser/macros-darwin-vararg.s +++ b/llvm/test/MC/AsmParser/macros-darwin-vararg.s @@ -54,7 +54,7 @@ abc zed0, zed1, zed2 ifcc4 %eax, %ecx ## test ifcc4 %ecx, %eax ## test -// CHECK-NOT movl +// CHECK-NOT: movl // CHECK: subl $1, %esp .set cc,0 ifcc movl, %esp, %ebp diff --git a/llvm/test/MC/AsmParser/vararg.s b/llvm/test/MC/AsmParser/vararg.s index e3236b072d1..dae81dfb78c 100644 --- a/llvm/test/MC/AsmParser/vararg.s +++ b/llvm/test/MC/AsmParser/vararg.s @@ -44,7 +44,7 @@ ifcc4 %eax %ecx ## test ifcc4 %ecx, %eax ## test -// CHECK-NOT movl +// CHECK-NOT: movl // CHECK: subl $1, %esp .set cc,0 ifcc movl %esp, %ebp diff --git a/llvm/test/Transforms/InstCombine/cast-set.ll b/llvm/test/Transforms/InstCombine/cast-set.ll index 47ba920d928..8f19bdcdfde 100644 --- a/llvm/test/Transforms/InstCombine/cast-set.ll +++ b/llvm/test/Transforms/InstCombine/cast-set.ll @@ -10,7 +10,7 @@ define i1 @test1(i32 %X) { ; Convert to setne int %X, 12 %c = icmp ne i32 %A, 12 ; <i1> [#uses=1] ret i1 %c -; CHECK-LABEL @test1( +; CHECK-LABEL: @test1( ; CHECK: %c = icmp ne i32 %X, 12 ; CHECK: ret i1 %c } @@ -21,7 +21,7 @@ define i1 @test2(i32 %X, i32 %Y) { ; Convert to setne int %X, %Y %c = icmp ne i32 %A, %B ; <i1> [#uses=1] ret i1 %c -; CHECK-LABEL @test2( +; CHECK-LABEL: @test2( ; CHECK: %c = icmp ne i32 %X, %Y ; CHECK: ret i1 %c } diff --git a/llvm/test/Transforms/InstCombine/div.ll b/llvm/test/Transforms/InstCombine/div.ll index e0ff07baae7..933d9ec4b0d 100644 --- a/llvm/test/Transforms/InstCombine/div.ll +++ b/llvm/test/Transforms/InstCombine/div.ll @@ -163,7 +163,7 @@ define i32 @test19(i32 %x) { ; CHECK-LABEL: @test19( ; CHECK-NEXT: icmp eq i32 %x, 1 ; CHECK-NEXT: zext i1 %{{.*}} to i32 -; CHECK-NEXT ret i32 +; CHECK-NEXT: ret i32 } define i32 @test20(i32 %x) { diff --git a/llvm/test/Transforms/InstSimplify/apint-or.ll b/llvm/test/Transforms/InstSimplify/apint-or.ll index 5d314db7133..ebbc7be98b0 100644 --- a/llvm/test/Transforms/InstSimplify/apint-or.ll +++ b/llvm/test/Transforms/InstSimplify/apint-or.ll @@ -12,7 +12,7 @@ define i39 @test1(i39 %V, i39 %M) { %D = and i39 %V, 274877906943 %R = or i39 %B, %D ret i39 %R -; CHECK-LABEL @test1 +; CHECK-LABEL: @test1 ; CHECK-NEXT: and {{.*}}, -274877906944 ; CHECK-NEXT: add ; CHECK-NEXT: ret @@ -30,7 +30,7 @@ define i399 @test2(i399 %V, i399 %M) { %D = and i399 %V, 274877906943 %R = or i399 %B, %D ret i399 %R -; CHECK-LABEL @test2 +; CHECK-LABEL: @test2 ; CHECK-NEXT: and {{.*}}, 18446742974197923840 ; CHECK-NEXT: add ; CHECK-NEXT: ret diff --git a/llvm/test/Transforms/MergeFunc/ranges.ll b/llvm/test/Transforms/MergeFunc/ranges.ll index 46a0c76cc7d..44e71300703 100644 --- a/llvm/test/Transforms/MergeFunc/ranges.ll +++ b/llvm/test/Transforms/MergeFunc/ranges.ll @@ -8,10 +8,10 @@ define i1 @cmp_with_range(i8*, i8*) { define i1 @cmp_no_range(i8*, i8*) { ; CHECK-LABEL: @cmp_no_range -; CHECK-NEXT %v1 = load i8, i8* %0 -; CHECK-NEXT %v2 = load i8, i8* %1 -; CHECK-NEXT %out = icmp eq i8 %v1, %v2 -; CHECK-NEXT ret i1 %out +; CHECK-NEXT: %v1 = load i8, i8* %0 +; CHECK-NEXT: %v2 = load i8, i8* %1 +; CHECK-NEXT: %out = icmp eq i8 %v1, %v2 +; CHECK-NEXT: ret i1 %out %v1 = load i8, i8* %0 %v2 = load i8, i8* %1 %out = icmp eq i8 %v1, %v2 diff --git a/llvm/test/Transforms/Reassociate/vaarg_movable.ll b/llvm/test/Transforms/Reassociate/vaarg_movable.ll index 4581bc15c67..be4fe121fae 100644 --- a/llvm/test/Transforms/Reassociate/vaarg_movable.ll +++ b/llvm/test/Transforms/Reassociate/vaarg_movable.ll @@ -3,7 +3,7 @@ ; The two va_arg instructions depend on the memory/context, are therfore not ; identical and the sub should not be optimized to 0 by reassociate. ; -; CHECK-LABEL @func( +; CHECK-LABEL: @func( ; ... ; CHECK: %v0 = va_arg i8** %varargs, i32 ; CHECK: %v1 = va_arg i8** %varargs, i32 diff --git a/llvm/test/Transforms/RewriteStatepointsForGC/relocation.ll b/llvm/test/Transforms/RewriteStatepointsForGC/relocation.ll index d7a84e5820c..10ee08c25a4 100644 --- a/llvm/test/Transforms/RewriteStatepointsForGC/relocation.ll +++ b/llvm/test/Transforms/RewriteStatepointsForGC/relocation.ll @@ -232,7 +232,7 @@ inner-loop: ; CHECK: phi i8 addrspace(1)* ; CHECK-DAG: %outer-loop ] ; CHECK-DAG: [ %arg2.relocated, %inner-loop ] -; CHECKL phi i8 addrspace(1)* +; CHECK: phi i8 addrspace(1)* ; CHECK-DAG: %outer-loop ] ; CHECK-DAG: [ %arg1.relocated, %inner-loop ] ; CHECK: gc.statepoint diff --git a/llvm/test/Transforms/TailCallElim/basic.ll b/llvm/test/Transforms/TailCallElim/basic.ll index 2488b552d8f..fe8bbe9ad03 100644 --- a/llvm/test/Transforms/TailCallElim/basic.ll +++ b/llvm/test/Transforms/TailCallElim/basic.ll @@ -156,7 +156,7 @@ define void @test9(i32* byval %a) { declare void @ctor(%struct.X*) define void @test10(%struct.X* noalias sret %agg.result, i1 zeroext %b) { -; CHECK-LABEL @test10 +; CHECK-LABEL: @test10 entry: %x = alloca %struct.X, align 8 br i1 %b, label %if.then, label %if.end diff --git a/llvm/test/tools/dsymutil/X86/basic-lto-linking-x86.test b/llvm/test/tools/dsymutil/X86/basic-lto-linking-x86.test index 81744273c6b..5e9185d92b5 100644 --- a/llvm/test/tools/dsymutil/X86/basic-lto-linking-x86.test +++ b/llvm/test/tools/dsymutil/X86/basic-lto-linking-x86.test @@ -117,7 +117,7 @@ CHECK: DW_AT_type [DW_FORM_ref_addr] (0x0000000000000063) CHECK: DW_AT_location [DW_FORM_data4] (0x00000025) CHECK: DW_TAG_lexical_block [14] * CHECK: DW_AT_low_pc [DW_FORM_addr] (0x0000000100000f94) -CHECK DW_AT_high_pc [DW_FORM_addr] (0x0000000100000fa7) +CHECK: DW_AT_high_pc [DW_FORM_addr] (0x0000000100000fa7) CHECK: DW_TAG_inlined_subroutine [15] CHECK: DW_AT_abstract_origin [DW_FORM_ref4] (cu + 0x009a => {0x000001d4} "inc") CHECK: DW_AT_ranges [DW_FORM_data4] (0x00000000 |
