diff options
Diffstat (limited to 'llvm/test')
21 files changed, 4957 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/SystemZ/branch-11.ll b/llvm/test/CodeGen/SystemZ/branch-11.ll new file mode 100644 index 00000000000..ce7b3ef267b --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/branch-11.ll @@ -0,0 +1,56 @@ +; Test indirect jumps on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +define i32 @f1(i32 %x, i32 %y, i32 %op) { +; CHECK-LABEL: f1: +; CHECK: ahi %r4, -1 +; CHECK: clibh %r4, 5, 0(%r14) +; CHECK: llgfr [[OP64:%r[0-5]]], %r4 +; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3 +; CHECK: larl [[BASE:%r[1-5]]] +; CHECK: bi 0([[BASE]],[[INDEX]]) +entry: + switch i32 %op, label %exit [ + i32 1, label %b.add + i32 2, label %b.sub + i32 3, label %b.and + i32 4, label %b.or + i32 5, label %b.xor + i32 6, label %b.mul + ] + +b.add: + %add = add i32 %x, %y + br label %exit + +b.sub: + %sub = sub i32 %x, %y + br label %exit + +b.and: + %and = and i32 %x, %y + br label %exit + +b.or: + %or = or i32 %x, %y + br label %exit + +b.xor: + %xor = xor i32 %x, %y + br label %exit + +b.mul: + %mul = mul i32 %x, %y + br label %exit + +exit: + %res = phi i32 [ %x, %entry ], + [ %add, %b.add ], + [ %sub, %b.sub ], + [ %and, %b.and ], + [ %or, %b.or ], + [ %xor, %b.xor ], + [ %mul, %b.mul ] + ret i32 %res +} diff --git a/llvm/test/CodeGen/SystemZ/fp-mul-10.ll b/llvm/test/CodeGen/SystemZ/fp-mul-10.ll new file mode 100644 index 00000000000..977e5c60e3a --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/fp-mul-10.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare double @llvm.fma.f64(double %f1, double %f2, double %f3) + +define double @f1(double %f1, double %f2, double %acc) { +; CHECK-LABEL: f1: +; CHECK: wfnmadb %f0, %f0, %f2, %f4 +; CHECK: br %r14 + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) + %negres = fsub double -0.0, %res + ret double %negres +} + +define double @f2(double %f1, double %f2, double %acc) { +; CHECK-LABEL: f2: +; CHECK: wfnmsdb %f0, %f0, %f2, %f4 +; CHECK: br %r14 + %negacc = fsub double -0.0, %acc + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) + %negres = fsub double -0.0, %res + ret double %negres +} + diff --git a/llvm/test/CodeGen/SystemZ/int-add-17.ll b/llvm/test/CodeGen/SystemZ/int-add-17.ll new file mode 100644 index 00000000000..fd245871c65 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/int-add-17.ll @@ -0,0 +1,95 @@ +; Test additions between an i64 and a sign-extended i16 on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare i64 @foo() + +; Check AGH with no displacement. +define i64 @f1(i64 %a, i16 *%src) { +; CHECK-LABEL: f1: +; CHECK: agh %r2, 0(%r3) +; CHECK: br %r14 + %b = load i16, i16 *%src + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the high end of the aligned AGH range. +define i64 @f2(i64 %a, i16 *%src) { +; CHECK-LABEL: f2: +; CHECK: agh %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262143 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f3(i64 %a, i16 *%src) { +; CHECK-LABEL: f3: +; CHECK: agfi %r3, 524288 +; CHECK: agh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the high end of the negative aligned AGH range. +define i64 @f4(i64 %a, i16 *%src) { +; CHECK-LABEL: f4: +; CHECK: agh %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -1 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the low end of the AGH range. +define i64 @f5(i64 %a, i16 *%src) { +; CHECK-LABEL: f5: +; CHECK: agh %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 %a, i16 *%src) { +; CHECK-LABEL: f6: +; CHECK: agfi %r3, -524290 +; CHECK: agh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check that AGH allows an index. +define i64 @f7(i64 %a, i64 %src, i64 %index) { +; CHECK-LABEL: f7: +; CHECK: agh %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i16 * + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + diff --git a/llvm/test/CodeGen/SystemZ/int-mul-09.ll b/llvm/test/CodeGen/SystemZ/int-mul-09.ll new file mode 100644 index 00000000000..3e384e72db5 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/int-mul-09.ll @@ -0,0 +1,95 @@ +; Test multiplications between an i64 and a sign-extended i16 on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare i64 @foo() + +; Check MGH with no displacement. +define i64 @f1(i64 %a, i16 *%src) { +; CHECK-LABEL: f1: +; CHECK: mgh %r2, 0(%r3) +; CHECK: br %r14 + %b = load i16, i16 *%src + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the high end of the aligned MGH range. +define i64 @f2(i64 %a, i16 *%src) { +; CHECK-LABEL: f2: +; CHECK: mgh %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262143 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f3(i64 %a, i16 *%src) { +; CHECK-LABEL: f3: +; CHECK: agfi %r3, 524288 +; CHECK: mgh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the high end of the negative aligned MGH range. +define i64 @f4(i64 %a, i16 *%src) { +; CHECK-LABEL: f4: +; CHECK: mgh %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -1 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the low end of the MGH range. +define i64 @f5(i64 %a, i16 *%src) { +; CHECK-LABEL: f5: +; CHECK: mgh %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 %a, i16 *%src) { +; CHECK-LABEL: f6: +; CHECK: agfi %r3, -524290 +; CHECK: mgh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check that MGH allows an index. +define i64 @f7(i64 %a, i64 %src, i64 %index) { +; CHECK-LABEL: f7: +; CHECK: mgh %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i16 * + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + diff --git a/llvm/test/CodeGen/SystemZ/int-mul-10.ll b/llvm/test/CodeGen/SystemZ/int-mul-10.ll new file mode 100644 index 00000000000..a4d80af36a3 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/int-mul-10.ll @@ -0,0 +1,165 @@ +; Test signed high-part i64->i128 multiplications on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare i64 @foo() + +; Check sign-extended multiplication in which only the high part is used. +define i64 @f1(i64 %dummy, i64 %a, i64 %b) { +; CHECK-LABEL: f1: +; CHECK-NOT: {{%r[234]}} +; CHECK: mgrk %r2, %r3, %r4 +; CHECK: br %r14 + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check sign-extended multiplication in which only part of the high half +; is used. +define i64 @f2(i64 %dummy, i64 %a, i64 %b) { +; CHECK-LABEL: f2: +; CHECK-NOT: {{%r[234]}} +; CHECK: mgrk [[REG:%r[0-9]+]], %r3, %r4 +; CHECK: srlg %r2, [[REG]], 3 +; CHECK: br %r14 + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 67 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check sign-extended multiplication in which the result is split into +; high and low halves. +define i64 @f3(i64 %dummy, i64 %a, i64 %b) { +; CHECK-LABEL: f3: +; CHECK-NOT: {{%r[234]}} +; CHECK: mgrk %r2, %r3, %r4 +; CHECK: ogr %r2, %r3 +; CHECK: br %r14 + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + %low = trunc i128 %mulx to i64 + %or = or i64 %high, %low + ret i64 %or +} + +; Check MG with no displacement. +define i64 @f4(i64 %dummy, i64 %a, i64 *%src) { +; CHECK-LABEL: f4: +; CHECK-NOT: {{%r[234]}} +; CHECK: mg %r2, 0(%r4) +; CHECK: br %r14 + %b = load i64 , i64 *%src + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the high end of the aligned MG range. +define i64 @f5(i64 %dummy, i64 %a, i64 *%src) { +; CHECK-LABEL: f5: +; CHECK: mg %r2, 524280(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the next doubleword up, which requires separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 %dummy, i64 %a, i64 *%src) { +; CHECK-LABEL: f6: +; CHECK: agfi %r4, 524288 +; CHECK: mg %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the high end of the negative aligned MG range. +define i64 @f7(i64 %dummy, i64 %a, i64 *%src) { +; CHECK-LABEL: f7: +; CHECK: mg %r2, -8(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the low end of the MG range. +define i64 @f8(i64 %dummy, i64 %a, i64 *%src) { +; CHECK-LABEL: f8: +; CHECK: mg %r2, -524288(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f9(i64 *%dest, i64 %a, i64 *%src) { +; CHECK-LABEL: f9: +; CHECK: agfi %r4, -524296 +; CHECK: mg %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check that MG allows an index. +define i64 @f10(i64 *%dest, i64 %a, i64 %src, i64 %index) { +; CHECK-LABEL: f10: +; CHECK: mg %r2, 524287(%r5,%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + diff --git a/llvm/test/CodeGen/SystemZ/int-mul-11.ll b/llvm/test/CodeGen/SystemZ/int-mul-11.ll new file mode 100644 index 00000000000..f2625198251 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/int-mul-11.ll @@ -0,0 +1,32 @@ +; Test three-operand multiplication instructions on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +; Check MSRKC. +define i32 @f1(i32 %dummy, i32 %a, i32 %b) { +; CHECK-LABEL: f1: +; CHECK: msrkc %r2, %r3, %r4 +; CHECK: br %r14 + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check MSGRKC. +define i64 @f2(i64 %dummy, i64 %a, i64 %b) { +; CHECK-LABEL: f2: +; CHECK: msgrkc %r2, %r3, %r4 +; CHECK: br %r14 + %mul = mul i64 %a, %b + ret i64 %mul +} + +; Verify that we still use MSGFR for i32->i64 multiplies. +define i64 @f3(i64 %a, i32 %b) { +; CHECK-LABEL: f3: +; CHECK: msgfr %r2, %r3 +; CHECK: br %r14 + %bext = sext i32 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + diff --git a/llvm/test/CodeGen/SystemZ/int-sub-10.ll b/llvm/test/CodeGen/SystemZ/int-sub-10.ll new file mode 100644 index 00000000000..bf6638575e5 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/int-sub-10.ll @@ -0,0 +1,95 @@ +; Test subtractions of a sign-extended i16 from an i64 on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare i64 @foo() + +; Check SGH with no displacement. +define i64 @f1(i64 %a, i16 *%src) { +; CHECK-LABEL: f1: +; CHECK: sgh %r2, 0(%r3) +; CHECK: br %r14 + %b = load i16, i16 *%src + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the high end of the aligned SGH range. +define i64 @f2(i64 %a, i16 *%src) { +; CHECK-LABEL: f2: +; CHECK: sgh %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262143 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f3(i64 %a, i16 *%src) { +; CHECK-LABEL: f3: +; CHECK: agfi %r3, 524288 +; CHECK: sgh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the high end of the negative aligned SGH range. +define i64 @f4(i64 %a, i16 *%src) { +; CHECK-LABEL: f4: +; CHECK: sgh %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -1 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the low end of the SGH range. +define i64 @f5(i64 %a, i16 *%src) { +; CHECK-LABEL: f5: +; CHECK: sgh %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 %a, i16 *%src) { +; CHECK-LABEL: f6: +; CHECK: agfi %r3, -524290 +; CHECK: sgh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check that SGH allows an index. +define i64 @f7(i64 %a, i64 %src, i64 %index) { +; CHECK-LABEL: f7: +; CHECK: sgh %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i16 * + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + diff --git a/llvm/test/CodeGen/SystemZ/vec-and-04.ll b/llvm/test/CodeGen/SystemZ/vec-and-04.ll new file mode 100644 index 00000000000..e9355beb429 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/vec-and-04.ll @@ -0,0 +1,47 @@ +; Test vector NAND on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +; Test a v16i8 NAND. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vnn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <16 x i8> %val1, %val2 + %not = xor <16 x i8> %ret, <i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1> + ret <16 x i8> %not +} + +; Test a v8i16 NAND. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vnn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <8 x i16> %val1, %val2 + %not = xor <8 x i16> %ret, <i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1> + ret <8 x i16> %not +} + +; Test a v4i32 NAND. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vnn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <4 x i32> %val1, %val2 + %not = xor <4 x i32> %ret, <i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %not +} + +; Test a v2i64 NAND. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vnn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <2 x i64> %val1, %val2 + %not = xor <2 x i64> %ret, <i64 -1, i64 -1> + ret <2 x i64> %not +} diff --git a/llvm/test/CodeGen/SystemZ/vec-ctpop-02.ll b/llvm/test/CodeGen/SystemZ/vec-ctpop-02.ll new file mode 100644 index 00000000000..ee50e88d043 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/vec-ctpop-02.ll @@ -0,0 +1,45 @@ +; Test vector population-count instruction on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a) +declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %a) +declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %a) +declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a) + +define <16 x i8> @f1(<16 x i8> %a) { +; CHECK-LABEL: f1: +; CHECK: vpopctb %v24, %v24 +; CHECK: br %r14 + + %popcnt = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a) + ret <16 x i8> %popcnt +} + +define <8 x i16> @f2(<8 x i16> %a) { +; CHECK-LABEL: f2: +; CHECK: vpopcth %v24, %v24 +; CHECK: br %r14 + + %popcnt = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %a) + ret <8 x i16> %popcnt +} + +define <4 x i32> @f3(<4 x i32> %a) { +; CHECK-LABEL: f3: +; CHECK: vpopctf %v24, %v24 +; CHECK: br %r14 + + %popcnt = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %a) + ret <4 x i32> %popcnt +} + +define <2 x i64> @f4(<2 x i64> %a) { +; CHECK-LABEL: f4: +; CHECK: vpopctg %v24, %v24 +; CHECK: br %r14 + + %popcnt = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a) + ret <2 x i64> %popcnt +} + diff --git a/llvm/test/CodeGen/SystemZ/vec-intrinsics.ll b/llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll index 6f5eb0691aa..6f5eb0691aa 100644 --- a/llvm/test/CodeGen/SystemZ/vec-intrinsics.ll +++ b/llvm/test/CodeGen/SystemZ/vec-intrinsics-01.ll diff --git a/llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll b/llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll new file mode 100644 index 00000000000..27ee83fc774 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/vec-intrinsics-02.ll @@ -0,0 +1,212 @@ +; Test vector intrinsics added with z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare <2 x i64> @llvm.s390.vbperm(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vmslg(<2 x i64>, <2 x i64>, <16 x i8>, i32) +declare <16 x i8> @llvm.s390.vlrl(i32, i8 *) +declare void @llvm.s390.vstrl(<16 x i8>, i32, i8 *) +declare <2 x double> @llvm.s390.vfmaxdb(<2 x double>, <2 x double>, i32) +declare <2 x double> @llvm.s390.vfmindb(<2 x double>, <2 x double>, i32) + +; VBPERM. +define <2 x i64> @test_vbperm(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vbperm: +; CHECK: vbperm %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vbperm(<16 x i8> %a, <16 x i8> %b) + ret <2 x i64> %res +} + +; VMSLG with no shifts. +define <16 x i8> @test_vmslg1(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vmslg1: +; CHECK: vmslg %v24, %v24, %v26, %v28, 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vmslg(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c, i32 0) + ret <16 x i8> %res +} + +; VMSLG with both shifts. +define <16 x i8> @test_vmslg2(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vmslg2: +; CHECK: vmslg %v24, %v24, %v26, %v28, 12 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vmslg(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c, i32 12) + ret <16 x i8> %res +} + +; VLRLR with the lowest in-range displacement. +define <16 x i8> @test_vlrlr1(i8 *%ptr, i32 %length) { +; CHECK-LABEL: test_vlrlr1: +; CHECK: vlrlr %v24, %r3, 0(%r2) +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; VLRLR with the highest in-range displacement. +define <16 x i8> @test_vlrlr2(i8 *%base, i32 %length) { +; CHECK-LABEL: test_vlrlr2: +; CHECK: vlrlr %v24, %r3, 4095(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; VLRLR with an out-of-range displacement. +define <16 x i8> @test_vlrlr3(i8 *%base, i32 %length) { +; CHECK-LABEL: test_vlrlr3: +; CHECK: vlrlr %v24, %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; Check that VLRLR doesn't allow an index. +define <16 x i8> @test_vlrlr4(i8 *%base, i64 %index, i32 %length) { +; CHECK-LABEL: test_vlrlr4: +; CHECK: vlrlr %v24, %r4, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; VLRL with the lowest in-range displacement. +define <16 x i8> @test_vlrl1(i8 *%ptr) { +; CHECK-LABEL: test_vlrl1: +; CHECK: vlrl %v24, 0(%r2), 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr) + ret <16 x i8> %res +} + +; VLRL with the highest in-range displacement. +define <16 x i8> @test_vlrl2(i8 *%base) { +; CHECK-LABEL: test_vlrl2: +; CHECK: vlrl %v24, 4095(%r2), 0 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + %res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr) + ret <16 x i8> %res +} + +; VLRL with an out-of-range displacement. +define <16 x i8> @test_vlrl3(i8 *%base) { +; CHECK-LABEL: test_vlrl3: +; CHECK: vlrl %v24, 0({{%r[1-5]}}), 0 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + %res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr) + ret <16 x i8> %res +} + +; Check that VLRL doesn't allow an index. +define <16 x i8> @test_vlrl4(i8 *%base, i64 %index) { +; CHECK-LABEL: test_vlrl4: +; CHECK: vlrl %v24, 0({{%r[1-5]}}), 0 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + %res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr) + ret <16 x i8> %res +} + +; VSTRLR with the lowest in-range displacement. +define void @test_vstrlr1(<16 x i8> %vec, i8 *%ptr, i32 %length) { +; CHECK-LABEL: test_vstrlr1: +; CHECK: vstrlr %v24, %r3, 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; VSTRLR with the highest in-range displacement. +define void @test_vstrlr2(<16 x i8> %vec, i8 *%base, i32 %length) { +; CHECK-LABEL: test_vstrlr2: +; CHECK: vstrlr %v24, %r3, 4095(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; VSTRLR with an out-of-range displacement. +define void @test_vstrlr3(<16 x i8> %vec, i8 *%base, i32 %length) { +; CHECK-LABEL: test_vstrlr3: +; CHECK: vstrlr %v24, %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; Check that VSTRLR doesn't allow an index. +define void @test_vstrlr4(<16 x i8> %vec, i8 *%base, i64 %index, i32 %length) { +; CHECK-LABEL: test_vstrlr4: +; CHECK: vstrlr %v24, %r4, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; VSTRL with the lowest in-range displacement. +define void @test_vstrl1(<16 x i8> %vec, i8 *%ptr) { +; CHECK-LABEL: test_vstrl1: +; CHECK: vstrl %v24, 0(%r2), 8 +; CHECK: br %r14 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr) + ret void +} + +; VSTRL with the highest in-range displacement. +define void @test_vstrl2(<16 x i8> %vec, i8 *%base) { +; CHECK-LABEL: test_vstrl2: +; CHECK: vstrl %v24, 4095(%r2), 8 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr) + ret void +} + +; VSTRL with an out-of-range displacement. +define void @test_vstrl3(<16 x i8> %vec, i8 *%base) { +; CHECK-LABEL: test_vstrl3: +; CHECK: vstrl %v24, 0({{%r[1-5]}}), 8 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr) + ret void +} + +; Check that VSTRL doesn't allow an index. +define void @test_vstrl4(<16 x i8> %vec, i8 *%base, i64 %index) { +; CHECK-LABEL: test_vstrl4: +; CHECK: vstrl %v24, 0({{%r[1-5]}}), 8 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr) + ret void +} + +; VFMAXDB. +define <2 x double> @test_vfmaxdb(<2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: test_vfmaxdb: +; CHECK: vfmaxdb %v24, %v24, %v26, 4 +; CHECK: br %r14 + %res = call <2 x double> @llvm.s390.vfmaxdb(<2 x double> %a, <2 x double> %b, i32 4) + ret <2 x double> %res +} + +; VFMINDB. +define <2 x double> @test_vfmindb(<2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: test_vfmindb: +; CHECK: vfmindb %v24, %v24, %v26, 4 +; CHECK: br %r14 + %res = call <2 x double> @llvm.s390.vfmindb(<2 x double> %a, <2 x double> %b, i32 4) + ret <2 x double> %res +} + diff --git a/llvm/test/CodeGen/SystemZ/vec-max-05.ll b/llvm/test/CodeGen/SystemZ/vec-max-05.ll new file mode 100644 index 00000000000..44efac76423 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/vec-max-05.ll @@ -0,0 +1,58 @@ +; Test vector maximum on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare double @fmax(double, double) +declare double @llvm.maxnum.f64(double, double) +declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>) + +; Test the fmax library function. +define double @f1(double %dummy, double %val1, double %val2) { +; CHECK-LABEL: f1: +; CHECK: wfmaxdb %f0, %f2, %f4, 4 +; CHECK: br %r14 + %ret = call double @fmax(double %val1, double %val2) readnone + ret double %ret +} + +; Test the f64 maxnum intrinsic. +define double @f2(double %dummy, double %val1, double %val2) { +; CHECK-LABEL: f2: +; CHECK: wfmaxdb %f0, %f2, %f4, 4 +; CHECK: br %r14 + %ret = call double @llvm.maxnum.f64(double %val1, double %val2) + ret double %ret +} + +; Test a f64 constant compare/select resulting in maxnum. +define double @f3(double %dummy, double %val) { +; CHECK-LABEL: f3: +; CHECK: lzdr [[REG:%f[0-9]+]] +; CHECK: wfmaxdb %f0, %f2, [[REG]], 4 +; CHECK: br %r14 + %cmp = fcmp ogt double %val, 0.0 + %ret = select i1 %cmp, double %val, double 0.0 + ret double %ret +} + +; Test a f64 constant compare/select resulting in maxnan. +define double @f4(double %dummy, double %val) { +; CHECK-LABEL: f4: +; CHECK: lzdr [[REG:%f[0-9]+]] +; CHECK: wfmaxdb %f0, %f2, [[REG]], 1 +; CHECK: br %r14 + %cmp = fcmp ugt double %val, 0.0 + %ret = select i1 %cmp, double %val, double 0.0 + ret double %ret +} + +; Test the v2f64 maxnum intrinsic. +define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f5: +; CHECK: vfmaxdb %v24, %v26, %v28, 4 +; CHECK: br %r14 + %ret = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %val1, <2 x double> %val2) + ret <2 x double> %ret +} + diff --git a/llvm/test/CodeGen/SystemZ/vec-min-05.ll b/llvm/test/CodeGen/SystemZ/vec-min-05.ll new file mode 100644 index 00000000000..c2d8726addf --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/vec-min-05.ll @@ -0,0 +1,58 @@ +; Test vector minimum on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare double @fmin(double, double) +declare double @llvm.minnum.f64(double, double) +declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>) + +; Test the fmin library function. +define double @f1(double %dummy, double %val1, double %val2) { +; CHECK-LABEL: f1: +; CHECK: wfmindb %f0, %f2, %f4, 4 +; CHECK: br %r14 + %ret = call double @fmin(double %val1, double %val2) readnone + ret double %ret +} + +; Test the f64 minnum intrinsic. +define double @f2(double %dummy, double %val1, double %val2) { +; CHECK-LABEL: f2: +; CHECK: wfmindb %f0, %f2, %f4, 4 +; CHECK: br %r14 + %ret = call double @llvm.minnum.f64(double %val1, double %val2) + ret double %ret +} + +; Test a f64 constant compare/select resulting in minnum. +define double @f3(double %dummy, double %val) { +; CHECK-LABEL: f3: +; CHECK: lzdr [[REG:%f[0-9]+]] +; CHECK: wfmindb %f0, %f2, [[REG]], 4 +; CHECK: br %r14 + %cmp = fcmp olt double %val, 0.0 + %ret = select i1 %cmp, double %val, double 0.0 + ret double %ret +} + +; Test a f64 constant compare/select resulting in minnan. +define double @f4(double %dummy, double %val) { +; CHECK-LABEL: f4: +; CHECK: lzdr [[REG:%f[0-9]+]] +; CHECK: wfmindb %f0, %f2, [[REG]], 1 +; CHECK: br %r14 + %cmp = fcmp ult double %val, 0.0 + %ret = select i1 %cmp, double %val, double 0.0 + ret double %ret +} + +; Test the v2f64 minnum intrinsic. +define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f5: +; CHECK: vfmindb %v24, %v26, %v28, 4 +; CHECK: br %r14 + %ret = call <2 x double> @llvm.minnum.v2f64(<2 x double> %val1, <2 x double> %val2) + ret <2 x double> %ret +} + diff --git a/llvm/test/CodeGen/SystemZ/vec-move-18.ll b/llvm/test/CodeGen/SystemZ/vec-move-18.ll new file mode 100644 index 00000000000..5d3d09d83ef --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/vec-move-18.ll @@ -0,0 +1,24 @@ +; Test insertions of memory values into 0 on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +; Test VLLEZLF. +define <4 x i32> @f1(i32 *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vllezlf %v24, 0(%r2) +; CHECK: br %r14 + %val = load i32, i32 *%ptr + %ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 0 + ret <4 x i32> %ret +} + +; Test VLLEZLF with a float. +define <4 x float> @f2(float *%ptr) { +; CHECK-LABEL: f2: +; CHECK: vllezlf %v24, 0(%r2) +; CHECK: br %r14 + %val = load float, float *%ptr + %ret = insertelement <4 x float> zeroinitializer, float %val, i32 0 + ret <4 x float> %ret +} + diff --git a/llvm/test/CodeGen/SystemZ/vec-mul-05.ll b/llvm/test/CodeGen/SystemZ/vec-mul-05.ll new file mode 100644 index 00000000000..c05437d4923 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/vec-mul-05.ll @@ -0,0 +1,32 @@ +; Test vector negative multiply-and-add on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) + +; Test a v2f64 negative multiply-and-add. +define <2 x double> @f1(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2, <2 x double> %val3) { +; CHECK-LABEL: f1: +; CHECK: vfnmadb %v24, %v26, %v28, %v30 +; CHECK: br %r14 + %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1, + <2 x double> %val2, + <2 x double> %val3) + %negret = fsub <2 x double> <double -0.0, double -0.0>, %ret + ret <2 x double> %negret +} + +; Test a v2f64 negative multiply-and-subtract. +define <2 x double> @f2(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2, <2 x double> %val3) { +; CHECK-LABEL: f2: +; CHECK: vfnmsdb %v24, %v26, %v28, %v30 +; CHECK: br %r14 + %negval3 = fsub <2 x double> <double -0.0, double -0.0>, %val3 + %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1, + <2 x double> %val2, + <2 x double> %negval3) + %negret = fsub <2 x double> <double -0.0, double -0.0>, %ret + ret <2 x double> %negret +} diff --git a/llvm/test/CodeGen/SystemZ/vec-or-03.ll b/llvm/test/CodeGen/SystemZ/vec-or-03.ll new file mode 100644 index 00000000000..010629d880d --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/vec-or-03.ll @@ -0,0 +1,91 @@ +; Test vector OR-NOT on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +; Test a v16i8 OR-NOT. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: voc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <16 x i8> %val2, <i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1> + %ret = or <16 x i8> %val1, %not + ret <16 x i8> %ret +} + +; ...and again with the reverse. +define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: voc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <16 x i8> %val1, <i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1> + %ret = or <16 x i8> %not, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 OR-NOT. +define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f3: +; CHECK: voc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <8 x i16> %val2, <i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1> + %ret = or <8 x i16> %val1, %not + ret <8 x i16> %ret +} + +; ...and again with the reverse. +define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f4: +; CHECK: voc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <8 x i16> %val1, <i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1> + %ret = or <8 x i16> %not, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 OR-NOT. +define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f5: +; CHECK: voc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <4 x i32> %val2, <i32 -1, i32 -1, i32 -1, i32 -1> + %ret = or <4 x i32> %val1, %not + ret <4 x i32> %ret +} + +; ...and again with the reverse. +define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f6: +; CHECK: voc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <4 x i32> %val1, <i32 -1, i32 -1, i32 -1, i32 -1> + %ret = or <4 x i32> %not, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 OR-NOT. +define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f7: +; CHECK: voc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <2 x i64> %val2, <i64 -1, i64 -1> + %ret = or <2 x i64> %val1, %not + ret <2 x i64> %ret +} + +; ...and again with the reverse. +define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f8: +; CHECK: voc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <2 x i64> %val1, <i64 -1, i64 -1> + %ret = or <2 x i64> %not, %val2 + ret <2 x i64> %ret +} diff --git a/llvm/test/CodeGen/SystemZ/vec-xor-02.ll b/llvm/test/CodeGen/SystemZ/vec-xor-02.ll new file mode 100644 index 00000000000..b4b5a96ba25 --- /dev/null +++ b/llvm/test/CodeGen/SystemZ/vec-xor-02.ll @@ -0,0 +1,47 @@ +; Test vector NOT-XOR on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +; Test a v16i8 NOT-XOR. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vnx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <16 x i8> %val1, %val2 + %not = xor <16 x i8> %ret, <i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1, + i8 -1, i8 -1, i8 -1, i8 -1> + ret <16 x i8> %not +} + +; Test a v8i16 NOT-XOR. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vnx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <8 x i16> %val1, %val2 + %not = xor <8 x i16> %ret, <i16 -1, i16 -1, i16 -1, i16 -1, + i16 -1, i16 -1, i16 -1, i16 -1> + ret <8 x i16> %not +} + +; Test a v4i32 NOT-XOR. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vnx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <4 x i32> %val1, %val2 + %not = xor <4 x i32> %ret, <i32 -1, i32 -1, i32 -1, i32 -1> + ret <4 x i32> %not +} + +; Test a v2i64 NOT-XOR. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vnx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <2 x i64> %val1, %val2 + %not = xor <2 x i64> %ret, <i64 -1, i64 -1> + ret <2 x i64> %not +} diff --git a/llvm/test/MC/Disassembler/SystemZ/insns-z14.txt b/llvm/test/MC/Disassembler/SystemZ/insns-z14.txt new file mode 100644 index 00000000000..07d2f233f20 --- /dev/null +++ b/llvm/test/MC/Disassembler/SystemZ/insns-z14.txt @@ -0,0 +1,1594 @@ +# Test z14 instructions that don't have PC-relative operands. +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z14 \ +# RUN: | FileCheck %s + +# CHECK: agh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x38 + +# CHECK: agh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x38 + +# CHECK: agh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x38 + +# CHECK: agh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x38 + +# CHECK: agh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x38 + +# CHECK: agh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x38 + +# CHECK: agh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x38 + +# CHECK: agh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x38 + +# CHECK: agh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x38 + +# CHECK: agh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x38 + +# CHECK: bi -524288 +0xe3 0xf0 0x00 0x00 0x80 0x47 + +# CHECK: bi -1 +0xe3 0xf0 0x0f 0xff 0xff 0x47 + +# CHECK: bi 0 +0xe3 0xf0 0x00 0x00 0x00 0x47 + +# CHECK: bi 1 +0xe3 0xf0 0x00 0x01 0x00 0x47 + +# CHECK: bi 524287 +0xe3 0xf0 0x0f 0xff 0x7f 0x47 + +# CHECK: bi 0(%r1) +0xe3 0xf0 0x10 0x00 0x00 0x47 + +# CHECK: bi 0(%r15) +0xe3 0xf0 0xf0 0x00 0x00 0x47 + +# CHECK: bi 524287(%r1,%r15) +0xe3 0xf1 0xff 0xff 0x7f 0x47 + +# CHECK: bi 524287(%r15,%r1) +0xe3 0xff 0x1f 0xff 0x7f 0x47 + +# CHECK: bic 0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x47 + +# CHECK: bic 0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x47 + +# CHECK: bic 0, 0 +0xe3 0x00 0x00 0x00 0x00 0x47 + +# CHECK: bic 0, 1 +0xe3 0x00 0x00 0x01 0x00 0x47 + +# CHECK: bic 0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x47 + +# CHECK: bic 0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x47 + +# CHECK: bic 0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x47 + +# CHECK: bic 0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x47 + +# CHECK: bic 0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x47 + +# CHECK: bio 0(%r15) +0xe3 0x10 0xf0 0x00 0x00 0x47 + +# CHECK: bih 0(%r15) +0xe3 0x20 0xf0 0x00 0x00 0x47 + +# CHECK: binle 0(%r15) +0xe3 0x30 0xf0 0x00 0x00 0x47 + +# CHECK: bil 0(%r15) +0xe3 0x40 0xf0 0x00 0x00 0x47 + +# CHECK: binhe 0(%r15) +0xe3 0x50 0xf0 0x00 0x00 0x47 + +# CHECK: bilh 0(%r15) +0xe3 0x60 0xf0 0x00 0x00 0x47 + +# CHECK: bine 0(%r15) +0xe3 0x70 0xf0 0x00 0x00 0x47 + +# CHECK: bie 0(%r15) +0xe3 0x80 0xf0 0x00 0x00 0x47 + +# CHECK: binlh 0(%r15) +0xe3 0x90 0xf0 0x00 0x00 0x47 + +# CHECK: bihe 0(%r15) +0xe3 0xa0 0xf0 0x00 0x00 0x47 + +# CHECK: binl 0(%r15) +0xe3 0xb0 0xf0 0x00 0x00 0x47 + +# CHECK: bile 0(%r15) +0xe3 0xc0 0xf0 0x00 0x00 0x47 + +# CHECK: binh 0(%r15) +0xe3 0xd0 0xf0 0x00 0x00 0x47 + +# CHECK: bino 0(%r15) +0xe3 0xe0 0xf0 0x00 0x00 0x47 + +# CHECK: irbm %r0, %r0 +0xb9 0xac 0x00 0x00 + +# CHECK: irbm %r0, %r15 +0xb9 0xac 0x00 0x0f + +# CHECK: irbm %r15, %r0 +0xb9 0xac 0x00 0xf0 + +# CHECK: irbm %r7, %r8 +0xb9 0xac 0x00 0x78 + +# CHECK: irbm %r15, %r15 +0xb9 0xac 0x00 0xff + +# CHECK: kma %r2, %r2, %r2 +0xb9 0x29 0x20 0x22 + +# CHECK: kma %r2, %r8, %r14 +0xb9 0x29 0x80 0x2e + +# CHECK: kma %r14, %r8, %r2 +0xb9 0x29 0x80 0xe2 + +# CHECK: kma %r6, %r8, %r10 +0xb9 0x29 0x80 0x6a + +# CHECK: lgg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x4c + +# CHECK: lgg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x4c + +# CHECK: lgg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x4c + +# CHECK: lgg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x4c + +# CHECK: lgg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x4c + +# CHECK: lgg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x4c + +# CHECK: lgg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x4c + +# CHECK: lgg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x4c + +# CHECK: lgg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x4c + +# CHECK: lgg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x4c + +# CHECK: lgsc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x4d + +# CHECK: lgsc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x4d + +# CHECK: lgsc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x4d + +# CHECK: lgsc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x4d + +# CHECK: lgsc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x4d + +# CHECK: lgsc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x4d + +# CHECK: lgsc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x4d + +# CHECK: lgsc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x4d + +# CHECK: lgsc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x4d + +# CHECK: llgfsg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x48 + +# CHECK: llgfsg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x48 + +# CHECK: llgfsg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x48 + +# CHECK: llgfsg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x48 + +# CHECK: llgfsg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x48 + +# CHECK: llgfsg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x48 + +# CHECK: llgfsg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x48 + +# CHECK: llgfsg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x48 + +# CHECK: llgfsg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x48 + +# CHECK: llgfsg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x48 + +# CHECK: mg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x84 + +# CHECK: mg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x84 + +# CHECK: mg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x84 + +# CHECK: mg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x84 + +# CHECK: mg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x84 + +# CHECK: mg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x84 + +# CHECK: mg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x84 + +# CHECK: mg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x84 + +# CHECK: mg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x84 + +# CHECK: mg %r14, 0 +0xe3 0xe0 0x00 0x00 0x00 0x84 + +# CHECK: mgh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x3c + +# CHECK: mgh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x3c + +# CHECK: mgh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x3c + +# CHECK: mgh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x3c + +# CHECK: mgh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x3c + +# CHECK: mgh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x3c + +# CHECK: mgh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x3c + +# CHECK: mgh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x3c + +# CHECK: mgh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x3c + +# CHECK: mgh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x3c + +# CHECK: mgrk %r0, %r0, %r0 +0xb9 0xec 0x00 0x00 + +# CHECK: mgrk %r0, %r0, %r15 +0xb9 0xec 0xf0 0x00 + +# CHECK: mgrk %r0, %r15, %r0 +0xb9 0xec 0x00 0x0f + +# CHECK: mgrk %r14, %r0, %r0 +0xb9 0xec 0x00 0xe0 + +# CHECK: mgrk %r6, %r8, %r9 +0xb9 0xec 0x90 0x68 + +# CHECK: msc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x53 + +# CHECK: msc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x53 + +# CHECK: msc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x53 + +# CHECK: msc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x53 + +# CHECK: msc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x53 + +# CHECK: msc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x53 + +# CHECK: msc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x53 + +# CHECK: msc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x53 + +# CHECK: msc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x53 + +# CHECK: msc %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x53 + +# CHECK: msgc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x83 + +# CHECK: msgc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x83 + +# CHECK: msgc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x83 + +# CHECK: msgc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x83 + +# CHECK: msgc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x83 + +# CHECK: msgc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x83 + +# CHECK: msgc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x83 + +# CHECK: msgc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x83 + +# CHECK: msgc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x83 + +# CHECK: msgc %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x83 + +# CHECK: msrkc %r0, %r0, %r0 +0xb9 0xfd 0x00 0x00 + +# CHECK: msrkc %r0, %r0, %r15 +0xb9 0xfd 0xf0 0x00 + +# CHECK: msrkc %r0, %r15, %r0 +0xb9 0xfd 0x00 0x0f + +# CHECK: msrkc %r15, %r0, %r0 +0xb9 0xfd 0x00 0xf0 + +# CHECK: msrkc %r7, %r8, %r9 +0xb9 0xfd 0x90 0x78 + +# CHECK: msgrkc %r0, %r0, %r0 +0xb9 0xed 0x00 0x00 + +# CHECK: msgrkc %r0, %r0, %r15 +0xb9 0xed 0xf0 0x00 + +# CHECK: msgrkc %r0, %r15, %r0 +0xb9 0xed 0x00 0x0f + +# CHECK: msgrkc %r15, %r0, %r0 +0xb9 0xed 0x00 0xf0 + +# CHECK: msgrkc %r7, %r8, %r9 +0xb9 0xed 0x90 0x78 + +# CHECK: sgh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x39 + +# CHECK: sgh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x39 + +# CHECK: sgh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x39 + +# CHECK: sgh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x39 + +# CHECK: sgh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x39 + +# CHECK: sgh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x39 + +# CHECK: sgh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x39 + +# CHECK: sgh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x39 + +# CHECK: sgh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x39 + +# CHECK: sgh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x39 + +# CHECK: stgsc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x49 + +# CHECK: stgsc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x49 + +# CHECK: stgsc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x49 + +# CHECK: stgsc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x49 + +# CHECK: stgsc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x49 + +# CHECK: stgsc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x49 + +# CHECK: stgsc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x49 + +# CHECK: stgsc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x49 + +# CHECK: stgsc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x49 + +# CHECK: vap %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x71 + +# CHECK: vap %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x71 + +# CHECK: vap %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x71 + +# CHECK: vap %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x71 + +# CHECK: vap %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x71 + +# CHECK: vap %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x71 + +# CHECK: vap %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x71 + +# CHECK: vbperm %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x85 + +# CHECK: vbperm %v0, %v0, %v15 +0xe7 0x00 0xf0 0x00 0x00 0x85 + +# CHECK: vbperm %v0, %v0, %v31 +0xe7 0x00 0xf0 0x00 0x02 0x85 + +# CHECK: vbperm %v0, %v15, %v0 +0xe7 0x0f 0x00 0x00 0x00 0x85 + +# CHECK: vbperm %v0, %v31, %v0 +0xe7 0x0f 0x00 0x00 0x04 0x85 + +# CHECK: vbperm %v15, %v0, %v0 +0xe7 0xf0 0x00 0x00 0x00 0x85 + +# CHECK: vbperm %v31, %v0, %v0 +0xe7 0xf0 0x00 0x00 0x08 0x85 + +# CHECK: vbperm %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x85 + +# CHECK: vcp %v0, %v0, 0 +0xe6 0x00 0x00 0x00 0x00 0x77 + +# CHECK: vcp %v0, %v0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x77 + +# CHECK: vcp %v15, %v0, 0 +0xe6 0x0f 0x00 0x00 0x00 0x77 + +# CHECK: vcp %v31, %v0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x77 + +# CHECK: vcp %v0, %v15, 0 +0xe6 0x00 0xf0 0x00 0x00 0x77 + +# CHECK: vcp %v0, %v31, 0 +0xe6 0x00 0xf0 0x00 0x02 0x77 + +# CHECK: vcp %v3, %v18, 4 +0xe6 0x03 0x20 0x40 0x02 0x77 + +# CHECK: vcvb %r0, %v0, 0 +0xe6 0x00 0x00 0x00 0x00 0x50 + +# CHECK: vcvb %r0, %v0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x50 + +# CHECK: vcvb %r15, %v0, 0 +0xe6 0xf0 0x00 0x00 0x00 0x50 + +# CHECK: vcvb %r0, %v15, 0 +0xe6 0x0f 0x00 0x00 0x00 0x50 + +# CHECK: vcvb %r0, %v31, 0 +0xe6 0x0f 0x00 0x00 0x04 0x50 + +# CHECK: vcvb %r3, %v18, 4 +0xe6 0x32 0x00 0x40 0x04 0x50 + +# CHECK: vcvbg %r0, %v0, 0 +0xe6 0x00 0x00 0x00 0x00 0x52 + +# CHECK: vcvbg %r0, %v0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x52 + +# CHECK: vcvbg %r15, %v0, 0 +0xe6 0xf0 0x00 0x00 0x00 0x52 + +# CHECK: vcvbg %r0, %v15, 0 +0xe6 0x0f 0x00 0x00 0x00 0x52 + +# CHECK: vcvbg %r0, %v31, 0 +0xe6 0x0f 0x00 0x00 0x04 0x52 + +# CHECK: vcvbg %r3, %v18, 4 +0xe6 0x32 0x00 0x40 0x04 0x52 + +# CHECK: vcvd %v0, %r0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x58 + +# CHECK: vcvd %v0, %r0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x58 + +# CHECK: vcvd %v0, %r0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x58 + +# CHECK: vcvd %v0, %r15, 0, 0 +0xe6 0x0f 0x00 0x00 0x00 0x58 + +# CHECK: vcvd %v15, %r0, 0, 0 +0xe6 0xf0 0x00 0x00 0x00 0x58 + +# CHECK: vcvd %v31, %r0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x58 + +# CHECK: vcvd %v18, %r9, 52, 11 +0xe6 0x29 0x00 0xb3 0x48 0x58 + +# CHECK: vcvdg %v0, %r0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x5a + +# CHECK: vcvdg %v0, %r0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x5a + +# CHECK: vcvdg %v0, %r0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x5a + +# CHECK: vcvdg %v0, %r15, 0, 0 +0xe6 0x0f 0x00 0x00 0x00 0x5a + +# CHECK: vcvdg %v15, %r0, 0, 0 +0xe6 0xf0 0x00 0x00 0x00 0x5a + +# CHECK: vcvdg %v31, %r0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x5a + +# CHECK: vcvdg %v18, %r9, 52, 11 +0xe6 0x29 0x00 0xb3 0x48 0x5a + +# CHECK: vdp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x7a + +# CHECK: vdp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x7a + +# CHECK: vdp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x7a + +# CHECK: vdp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x7a + +# CHECK: vdp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x7a + +# CHECK: vdp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x7a + +# CHECK: vdp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x7a + +# CHECK: vfkedb %v0, %v0, %v0 +0xe7 0x00 0x00 0x04 0x30 0xe8 + +# CHECK: vfkedb %v0, %v0, %v31 +0xe7 0x00 0xf0 0x04 0x32 0xe8 + +# CHECK: vfkedb %v0, %v31, %v0 +0xe7 0x0f 0x00 0x04 0x34 0xe8 + +# CHECK: vfkedb %v31, %v0, %v0 +0xe7 0xf0 0x00 0x04 0x38 0xe8 + +# CHECK: vfkedb %v18, %v3, %v20 +0xe7 0x23 0x40 0x04 0x3a 0xe8 + +# CHECK: vfkedbs %v0, %v0, %v0 +0xe7 0x00 0x00 0x14 0x30 0xe8 + +# CHECK: vfkedbs %v0, %v0, %v31 +0xe7 0x00 0xf0 0x14 0x32 0xe8 + +# CHECK: vfkedbs %v0, %v31, %v0 +0xe7 0x0f 0x00 0x14 0x34 0xe8 + +# CHECK: vfkedbs %v31, %v0, %v0 +0xe7 0xf0 0x00 0x14 0x38 0xe8 + +# CHECK: vfkedbs %v18, %v3, %v20 +0xe7 0x23 0x40 0x14 0x3a 0xe8 + +# CHECK: vfkhdb %v0, %v0, %v0 +0xe7 0x00 0x00 0x04 0x30 0xeb + +# CHECK: vfkhdb %v0, %v0, %v31 +0xe7 0x00 0xf0 0x04 0x32 0xeb + +# CHECK: vfkhdb %v0, %v31, %v0 +0xe7 0x0f 0x00 0x04 0x34 0xeb + +# CHECK: vfkhdb %v31, %v0, %v0 +0xe7 0xf0 0x00 0x04 0x38 0xeb + +# CHECK: vfkhdb %v18, %v3, %v20 +0xe7 0x23 0x40 0x04 0x3a 0xeb + +# CHECK: vfkhdbs %v0, %v0, %v0 +0xe7 0x00 0x00 0x14 0x30 0xeb + +# CHECK: vfkhdbs %v0, %v0, %v31 +0xe7 0x00 0xf0 0x14 0x32 0xeb + +# CHECK: vfkhdbs %v0, %v31, %v0 +0xe7 0x0f 0x00 0x14 0x34 0xeb + +# CHECK: vfkhdbs %v31, %v0, %v0 +0xe7 0xf0 0x00 0x14 0x38 0xeb + +# CHECK: vfkhdbs %v18, %v3, %v20 +0xe7 0x23 0x40 0x14 0x3a 0xeb + +# CHECK: vfkhedb %v0, %v0, %v0 +0xe7 0x00 0x00 0x04 0x30 0xea + +# CHECK: vfkhedb %v0, %v0, %v31 +0xe7 0x00 0xf0 0x04 0x32 0xea + +# CHECK: vfkhedb %v0, %v31, %v0 +0xe7 0x0f 0x00 0x04 0x34 0xea + +# CHECK: vfkhedb %v31, %v0, %v0 +0xe7 0xf0 0x00 0x04 0x38 0xea + +# CHECK: vfkhedb %v18, %v3, %v20 +0xe7 0x23 0x40 0x04 0x3a 0xea + +# CHECK: vfkhedbs %v0, %v0, %v0 +0xe7 0x00 0x00 0x14 0x30 0xea + +# CHECK: vfkhedbs %v0, %v0, %v31 +0xe7 0x00 0xf0 0x14 0x32 0xea + +# CHECK: vfkhedbs %v0, %v31, %v0 +0xe7 0x0f 0x00 0x14 0x34 0xea + +# CHECK: vfkhedbs %v31, %v0, %v0 +0xe7 0xf0 0x00 0x14 0x38 0xea + +# CHECK: vfkhedbs %v18, %v3, %v20 +0xe7 0x23 0x40 0x14 0x3a 0xea + +# CHECK: vfmax %v0, %v0, %v0, 0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0xef + +# CHECK: vfmax %v0, %v0, %v0, 15, 0, 0 +0xe7 0x00 0x00 0x00 0xf0 0xef + +# CHECK: vfmax %v0, %v0, %v0, 0, 15, 0 +0xe7 0x00 0x00 0x0f 0x00 0xef + +# CHECK: vfmax %v0, %v0, %v0, 0, 0, 4 +0xe7 0x00 0x00 0x40 0x00 0xef + +# CHECK: vfmax %v0, %v0, %v31, 0, 0, 0 +0xe7 0x00 0xf0 0x00 0x02 0xef + +# CHECK: vfmax %v0, %v31, %v0, 0, 0, 0 +0xe7 0x0f 0x00 0x00 0x04 0xef + +# CHECK: vfmax %v31, %v0, %v0, 0, 0, 0 +0xe7 0xf0 0x00 0x00 0x08 0xef + +# CHECK: vfmax %v18, %v3, %v20, 11, 9, 12 +0xe7 0x23 0x40 0xc9 0xba 0xef + +# CHECK: vfmaxdb %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0xef + +# CHECK: vfmaxdb %v0, %v0, %v0, 4 +0xe7 0x00 0x00 0x40 0x30 0xef + +# CHECK: vfmaxdb %v0, %v0, %v31, 0 +0xe7 0x00 0xf0 0x00 0x32 0xef + +# CHECK: vfmaxdb %v0, %v31, %v0, 0 +0xe7 0x0f 0x00 0x00 0x34 0xef + +# CHECK: vfmaxdb %v31, %v0, %v0, 0 +0xe7 0xf0 0x00 0x00 0x38 0xef + +# CHECK: vfmaxdb %v18, %v3, %v20, 12 +0xe7 0x23 0x40 0xc0 0x3a 0xef + +# CHECK: vfmin %v0, %v0, %v0, 0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0xee + +# CHECK: vfmin %v0, %v0, %v0, 15, 0, 0 +0xe7 0x00 0x00 0x00 0xf0 0xee + +# CHECK: vfmin %v0, %v0, %v0, 0, 15, 0 +0xe7 0x00 0x00 0x0f 0x00 0xee + +# CHECK: vfmin %v0, %v0, %v0, 0, 0, 4 +0xe7 0x00 0x00 0x40 0x00 0xee + +# CHECK: vfmin %v0, %v0, %v31, 0, 0, 0 +0xe7 0x00 0xf0 0x00 0x02 0xee + +# CHECK: vfmin %v0, %v31, %v0, 0, 0, 0 +0xe7 0x0f 0x00 0x00 0x04 0xee + +# CHECK: vfmin %v31, %v0, %v0, 0, 0, 0 +0xe7 0xf0 0x00 0x00 0x08 0xee + +# CHECK: vfmin %v18, %v3, %v20, 11, 9, 12 +0xe7 0x23 0x40 0xc9 0xba 0xee + +# CHECK: vfmindb %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0xee + +# CHECK: vfmindb %v0, %v0, %v0, 4 +0xe7 0x00 0x00 0x40 0x30 0xee + +# CHECK: vfmindb %v0, %v0, %v31, 0 +0xe7 0x00 0xf0 0x00 0x32 0xee + +# CHECK: vfmindb %v0, %v31, %v0, 0 +0xe7 0x0f 0x00 0x00 0x34 0xee + +# CHECK: vfmindb %v31, %v0, %v0, 0 +0xe7 0xf0 0x00 0x00 0x38 0xee + +# CHECK: vfmindb %v18, %v3, %v20, 12 +0xe7 0x23 0x40 0xc0 0x3a 0xee + +# CHECK: vfnma %v0, %v0, %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x9f + +# CHECK: vfnma %v0, %v0, %v0, %v0, 0, 15 +0xe7 0x00 0x0f 0x00 0x00 0x9f + +# CHECK: vfnma %v0, %v0, %v0, %v0, 15, 0 +0xe7 0x00 0x00 0x0f 0x00 0x9f + +# CHECK: vfnma %v0, %v0, %v0, %v31, 0, 0 +0xe7 0x00 0x00 0x00 0xf1 0x9f + +# CHECK: vfnma %v0, %v0, %v31, %v0, 0, 0 +0xe7 0x00 0xf0 0x00 0x02 0x9f + +# CHECK: vfnma %v0, %v31, %v0, %v0, 0, 0 +0xe7 0x0f 0x00 0x00 0x04 0x9f + +# CHECK: vfnma %v31, %v0, %v0, %v0, 0, 0 +0xe7 0xf0 0x00 0x00 0x08 0x9f + +# CHECK: vfnma %v13, %v17, %v21, %v25, 9, 11 +0xe7 0xd1 0x5b 0x09 0x97 0x9f + +# CHECK: vfnmadb %v0, %v0, %v0, %v0 +0xe7 0x00 0x03 0x00 0x00 0x9f + +# CHECK: vfnmadb %v0, %v0, %v0, %v31 +0xe7 0x00 0x03 0x00 0xf1 0x9f + +# CHECK: vfnmadb %v0, %v0, %v31, %v0 +0xe7 0x00 0xf3 0x00 0x02 0x9f + +# CHECK: vfnmadb %v0, %v31, %v0, %v0 +0xe7 0x0f 0x03 0x00 0x04 0x9f + +# CHECK: vfnmadb %v31, %v0, %v0, %v0 +0xe7 0xf0 0x03 0x00 0x08 0x9f + +# CHECK: vfnmadb %v13, %v17, %v21, %v25 +0xe7 0xd1 0x53 0x00 0x97 0x9f + +# CHECK: vfnms %v0, %v0, %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x9e + +# CHECK: vfnms %v0, %v0, %v0, %v0, 0, 15 +0xe7 0x00 0x0f 0x00 0x00 0x9e + +# CHECK: vfnms %v0, %v0, %v0, %v0, 15, 0 +0xe7 0x00 0x00 0x0f 0x00 0x9e + +# CHECK: vfnms %v0, %v0, %v0, %v31, 0, 0 +0xe7 0x00 0x00 0x00 0xf1 0x9e + +# CHECK: vfnms %v0, %v0, %v31, %v0, 0, 0 +0xe7 0x00 0xf0 0x00 0x02 0x9e + +# CHECK: vfnms %v0, %v31, %v0, %v0, 0, 0 +0xe7 0x0f 0x00 0x00 0x04 0x9e + +# CHECK: vfnms %v31, %v0, %v0, %v0, 0, 0 +0xe7 0xf0 0x00 0x00 0x08 0x9e + +# CHECK: vfnms %v13, %v17, %v21, %v25, 9, 11 +0xe7 0xd1 0x5b 0x09 0x97 0x9e + +# CHECK: vfnmsdb %v0, %v0, %v0, %v0 +0xe7 0x00 0x03 0x00 0x00 0x9e + +# CHECK: vfnmsdb %v0, %v0, %v0, %v31 +0xe7 0x00 0x03 0x00 0xf1 0x9e + +# CHECK: vfnmsdb %v0, %v0, %v31, %v0 +0xe7 0x00 0xf3 0x00 0x02 0x9e + +# CHECK: vfnmsdb %v0, %v31, %v0, %v0 +0xe7 0x0f 0x03 0x00 0x04 0x9e + +# CHECK: vfnmsdb %v31, %v0, %v0, %v0 +0xe7 0xf0 0x03 0x00 0x08 0x9e + +# CHECK: vfnmsdb %v13, %v17, %v21, %v25 +0xe7 0xd1 0x53 0x00 0x97 0x9e + +# CHECK: vlip %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x49 + +# CHECK: vlip %v0, 0, 15 +0xe6 0x00 0x00 0x00 0xf0 0x49 + +# CHECK: vlip %v0, 65535, 0 +0xe6 0x00 0xff 0xff 0x00 0x49 + +# CHECK: vlip %v15, 0, 0 +0xe6 0xf0 0x00 0x00 0x00 0x49 + +# CHECK: vlip %v31, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x49 + +# CHECK: vlip %v17, 4660, 7 +0xe6 0x10 0x12 0x34 0x78 0x49 + +# CHECK: vllezlf %v0, 0 +0xe7 0x00 0x00 0x00 0x60 0x04 + +# CHECK: vllezlf %v0, 4095 +0xe7 0x00 0x0f 0xff 0x60 0x04 + +# CHECK: vllezlf %v0, 0(%r15) +0xe7 0x00 0xf0 0x00 0x60 0x04 + +# CHECK: vllezlf %v0, 0(%r15,%r1) +0xe7 0x0f 0x10 0x00 0x60 0x04 + +# CHECK: vllezlf %v15, 0 +0xe7 0xf0 0x00 0x00 0x60 0x04 + +# CHECK: vllezlf %v31, 0 +0xe7 0xf0 0x00 0x00 0x68 0x04 + +# CHECK: vllezlf %v18, 1383(%r3,%r4) +0xe7 0x23 0x45 0x67 0x68 0x04 + +# CHECK: vlrl %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x35 + +# CHECK: vlrl %v0, 4095, 0 +0xe6 0x00 0x0f 0xff 0x00 0x35 + +# CHECK: vlrl %v0, 0(%r15), 0 +0xe6 0x00 0xf0 0x00 0x00 0x35 + +# CHECK: vlrl %v0, 0, 255 +0xe6 0xff 0x00 0x00 0x00 0x35 + +# CHECK: vlrl %v15, 0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x35 + +# CHECK: vlrl %v31, 0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x35 + +# CHECK: vlrl %v18, 1383(%r4), 3 +0xe6 0x03 0x45 0x67 0x21 0x35 + +# CHECK: vlrlr %v0, %r0, 0 +0xe6 0x00 0x00 0x00 0x00 0x37 + +# CHECK: vlrlr %v0, %r0, 4095 +0xe6 0x00 0x0f 0xff 0x00 0x37 + +# CHECK: vlrlr %v0, %r0, 0(%r15) +0xe6 0x00 0xf0 0x00 0x00 0x37 + +# CHECK: vlrlr %v0, %r15, 0 +0xe6 0x0f 0x00 0x00 0x00 0x37 + +# CHECK: vlrlr %v15, %r0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x37 + +# CHECK: vlrlr %v31, %r0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x37 + +# CHECK: vlrlr %v18, %r3, 1383(%r4) +0xe6 0x03 0x45 0x67 0x21 0x37 + +# CHECK: vmsl %v0, %v0, %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0xb8 + +# CHECK: vmsl %v0, %v0, %v0, %v0, 15, 0 +0xe7 0x00 0x0f 0x00 0x00 0xb8 + +# CHECK: vmsl %v0, %v0, %v0, %v0, 0, 12 +0xe7 0x00 0x00 0xc0 0x00 0xb8 + +# CHECK: vmsl %v0, %v0, %v0, %v15, 0, 0 +0xe7 0x00 0x00 0x00 0xf0 0xb8 + +# CHECK: vmsl %v0, %v0, %v0, %v31, 0, 0 +0xe7 0x00 0x00 0x00 0xf1 0xb8 + +# CHECK: vmsl %v0, %v0, %v15, %v0, 0, 0 +0xe7 0x00 0xf0 0x00 0x00 0xb8 + +# CHECK: vmsl %v0, %v0, %v31, %v0, 0, 0 +0xe7 0x00 0xf0 0x00 0x02 0xb8 + +# CHECK: vmsl %v0, %v15, %v0, %v0, 0, 0 +0xe7 0x0f 0x00 0x00 0x00 0xb8 + +# CHECK: vmsl %v0, %v31, %v0, %v0, 0, 0 +0xe7 0x0f 0x00 0x00 0x04 0xb8 + +# CHECK: vmsl %v15, %v0, %v0, %v0, 0, 0 +0xe7 0xf0 0x00 0x00 0x00 0xb8 + +# CHECK: vmsl %v31, %v0, %v0, %v0, 0, 0 +0xe7 0xf0 0x00 0x00 0x08 0xb8 + +# CHECK: vmsl %v18, %v3, %v20, %v5, 0, 4 +0xe7 0x23 0x40 0x40 0x5a 0xb8 + +# CHECK: vmsl %v18, %v3, %v20, %v5, 11, 8 +0xe7 0x23 0x4b 0x80 0x5a 0xb8 + +# CHECK: vmslg %v0, %v0, %v0, %v0, 0 +0xe7 0x00 0x03 0x00 0x00 0xb8 + +# CHECK: vmslg %v0, %v0, %v0, %v0, 12 +0xe7 0x00 0x03 0xc0 0x00 0xb8 + +# CHECK: vmslg %v0, %v0, %v0, %v15, 0 +0xe7 0x00 0x03 0x00 0xf0 0xb8 + +# CHECK: vmslg %v0, %v0, %v0, %v31, 0 +0xe7 0x00 0x03 0x00 0xf1 0xb8 + +# CHECK: vmslg %v0, %v0, %v15, %v0, 0 +0xe7 0x00 0xf3 0x00 0x00 0xb8 + +# CHECK: vmslg %v0, %v0, %v31, %v0, 0 +0xe7 0x00 0xf3 0x00 0x02 0xb8 + +# CHECK: vmslg %v0, %v15, %v0, %v0, 0 +0xe7 0x0f 0x03 0x00 0x00 0xb8 + +# CHECK: vmslg %v0, %v31, %v0, %v0, 0 +0xe7 0x0f 0x03 0x00 0x04 0xb8 + +# CHECK: vmslg %v15, %v0, %v0, %v0, 0 +0xe7 0xf0 0x03 0x00 0x00 0xb8 + +# CHECK: vmslg %v31, %v0, %v0, %v0, 0 +0xe7 0xf0 0x03 0x00 0x08 0xb8 + +# CHECK: vmslg %v18, %v3, %v20, %v5, 4 +0xe7 0x23 0x43 0x40 0x5a 0xb8 + +# CHECK: vmslg %v18, %v3, %v20, %v5, 8 +0xe7 0x23 0x43 0x80 0x5a 0xb8 + +# CHECK: vmp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x78 + +# CHECK: vmp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x78 + +# CHECK: vmp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x78 + +# CHECK: vmp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x78 + +# CHECK: vmp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x78 + +# CHECK: vmp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x78 + +# CHECK: vmp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x78 + +# CHECK: vmsp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x79 + +# CHECK: vmsp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x79 + +# CHECK: vmsp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x79 + +# CHECK: vmsp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x79 + +# CHECK: vmsp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x79 + +# CHECK: vmsp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x79 + +# CHECK: vmsp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x79 + +# CHECK: vnn %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x6e + +# CHECK: vnn %v0, %v0, %v31 +0xe7 0x00 0xf0 0x00 0x02 0x6e + +# CHECK: vnn %v0, %v31, %v0 +0xe7 0x0f 0x00 0x00 0x04 0x6e + +# CHECK: vnn %v31, %v0, %v0 +0xe7 0xf0 0x00 0x00 0x08 0x6e + +# CHECK: vnn %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x6e + +# CHECK: vnx %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x6c + +# CHECK: vnx %v0, %v0, %v31 +0xe7 0x00 0xf0 0x00 0x02 0x6c + +# CHECK: vnx %v0, %v31, %v0 +0xe7 0x0f 0x00 0x00 0x04 0x6c + +# CHECK: vnx %v31, %v0, %v0 +0xe7 0xf0 0x00 0x00 0x08 0x6c + +# CHECK: vnx %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x6c + +# CHECK: voc %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x6f + +# CHECK: voc %v0, %v0, %v31 +0xe7 0x00 0xf0 0x00 0x02 0x6f + +# CHECK: voc %v0, %v31, %v0 +0xe7 0x0f 0x00 0x00 0x04 0x6f + +# CHECK: voc %v31, %v0, %v0 +0xe7 0xf0 0x00 0x00 0x08 0x6f + +# CHECK: voc %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x6f + +# CHECK: vpkz %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x34 + +# CHECK: vpkz %v0, 4095, 0 +0xe6 0x00 0x0f 0xff 0x00 0x34 + +# CHECK: vpkz %v0, 0(%r15), 0 +0xe6 0x00 0xf0 0x00 0x00 0x34 + +# CHECK: vpkz %v0, 0, 255 +0xe6 0xff 0x00 0x00 0x00 0x34 + +# CHECK: vpkz %v15, 0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x34 + +# CHECK: vpkz %v31, 0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x34 + +# CHECK: vpkz %v18, 1383(%r4), 3 +0xe6 0x03 0x45 0x67 0x21 0x34 + +# CHECK: vpopctb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x50 + +# CHECK: vpopctb %v0, %v15 +0xe7 0x0f 0x00 0x00 0x00 0x50 + +# CHECK: vpopctb %v0, %v31 +0xe7 0x0f 0x00 0x00 0x04 0x50 + +# CHECK: vpopctb %v15, %v0 +0xe7 0xf0 0x00 0x00 0x00 0x50 + +# CHECK: vpopctb %v31, %v0 +0xe7 0xf0 0x00 0x00 0x08 0x50 + +# CHECK: vpopctb %v14, %v17 +0xe7 0xe1 0x00 0x00 0x04 0x50 + +# CHECK: vpopctf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x50 + +# CHECK: vpopctf %v0, %v15 +0xe7 0x0f 0x00 0x00 0x20 0x50 + +# CHECK: vpopctf %v0, %v31 +0xe7 0x0f 0x00 0x00 0x24 0x50 + +# CHECK: vpopctf %v15, %v0 +0xe7 0xf0 0x00 0x00 0x20 0x50 + +# CHECK: vpopctf %v31, %v0 +0xe7 0xf0 0x00 0x00 0x28 0x50 + +# CHECK: vpopctf %v14, %v17 +0xe7 0xe1 0x00 0x00 0x24 0x50 + +# CHECK: vpopctg %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x50 + +# CHECK: vpopctg %v0, %v15 +0xe7 0x0f 0x00 0x00 0x30 0x50 + +# CHECK: vpopctg %v0, %v31 +0xe7 0x0f 0x00 0x00 0x34 0x50 + +# CHECK: vpopctg %v15, %v0 +0xe7 0xf0 0x00 0x00 0x30 0x50 + +# CHECK: vpopctg %v31, %v0 +0xe7 0xf0 0x00 0x00 0x38 0x50 + +# CHECK: vpopctg %v14, %v17 +0xe7 0xe1 0x00 0x00 0x34 0x50 + +# CHECK: vpopcth %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x50 + +# CHECK: vpopcth %v0, %v15 +0xe7 0x0f 0x00 0x00 0x10 0x50 + +# CHECK: vpopcth %v0, %v31 +0xe7 0x0f 0x00 0x00 0x14 0x50 + +# CHECK: vpopcth %v15, %v0 +0xe7 0xf0 0x00 0x00 0x10 0x50 + +# CHECK: vpopcth %v31, %v0 +0xe7 0xf0 0x00 0x00 0x18 0x50 + +# CHECK: vpopcth %v14, %v17 +0xe7 0xe1 0x00 0x00 0x14 0x50 + +# CHECK: vpsop %v0, %v0, 0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x5b + +# CHECK: vpsop %v0, %v0, 0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x5b + +# CHECK: vpsop %v0, %v0, 0, 255, 0 +0xe6 0x00 0xff 0x00 0x00 0x5b + +# CHECK: vpsop %v0, %v0, 255, 0, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x5b + +# CHECK: vpsop %v0, %v31, 0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x5b + +# CHECK: vpsop %v31, %v0, 0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x5b + +# CHECK: vpsop %v13, %v17, 52, 121, 11 +0xe6 0xd1 0x79 0xb3 0x44 0x5b + +# CHECK: vrp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x7b + +# CHECK: vrp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x7b + +# CHECK: vrp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x7b + +# CHECK: vrp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x7b + +# CHECK: vrp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x7b + +# CHECK: vrp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x7b + +# CHECK: vrp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x7b + +# CHECK: vsdp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x7e + +# CHECK: vsdp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x7e + +# CHECK: vsdp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x7e + +# CHECK: vsdp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x7e + +# CHECK: vsdp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x7e + +# CHECK: vsdp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x7e + +# CHECK: vsdp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x7e + +# CHECK: vsp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x73 + +# CHECK: vsp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x73 + +# CHECK: vsp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x73 + +# CHECK: vsp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x73 + +# CHECK: vsp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x73 + +# CHECK: vsp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x73 + +# CHECK: vsp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x73 + +# CHECK: vsrp %v0, %v0, 0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x59 + +# CHECK: vsrp %v0, %v0, 0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x59 + +# CHECK: vsrp %v0, %v0, 0, 255, 0 +0xe6 0x00 0xff 0x00 0x00 0x59 + +# CHECK: vsrp %v0, %v0, 255, 0, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x59 + +# CHECK: vsrp %v0, %v31, 0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x59 + +# CHECK: vsrp %v31, %v0, 0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x59 + +# CHECK: vsrp %v13, %v17, 52, 121, 11 +0xe6 0xd1 0x79 0xb3 0x44 0x59 + +# CHECK: vstrl %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x3d + +# CHECK: vstrl %v0, 4095, 0 +0xe6 0x00 0x0f 0xff 0x00 0x3d + +# CHECK: vstrl %v0, 0(%r15), 0 +0xe6 0x00 0xf0 0x00 0x00 0x3d + +# CHECK: vstrl %v0, 0, 255 +0xe6 0xff 0x00 0x00 0x00 0x3d + +# CHECK: vstrl %v15, 0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x3d + +# CHECK: vstrl %v31, 0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x3d + +# CHECK: vstrl %v18, 1383(%r4), 3 +0xe6 0x03 0x45 0x67 0x21 0x3d + +# CHECK: vstrlr %v0, %r0, 0 +0xe6 0x00 0x00 0x00 0x00 0x3f + +# CHECK: vstrlr %v0, %r0, 4095 +0xe6 0x00 0x0f 0xff 0x00 0x3f + +# CHECK: vstrlr %v0, %r0, 0(%r15) +0xe6 0x00 0xf0 0x00 0x00 0x3f + +# CHECK: vstrlr %v0, %r15, 0 +0xe6 0x0f 0x00 0x00 0x00 0x3f + +# CHECK: vstrlr %v15, %r0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x3f + +# CHECK: vstrlr %v31, %r0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x3f + +# CHECK: vstrlr %v18, %r3, 1383(%r4) +0xe6 0x03 0x45 0x67 0x21 0x3f + +# CHECK: vtp %v0 +0xe6 0x00 0x00 0x00 0x00 0x5f + +# CHECK: vtp %v15 +0xe6 0x0f 0x00 0x00 0x00 0x5f + +# CHECK: vtp %v31 +0xe6 0x0f 0x00 0x00 0x04 0x5f + +# CHECK: vupkz %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x3c + +# CHECK: vupkz %v0, 4095, 0 +0xe6 0x00 0x0f 0xff 0x00 0x3c + +# CHECK: vupkz %v0, 0(%r15), 0 +0xe6 0x00 0xf0 0x00 0x00 0x3c + +# CHECK: vupkz %v0, 0, 255 +0xe6 0xff 0x00 0x00 0x00 0x3c + +# CHECK: vupkz %v15, 0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x3c + +# CHECK: vupkz %v31, 0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x3c + +# CHECK: vupkz %v18, 1383(%r4), 3 +0xe6 0x03 0x45 0x67 0x21 0x3c + +# CHECK: wfkedb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xe8 + +# CHECK: wfkedb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xe8 + +# CHECK: wfkedb %f0, %f0, %v31 +0xe7 0x00 0xf0 0x0c 0x32 0xe8 + +# CHECK: wfkedb %f0, %v31, %f0 +0xe7 0x0f 0x00 0x0c 0x34 0xe8 + +# CHECK: wfkedb %v31, %f0, %f0 +0xe7 0xf0 0x00 0x0c 0x38 0xe8 + +# CHECK: wfkedb %v18, %f3, %v20 +0xe7 0x23 0x40 0x0c 0x3a 0xe8 + +# CHECK: wfkedbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xe8 + +# CHECK: wfkedbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xe8 + +# CHECK: wfkedbs %f0, %f0, %v31 +0xe7 0x00 0xf0 0x1c 0x32 0xe8 + +# CHECK: wfkedbs %f0, %v31, %f0 +0xe7 0x0f 0x00 0x1c 0x34 0xe8 + +# CHECK: wfkedbs %v31, %f0, %f0 +0xe7 0xf0 0x00 0x1c 0x38 0xe8 + +# CHECK: wfkedbs %v18, %f3, %v20 +0xe7 0x23 0x40 0x1c 0x3a 0xe8 + +# CHECK: wfkhdb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xeb + +# CHECK: wfkhdb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xeb + +# CHECK: wfkhdb %f0, %f0, %v31 +0xe7 0x00 0xf0 0x0c 0x32 0xeb + +# CHECK: wfkhdb %f0, %v31, %f0 +0xe7 0x0f 0x00 0x0c 0x34 0xeb + +# CHECK: wfkhdb %v31, %f0, %f0 +0xe7 0xf0 0x00 0x0c 0x38 0xeb + +# CHECK: wfkhdb %v18, %f3, %v20 +0xe7 0x23 0x40 0x0c 0x3a 0xeb + +# CHECK: wfkhdbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xeb + +# CHECK: wfkhdbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xeb + +# CHECK: wfkhdbs %f0, %f0, %v31 +0xe7 0x00 0xf0 0x1c 0x32 0xeb + +# CHECK: wfkhdbs %f0, %v31, %f0 +0xe7 0x0f 0x00 0x1c 0x34 0xeb + +# CHECK: wfkhdbs %v31, %f0, %f0 +0xe7 0xf0 0x00 0x1c 0x38 0xeb + +# CHECK: wfkhdbs %v18, %f3, %v20 +0xe7 0x23 0x40 0x1c 0x3a 0xeb + +# CHECK: wfkhedb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xea + +# CHECK: wfkhedb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xea + +# CHECK: wfkhedb %f0, %f0, %v31 +0xe7 0x00 0xf0 0x0c 0x32 0xea + +# CHECK: wfkhedb %f0, %v31, %f0 +0xe7 0x0f 0x00 0x0c 0x34 0xea + +# CHECK: wfkhedb %v31, %f0, %f0 +0xe7 0xf0 0x00 0x0c 0x38 0xea + +# CHECK: wfkhedb %v18, %f3, %v20 +0xe7 0x23 0x40 0x0c 0x3a 0xea + +# CHECK: wfkhedbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xea + +# CHECK: wfkhedbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xea + +# CHECK: wfkhedbs %f0, %f0, %v31 +0xe7 0x00 0xf0 0x1c 0x32 0xea + +# CHECK: wfkhedbs %f0, %v31, %f0 +0xe7 0x0f 0x00 0x1c 0x34 0xea + +# CHECK: wfkhedbs %v31, %f0, %f0 +0xe7 0xf0 0x00 0x1c 0x38 0xea + +# CHECK: wfkhedbs %v18, %f3, %v20 +0xe7 0x23 0x40 0x1c 0x3a 0xea + +# CHECK: wfmaxdb %f0, %f0, %f0, 0 +0xe7 0x00 0x00 0x08 0x30 0xef + +# CHECK: wfmaxdb %f0, %f0, %f0, 0 +0xe7 0x00 0x00 0x08 0x30 0xef + +# CHECK: wfmaxdb %f0, %f0, %f0, 4 +0xe7 0x00 0x00 0x48 0x30 0xef + +# CHECK: wfmaxdb %f0, %f0, %v31, 0 +0xe7 0x00 0xf0 0x08 0x32 0xef + +# CHECK: wfmaxdb %f0, %v31, %f0, 0 +0xe7 0x0f 0x00 0x08 0x34 0xef + +# CHECK: wfmaxdb %v31, %f0, %f0, 0 +0xe7 0xf0 0x00 0x08 0x38 0xef + +# CHECK: wfmaxdb %v18, %f3, %v20, 11 +0xe7 0x23 0x40 0xb8 0x3a 0xef + +# CHECK: wfmindb %f0, %f0, %f0, 0 +0xe7 0x00 0x00 0x08 0x30 0xee + +# CHECK: wfmindb %f0, %f0, %f0, 0 +0xe7 0x00 0x00 0x08 0x30 0xee + +# CHECK: wfmindb %f0, %f0, %f0, 4 +0xe7 0x00 0x00 0x48 0x30 0xee + +# CHECK: wfmindb %f0, %f0, %v31, 0 +0xe7 0x00 0xf0 0x08 0x32 0xee + +# CHECK: wfmindb %f0, %v31, %f0, 0 +0xe7 0x0f 0x00 0x08 0x34 0xee + +# CHECK: wfmindb %v31, %f0, %f0, 0 +0xe7 0xf0 0x00 0x08 0x38 0xee + +# CHECK: wfmindb %v18, %f3, %v20, 11 +0xe7 0x23 0x40 0xb8 0x3a 0xee + +# CHECK: wfnmadb %f0, %f0, %f0, %f0 +0xe7 0x00 0x03 0x08 0x00 0x9f + +# CHECK: wfnmadb %f0, %f0, %f0, %f0 +0xe7 0x00 0x03 0x08 0x00 0x9f + +# CHECK: wfnmadb %f0, %f0, %f0, %v31 +0xe7 0x00 0x03 0x08 0xf1 0x9f + +# CHECK: wfnmadb %f0, %f0, %v31, %f0 +0xe7 0x00 0xf3 0x08 0x02 0x9f + +# CHECK: wfnmadb %f0, %v31, %f0, %f0 +0xe7 0x0f 0x03 0x08 0x04 0x9f + +# CHECK: wfnmadb %v31, %f0, %f0, %f0 +0xe7 0xf0 0x03 0x08 0x08 0x9f + +# CHECK: wfnmadb %f13, %v17, %v21, %v25 +0xe7 0xd1 0x53 0x08 0x97 0x9f + +# CHECK: wfnmsdb %f0, %f0, %f0, %f0 +0xe7 0x00 0x03 0x08 0x00 0x9e + +# CHECK: wfnmsdb %f0, %f0, %f0, %f0 +0xe7 0x00 0x03 0x08 0x00 0x9e + +# CHECK: wfnmsdb %f0, %f0, %f0, %v31 +0xe7 0x00 0x03 0x08 0xf1 0x9e + +# CHECK: wfnmsdb %f0, %f0, %v31, %f0 +0xe7 0x00 0xf3 0x08 0x02 0x9e + +# CHECK: wfnmsdb %f0, %v31, %f0, %f0 +0xe7 0x0f 0x03 0x08 0x04 0x9e + +# CHECK: wfnmsdb %v31, %f0, %f0, %f0 +0xe7 0xf0 0x03 0x08 0x08 0x9e + +# CHECK: wfnmsdb %f13, %v17, %v21, %v25 +0xe7 0xd1 0x53 0x08 0x97 0x9e + diff --git a/llvm/test/MC/SystemZ/insn-bad-z13.s b/llvm/test/MC/SystemZ/insn-bad-z13.s index e9fac44aa88..7bf5b5303dd 100644 --- a/llvm/test/MC/SystemZ/insn-bad-z13.s +++ b/llvm/test/MC/SystemZ/insn-bad-z13.s @@ -4,6 +4,19 @@ # RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=arch11 < %s 2> %t # RUN: FileCheck < %t %s +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: agh %r0, 0 + + agh %r0, 0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: bi 0 +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: bic 0, 0 + + bi 0 + bic 0, 0 + #CHECK: error: invalid operand #CHECK: cdpt %f0, 0(1), -1 #CHECK: error: invalid operand @@ -150,6 +163,16 @@ cxpt %f0, 0(-), 0 cxpt %f15, 0(1), 0 +#CHECK: error: instruction requires: insert-reference-bits-multiple +#CHECK: irbm %r0, %r0 + + irbm %r0, %r0 + +#CHECK: error: instruction requires: message-security-assist-extension8 +#CHECK: kma %r2, %r4, %r6 + + kma %r2, %r4, %r6 + #CHECK: error: invalid operand #CHECK: lcbb %r0, 0, -1 #CHECK: error: invalid operand @@ -167,6 +190,21 @@ lcbb %r0, 4096, 0 lcbb %r0, 0(%v1,%r2), 0 +#CHECK: error: instruction requires: guarded-storage +#CHECK: lgg %r0, 0 + + lgg %r0, 0 + +#CHECK: error: instruction requires: guarded-storage +#CHECK: lgsc %r0, 0 + + lgsc %r0, 0 + +#CHECK: error: instruction requires: guarded-storage +#CHECK: llgfsg %r0, 0 + + llgfsg %r0, 0 + #CHECK: error: invalid operand #CHECK: llzrgf %r0, -524289 #CHECK: error: invalid operand @@ -249,6 +287,41 @@ lzrg %r0, -524289 lzrg %r0, 524288 +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: mg %r0, 0 + + mg %r0, 0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: mgh %r0, 0 + + mgh %r0, 0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: mgrk %r0, %r0, %r0 + + mgrk %r0, %r0, %r0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: msc %r0, 0 + + msc %r0, 0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: msgc %r0, 0 + + msgc %r0, 0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: msrkc %r0, %r0, %r0 + + msrkc %r0, %r0, %r0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: msgrkc %r0, %r0, %r0 + + msgrkc %r0, %r0, %r0 + #CHECK: error: invalid register pair #CHECK: ppno %r1, %r2 #CHECK: error: invalid register pair @@ -257,6 +330,21 @@ ppno %r1, %r2 ppno %r2, %r1 +#CHECK: error: instruction requires: message-security-assist-extension7 +#CHECK: prno %r2, %r4 + + prno %r2, %r4 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: sgh %r0, 0 + + sgh %r0, 0 + +#CHECK: error: instruction requires: guarded-storage +#CHECK: stgsc %r0, 0 + + stgsc %r0, 0 + #CHECK: error: invalid operand #CHECK: stocfh %r0, 0, -1 #CHECK: error: invalid operand @@ -274,6 +362,16 @@ stocfh %r0, 524288, 1 stocfh %r0, 0(%r1,%r2), 1 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vap %v0, %v0, %v0, 0, 0 + + vap %v0, %v0, %v0, 0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vbperm %v0, %v0, %v0 + + vbperm %v0, %v0, %v0 + #CHECK: error: invalid operand #CHECK: vcdg %v0, %v0, 0, 0, -1 #CHECK: error: invalid operand @@ -410,6 +508,35 @@ vclgdb %v0, %v0, -1, 0 vclgdb %v0, %v0, 16, 0 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vcp %v0, %v0, 0 + + vcp %v0, %v0, 0 + +#CHECK: vcvb %r0, %v0, 0 + + vcvb %r0, %v0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vcvbg %r0, %v0, 0 + + vcvbg %r0, %v0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vcvd %v0, %r0, 0, 0 + + vcvd %v0, %r0, 0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vcvdg %v0, %r0, 0, 0 + + vcvdg %v0, %r0, 0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vdp %v0, %v0, %v0, 0, 0 + + vdp %v0, %v0, %v0, 0, 0 + #CHECK: error: invalid operand #CHECK: verim %v0, %v0, %v0, 0, -1 #CHECK: error: invalid operand @@ -1130,6 +1257,62 @@ vfidb %v0, %v0, -1, 0 vfidb %v0, %v0, 16, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkedb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkedbs %v0, %v0, %v0 + + vfkedb %v0, %v0, %v0 + vfkedbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkhdb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkhdbs %v0, %v0, %v0 + + vfkhdb %v0, %v0, %v0 + vfkhdbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkhedb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkhedbs %v0, %v0, %v0 + + vfkhedb %v0, %v0, %v0 + vfkhedbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfmax %v0, %v0, %v0, 0, 0, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfmaxdb %v0, %v0, %v0, 0 + + vfmax %v0, %v0, %v0, 0, 0, 0 + vfmaxdb %v0, %v0, %v0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfmin %v0, %v0, %v0, 0, 0, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfmindb %v0, %v0, %v0, 0 + + vfmin %v0, %v0, %v0, 0, 0, 0 + vfmindb %v0, %v0, %v0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfnma %v0, %v0, %v0, %v0, 0, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfnmadb %v0, %v0, %v0, %v0 + + vfnma %v0, %v0, %v0, %v0, 0, 0 + vfnmadb %v0, %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfnms %v0, %v0, %v0, %v0, 0, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfnmsdb %v0, %v0, %v0, %v0 + + vfnms %v0, %v0, %v0, %v0, 0, 0 + vfnmsdb %v0, %v0, %v0, %v0 + #CHECK: error: invalid operand #CHECK: vftci %v0, %v0, 0, 0, -1 #CHECK: error: invalid operand @@ -1615,6 +1798,11 @@ vlgvh %r0, %v0, 4096 vlgvh %r0, %v0, 0(%r0) +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vlip %v0, 0, 0 + + vlip %v0, 0, 0 + #CHECK: error: invalid operand #CHECK: vll %v0, %r0, -1 #CHECK: error: invalid operand @@ -1687,6 +1875,11 @@ vllezh %v0, 4096 vllezh %v0, 0(%v1,%r2) +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vllezlf %v0, 0 + + vllezlf %v0, 0 + #CHECK: error: invalid operand #CHECK: vlm %v0, %v0, -1 #CHECK: error: invalid operand @@ -1756,6 +1949,16 @@ vlreph %v0, 4096 vlreph %v0, 0(%v1,%r2) +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vlrl %v0, 0, 0 + + vlrl %v0, 0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vlrlr %v0, %r0, 0 + + vlrlr %v0, %r0, 0 + #CHECK: error: invalid operand #CHECK: vlvg %v0, %r0, 0, -1 #CHECK: error: invalid operand @@ -1817,6 +2020,39 @@ vlvgh %v0, %r0, 4096 vlvgh %v0, %r0, 0(%r0) +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vmp %v0, %v0, %v0, 0, 0 + + vmp %v0, %v0, %v0, 0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vmsl %v0, %v0, %v0, %v0, 0, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vmslg %v0, %v0, %v0, %v0, 0 + + vmsl %v0, %v0, %v0, %v0, 0, 0 + vmslg %v0, %v0, %v0, %v0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vmsp %v0, %v0, %v0, 0, 0 + + vmsp %v0, %v0, %v0, 0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vnn %v0, %v0, %v0 + + vnn %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vnx %v0, %v0, %v0 + + vnx %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: voc %v0, %v0, %v0 + + voc %v0, %v0, %v0 + #CHECK: error: invalid operand #CHECK: vpdi %v0, %v0, %v0, -1 #CHECK: error: invalid operand @@ -1825,6 +2061,30 @@ vpdi %v0, %v0, %v0, -1 vpdi %v0, %v0, %v0, 16 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vpkz %v0, 0, 0 + + vpkz %v0, 0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vpopctb %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vpopctf %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vpopctg %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vpopcth %v0, %v0 + + vpopctb %v0, %v0 + vpopctf %v0, %v0 + vpopctg %v0, %v0 + vpopcth %v0, %v0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vpsop %v0, %v0, 0, 0, 0 + + vpsop %v0, %v0, 0, 0, 0 + #CHECK: error: invalid operand #CHECK: vrep %v0, %v0, 0, -1 #CHECK: error: invalid operand @@ -1917,6 +2177,11 @@ vrepih %v0, -32769 vrepih %v0, 32768 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vrp %v0, %v0, %v0, 0, 0 + + vrp %v0, %v0, %v0, 0, 0 + #CHECK: error: vector index required #CHECK: vscef %v0, 0(%r1), 0 #CHECK: error: vector index required @@ -1957,6 +2222,11 @@ vsceg %v0, -1(%v0,%r1), 0 vsceg %v0, 4096(%v0,%r1), 0 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vsdp %v0, %v0, %v0, 0, 0 + + vsdp %v0, %v0, %v0, 0, 0 + #CHECK: error: invalid operand #CHECK: vsldb %v0, %v0, %v0, -1 #CHECK: error: invalid operand @@ -1965,6 +2235,16 @@ vsldb %v0, %v0, %v0, -1 vsldb %v0, %v0, %v0, 256 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vsp %v0, %v0, %v0, 0, 0 + + vsp %v0, %v0, %v0, 0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vsrp %v0, %v0, 0, 0, 0 + + vsrp %v0, %v0, 0, 0, 0 + #CHECK: error: invalid operand #CHECK: vst %v0, -1 #CHECK: error: invalid operand @@ -2251,6 +2531,26 @@ vstrczhs %v0, %v0, %v0 vstrczhs %v0, %v0, %v0, %v0, 0, 0 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vstrl %v0, 0, 0 + + vstrl %v0, 0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vstrlr %v0, %r0, 0 + + vstrlr %v0, %r0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vtp %v0 + + vtp %v0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vupkz %v0, 0, 0 + + vupkz %v0, 0, 0 + #CHECK: error: invalid operand #CHECK: wcdgb %v0, %v0, 0, -1 #CHECK: error: invalid operand @@ -2321,6 +2621,50 @@ wfidb %v0, %v0, -1, 0 wfidb %v0, %v0, 16, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkedb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkedbs %v0, %v0, %v0 + + wfkedb %v0, %v0, %v0 + wfkedbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkhdb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkhdbs %v0, %v0, %v0 + + wfkhdb %v0, %v0, %v0 + wfkhdbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkhedb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkhedbs %v0, %v0, %v0 + + wfkhedb %v0, %v0, %v0 + wfkhedbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfmaxdb %v0, %v0, %v0, 0 + + wfmaxdb %v0, %v0, %v0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfmindb %v0, %v0, %v0, 0 + + wfmindb %v0, %v0, %v0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfnmadb %v0, %v0, %v0, %v0 + + wfnmadb %v0, %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfnmsdb %v0, %v0, %v0, %v0 + + wfnmsdb %v0, %v0, %v0, %v0 + #CHECK: error: invalid operand #CHECK: wftcidb %v0, %v0, -1 #CHECK: error: invalid operand diff --git a/llvm/test/MC/SystemZ/insn-bad-z14.s b/llvm/test/MC/SystemZ/insn-bad-z14.s new file mode 100644 index 00000000000..4e0a250810a --- /dev/null +++ b/llvm/test/MC/SystemZ/insn-bad-z14.s @@ -0,0 +1,562 @@ +# For z14 only. +# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z14 < %s 2> %t +# RUN: FileCheck < %t %s +# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=arch12 < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: bi -524289 +#CHECK: error: invalid operand +#CHECK: bi 524288 + + bi -524289 + bi 524288 + +#CHECK: error: invalid operand +#CHECK: bic -1, 0(%r1) +#CHECK: error: invalid operand +#CHECK: bic 16, 0(%r1) +#CHECK: error: invalid operand +#CHECK: bic 0, -524289 +#CHECK: error: invalid operand +#CHECK: bic 0, 524288 + + bic -1, 0(%r1) + bic 16, 0(%r1) + bic 0, -524289 + bic 0, 524288 + +#CHECK: error: invalid operand +#CHECK: agh %r0, -524289 +#CHECK: error: invalid operand +#CHECK: agh %r0, 524288 + + agh %r0, -524289 + agh %r0, 524288 + +#CHECK: error: invalid register pair +#CHECK: kma %r1, %r2, %r4 +#CHECK: error: invalid register pair +#CHECK: kma %r2, %r1, %r4 +#CHECK: error: invalid register pair +#CHECK: kma %r2, %r4, %r1 + + kma %r1, %r2, %r4 + kma %r2, %r1, %r4 + kma %r2, %r4, %r1 + +#CHECK: error: invalid operand +#CHECK: lgg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lgg %r0, 524288 + + lgg %r0, -524289 + lgg %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: lgsc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lgsc %r0, 524288 + + lgsc %r0, -524289 + lgsc %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: llgfsg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: llgfsg %r0, 524288 + + llgfsg %r0, -524289 + llgfsg %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: mg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: mg %r0, 524288 +#CHECK: error: invalid register pair +#CHECK: mg %r1, 0 + + mg %r0, -524289 + mg %r0, 524288 + mg %r1, 0 + +#CHECK: error: invalid operand +#CHECK: mgh %r0, -524289 +#CHECK: error: invalid operand +#CHECK: mgh %r0, 524288 + + mgh %r0, -524289 + mgh %r0, 524288 + +#CHECK: error: invalid register pair +#CHECK: mgrk %r1, %r0, %r0 + + mgrk %r1, %r0, %r0 + +#CHECK: error: invalid operand +#CHECK: msc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: msc %r0, 524288 + + msc %r0, -524289 + msc %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: msgc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: msgc %r0, 524288 + + msgc %r0, -524289 + msgc %r0, 524288 + +#CHECK: error: invalid register pair +#CHECK: prno %r1, %r2 +#CHECK: error: invalid register pair +#CHECK: prno %r2, %r1 + + prno %r1, %r2 + prno %r2, %r1 + +#CHECK: error: invalid operand +#CHECK: sgh %r0, -524289 +#CHECK: error: invalid operand +#CHECK: sgh %r0, 524288 + + sgh %r0, -524289 + sgh %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: stgsc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: stgsc %r0, 524288 + + stgsc %r0, -524289 + stgsc %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: vap %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vap %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vap %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vap %v0, %v0, %v0, 256, 0 + + vap %v0, %v0, %v0, 0, -1 + vap %v0, %v0, %v0, 0, 16 + vap %v0, %v0, %v0, -1, 0 + vap %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vcp %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vcp %v0, %v0, 16 + + vcp %v0, %v0, -1 + vcp %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vcvb %r0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vcvb %r0, %v0, 16 + + vcvb %r0, %v0, -1 + vcvb %r0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vcvbg %r0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vcvbg %r0, %v0, 16 + + vcvbg %r0, %v0, -1 + vcvbg %r0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vcvd %r0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vcvd %r0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vcvd %r0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vcvd %r0, %v0, 256, 0 + + vcvd %r0, %v0, 0, -1 + vcvd %r0, %v0, 0, 16 + vcvd %r0, %v0, -1, 0 + vcvd %r0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vcvdg %r0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vcvdg %r0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vcvdg %r0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vcvdg %r0, %v0, 256, 0 + + vcvdg %r0, %v0, 0, -1 + vcvdg %r0, %v0, 0, 16 + vcvdg %r0, %v0, -1, 0 + vcvdg %r0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vdp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vdp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vdp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vdp %v0, %v0, %v0, 256, 0 + + vdp %v0, %v0, %v0, 0, -1 + vdp %v0, %v0, %v0, 0, 16 + vdp %v0, %v0, %v0, -1, 0 + vdp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, 0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, 0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, 0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, 0, 16, 0 +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, -1, 0, 0 +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, 16, 0, 0 + + vfmax %v0, %v0, %v0, 0, 0, -1 + vfmax %v0, %v0, %v0, 0, 0, 16 + vfmax %v0, %v0, %v0, 0, -1, 0 + vfmax %v0, %v0, %v0, 0, 16, 0 + vfmax %v0, %v0, %v0, -1, 0, 0 + vfmax %v0, %v0, %v0, 16, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vfmaxdb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vfmaxdb %v0, %v0, %v0, 16 + + vfmaxdb %v0, %v0, %v0, -1 + vfmaxdb %v0, %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, 0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, 0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, 0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, 0, 16, 0 +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, -1, 0, 0 +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, 16, 0, 0 + + vfmin %v0, %v0, %v0, 0, 0, -1 + vfmin %v0, %v0, %v0, 0, 0, 16 + vfmin %v0, %v0, %v0, 0, -1, 0 + vfmin %v0, %v0, %v0, 0, 16, 0 + vfmin %v0, %v0, %v0, -1, 0, 0 + vfmin %v0, %v0, %v0, 16, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vfmindb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vfmindb %v0, %v0, %v0, 16 + + vfmindb %v0, %v0, %v0, -1 + vfmindb %v0, %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vfnma %v0, %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vfnma %v0, %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vfnma %v0, %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vfnma %v0, %v0, %v0, %v0, 16, 0 + + vfnma %v0, %v0, %v0, %v0, 0, -1 + vfnma %v0, %v0, %v0, %v0, 0, 16 + vfnma %v0, %v0, %v0, %v0, -1, 0 + vfnma %v0, %v0, %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vfnms %v0, %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vfnms %v0, %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vfnms %v0, %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vfnms %v0, %v0, %v0, %v0, 16, 0 + + vfnms %v0, %v0, %v0, %v0, 0, -1 + vfnms %v0, %v0, %v0, %v0, 0, 16 + vfnms %v0, %v0, %v0, %v0, -1, 0 + vfnms %v0, %v0, %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vlip %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vlip %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vlip %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vlip %v0, 65536, 0 + + vlip %v0, 0, -1 + vlip %v0, 0, 16 + vlip %v0, -1, 0 + vlip %v0, 65536, 0 + +#CHECK: error: invalid operand +#CHECK: vllezlf %v0, -1 +#CHECK: error: invalid operand +#CHECK: vllezlf %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vllezlf %v0, 0(%v1,%r2) + + vllezlf %v0, -1 + vllezlf %v0, 4096 + vllezlf %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vlrl %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vlrl %v0, 0, 256 +#CHECK: error: invalid operand +#CHECK: vlrl %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vlrl %v0, 4096, 0 +#CHECK: error: %r0 used in an address +#CHECK: vlrl %v0, 0(%r0), 0 + + vlrl %v0, 0, -1 + vlrl %v0, 0, 256 + vlrl %v0, -1, 0 + vlrl %v0, 4096, 0 + vlrl %v0, 0(%r0), 0 + +#CHECK: error: invalid operand +#CHECK: vlrlr %v0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: vlrlr %v0, %r0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vlrlr %v0, %r0, 0(%r0) + + vlrlr %v0, %r0, -1 + vlrlr %v0, %r0, 4096 + vlrlr %v0, %r0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vmp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vmp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vmp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vmp %v0, %v0, %v0, 256, 0 + + vmp %v0, %v0, %v0, 0, -1 + vmp %v0, %v0, %v0, 0, 16 + vmp %v0, %v0, %v0, -1, 0 + vmp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vmsp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vmsp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vmsp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vmsp %v0, %v0, %v0, 256, 0 + + vmsp %v0, %v0, %v0, 0, -1 + vmsp %v0, %v0, %v0, 0, 16 + vmsp %v0, %v0, %v0, -1, 0 + vmsp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vmsl %v0, %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vmsl %v0, %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vmsl %v0, %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vmsl %v0, %v0, %v0, %v0, 16, 0 + + vmsl %v0, %v0, %v0, %v0, 0, -1 + vmsl %v0, %v0, %v0, %v0, 0, 16 + vmsl %v0, %v0, %v0, %v0, -1, 0 + vmsl %v0, %v0, %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vmslg %v0, %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vmslg %v0, %v0, %v0, %v0, 16 + + vmslg %v0, %v0, %v0, %v0, -1 + vmslg %v0, %v0, %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vpkz %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vpkz %v0, 0, 256 +#CHECK: error: invalid operand +#CHECK: vpkz %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vpkz %v0, 4096, 0 +#CHECK: error: %r0 used in an address +#CHECK: vpkz %v0, 0(%r0), 0 + + vpkz %v0, 0, -1 + vpkz %v0, 0, 256 + vpkz %v0, -1, 0 + vpkz %v0, 4096, 0 + vpkz %v0, 0(%r0), 0 + +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, 0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, 0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, 0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, 0, 256, 0 +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, -1, 0, 0 +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, 256, 0, 0 + + vpsop %v0, %v0, 0, 0, -1 + vpsop %v0, %v0, 0, 0, 16 + vpsop %v0, %v0, 0, -1, 0 + vpsop %v0, %v0, 0, 256, 0 + vpsop %v0, %v0, -1, 0, 0 + vpsop %v0, %v0, 256, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vrp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vrp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vrp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vrp %v0, %v0, %v0, 256, 0 + + vrp %v0, %v0, %v0, 0, -1 + vrp %v0, %v0, %v0, 0, 16 + vrp %v0, %v0, %v0, -1, 0 + vrp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vsdp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vsdp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vsdp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vsdp %v0, %v0, %v0, 256, 0 + + vsdp %v0, %v0, %v0, 0, -1 + vsdp %v0, %v0, %v0, 0, 16 + vsdp %v0, %v0, %v0, -1, 0 + vsdp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vsp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vsp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vsp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vsp %v0, %v0, %v0, 256, 0 + + vsp %v0, %v0, %v0, 0, -1 + vsp %v0, %v0, %v0, 0, 16 + vsp %v0, %v0, %v0, -1, 0 + vsp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, 0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, 0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, 0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, 0, 256, 0 +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, -1, 0, 0 +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, 256, 0, 0 + + vsrp %v0, %v0, 0, 0, -1 + vsrp %v0, %v0, 0, 0, 16 + vsrp %v0, %v0, 0, -1, 0 + vsrp %v0, %v0, 0, 256, 0 + vsrp %v0, %v0, -1, 0, 0 + vsrp %v0, %v0, 256, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vstrl %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vstrl %v0, 0, 256 +#CHECK: error: invalid operand +#CHECK: vstrl %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vstrl %v0, 4096, 0 +#CHECK: error: %r0 used in an address +#CHECK: vstrl %v0, 0(%r0), 0 + + vstrl %v0, 0, -1 + vstrl %v0, 0, 256 + vstrl %v0, -1, 0 + vstrl %v0, 4096, 0 + vstrl %v0, 0(%r0), 0 + +#CHECK: error: invalid operand +#CHECK: vstrlr %v0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: vstrlr %v0, %r0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vstrlr %v0, %r0, 0(%r0) + + vstrlr %v0, %r0, -1 + vstrlr %v0, %r0, 4096 + vstrlr %v0, %r0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vupkz %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vupkz %v0, 0, 256 +#CHECK: error: invalid operand +#CHECK: vupkz %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vupkz %v0, 4096, 0 +#CHECK: error: %r0 used in an address +#CHECK: vupkz %v0, 0(%r0), 0 + + vupkz %v0, 0, -1 + vupkz %v0, 0, 256 + vupkz %v0, -1, 0 + vupkz %v0, 4096, 0 + vupkz %v0, 0(%r0), 0 + +#CHECK: error: invalid operand +#CHECK: wfmaxdb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: wfmaxdb %v0, %v0, %v0, 16 + + wfmaxdb %v0, %v0, %v0, -1 + wfmaxdb %v0, %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: wfmindb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: wfmindb %v0, %v0, %v0, 16 + + wfmindb %v0, %v0, %v0, -1 + wfmindb %v0, %v0, %v0, 16 + diff --git a/llvm/test/MC/SystemZ/insn-good-z14.s b/llvm/test/MC/SystemZ/insn-good-z14.s new file mode 100644 index 00000000000..c247f252659 --- /dev/null +++ b/llvm/test/MC/SystemZ/insn-good-z14.s @@ -0,0 +1,1282 @@ +# For z14 and above. +# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z14 -show-encoding %s \ +# RUN: | FileCheck %s +# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch12 -show-encoding %s \ +# RUN: | FileCheck %s + +#CHECK: agh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x38] +#CHECK: agh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x38] +#CHECK: agh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x38] +#CHECK: agh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x38] +#CHECK: agh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x38] +#CHECK: agh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x38] +#CHECK: agh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x38] +#CHECK: agh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x38] +#CHECK: agh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x38] +#CHECK: agh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x38] + + agh %r0, -524288 + agh %r0, -1 + agh %r0, 0 + agh %r0, 1 + agh %r0, 524287 + agh %r0, 0(%r1) + agh %r0, 0(%r15) + agh %r0, 524287(%r1,%r15) + agh %r0, 524287(%r15,%r1) + agh %r15, 0 + +#CHECK: bi -524288 # encoding: [0xe3,0xf0,0x00,0x00,0x80,0x47] +#CHECK: bi -1 # encoding: [0xe3,0xf0,0x0f,0xff,0xff,0x47] +#CHECK: bi 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x47] +#CHECK: bi 1 # encoding: [0xe3,0xf0,0x00,0x01,0x00,0x47] +#CHECK: bi 524287 # encoding: [0xe3,0xf0,0x0f,0xff,0x7f,0x47] +#CHECK: bi 0(%r1) # encoding: [0xe3,0xf0,0x10,0x00,0x00,0x47] +#CHECK: bi 0(%r15) # encoding: [0xe3,0xf0,0xf0,0x00,0x00,0x47] +#CHECK: bi 524287(%r1,%r15) # encoding: [0xe3,0xf1,0xff,0xff,0x7f,0x47] +#CHECK: bi 524287(%r15,%r1) # encoding: [0xe3,0xff,0x1f,0xff,0x7f,0x47] + + bi -524288 + bi -1 + bi 0 + bi 1 + bi 524287 + bi 0(%r1) + bi 0(%r15) + bi 524287(%r1,%r15) + bi 524287(%r15,%r1) + +#CHECK: bic 0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x47] +#CHECK: bic 0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x47] +#CHECK: bic 0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x47] +#CHECK: bic 0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x47] +#CHECK: bic 0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x47] +#CHECK: bic 0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x47] +#CHECK: bic 0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x47] +#CHECK: bic 0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x47] +#CHECK: bic 0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x47] +#CHECK: bic 15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x47] + + bic 0, -524288 + bic 0, -1 + bic 0, 0 + bic 0, 1 + bic 0, 524287 + bic 0, 0(%r1) + bic 0, 0(%r15) + bic 0, 524287(%r1,%r15) + bic 0, 524287(%r15,%r1) + bic 15, 0 + +#CHECK: bic 1, 0(%r7) # encoding: [0xe3,0x10,0x70,0x00,0x00,0x47] +#CHECK: bio 0(%r15) # encoding: [0xe3,0x10,0xf0,0x00,0x00,0x47] + + bic 1, 0(%r7) + bio 0(%r15) + +#CHECK: bic 2, 0(%r7) # encoding: [0xe3,0x20,0x70,0x00,0x00,0x47] +#CHECK: bih 0(%r15) # encoding: [0xe3,0x20,0xf0,0x00,0x00,0x47] + + bic 2, 0(%r7) + bih 0(%r15) + +#CHECK: bic 3, 0(%r7) # encoding: [0xe3,0x30,0x70,0x00,0x00,0x47] +#CHECK: binle 0(%r15) # encoding: [0xe3,0x30,0xf0,0x00,0x00,0x47] + + bic 3, 0(%r7) + binle 0(%r15) + +#CHECK: bic 4, 0(%r7) # encoding: [0xe3,0x40,0x70,0x00,0x00,0x47] +#CHECK: bil 0(%r15) # encoding: [0xe3,0x40,0xf0,0x00,0x00,0x47] + + bic 4, 0(%r7) + bil 0(%r15) + +#CHECK: bic 5, 0(%r7) # encoding: [0xe3,0x50,0x70,0x00,0x00,0x47] +#CHECK: binhe 0(%r15) # encoding: [0xe3,0x50,0xf0,0x00,0x00,0x47] + + bic 5, 0(%r7) + binhe 0(%r15) + +#CHECK: bic 6, 0(%r7) # encoding: [0xe3,0x60,0x70,0x00,0x00,0x47] +#CHECK: bilh 0(%r15) # encoding: [0xe3,0x60,0xf0,0x00,0x00,0x47] + + bic 6, 0(%r7) + bilh 0(%r15) + +#CHECK: bic 7, 0(%r7) # encoding: [0xe3,0x70,0x70,0x00,0x00,0x47] +#CHECK: bine 0(%r15) # encoding: [0xe3,0x70,0xf0,0x00,0x00,0x47] + + bic 7, 0(%r7) + bine 0(%r15) + +#CHECK: bic 8, 0(%r7) # encoding: [0xe3,0x80,0x70,0x00,0x00,0x47] +#CHECK: bie 0(%r15) # encoding: [0xe3,0x80,0xf0,0x00,0x00,0x47] + + bic 8, 0(%r7) + bie 0(%r15) + +#CHECK: bic 9, 0(%r7) # encoding: [0xe3,0x90,0x70,0x00,0x00,0x47] +#CHECK: binlh 0(%r15) # encoding: [0xe3,0x90,0xf0,0x00,0x00,0x47] + + bic 9, 0(%r7) + binlh 0(%r15) + +#CHECK: bic 10, 0(%r7) # encoding: [0xe3,0xa0,0x70,0x00,0x00,0x47] +#CHECK: bihe 0(%r15) # encoding: [0xe3,0xa0,0xf0,0x00,0x00,0x47] + + bic 10, 0(%r7) + bihe 0(%r15) + +#CHECK: bic 11, 0(%r7) # encoding: [0xe3,0xb0,0x70,0x00,0x00,0x47] +#CHECK: binl 0(%r15) # encoding: [0xe3,0xb0,0xf0,0x00,0x00,0x47] + + bic 11, 0(%r7) + binl 0(%r15) + +#CHECK: bic 12, 0(%r7) # encoding: [0xe3,0xc0,0x70,0x00,0x00,0x47] +#CHECK: bile 0(%r15) # encoding: [0xe3,0xc0,0xf0,0x00,0x00,0x47] + + bic 12, 0(%r7) + bile 0(%r15) + +#CHECK: bic 13, 0(%r7) # encoding: [0xe3,0xd0,0x70,0x00,0x00,0x47] +#CHECK: binh 0(%r15) # encoding: [0xe3,0xd0,0xf0,0x00,0x00,0x47] + + bic 13, 0(%r7) + binh 0(%r15) + +#CHECK: bic 14, 0(%r7) # encoding: [0xe3,0xe0,0x70,0x00,0x00,0x47] +#CHECK: bino 0(%r15) # encoding: [0xe3,0xe0,0xf0,0x00,0x00,0x47] + + bic 14, 0(%r7) + bino 0(%r15) + +#CHECK: irbm %r0, %r0 # encoding: [0xb9,0xac,0x00,0x00] +#CHECK: irbm %r0, %r15 # encoding: [0xb9,0xac,0x00,0x0f] +#CHECK: irbm %r15, %r0 # encoding: [0xb9,0xac,0x00,0xf0] +#CHECK: irbm %r7, %r8 # encoding: [0xb9,0xac,0x00,0x78] +#CHECK: irbm %r15, %r15 # encoding: [0xb9,0xac,0x00,0xff] + + irbm %r0,%r0 + irbm %r0,%r15 + irbm %r15,%r0 + irbm %r7,%r8 + irbm %r15,%r15 + +#CHECK: kma %r2, %r2, %r2 # encoding: [0xb9,0x29,0x20,0x22] +#CHECK: kma %r2, %r8, %r14 # encoding: [0xb9,0x29,0x80,0x2e] +#CHECK: kma %r14, %r8, %r2 # encoding: [0xb9,0x29,0x80,0xe2] +#CHECK: kma %r6, %r8, %r10 # encoding: [0xb9,0x29,0x80,0x6a] + + kma %r2, %r2, %r2 + kma %r2, %r8, %r14 + kma %r14, %r8, %r2 + kma %r6, %r8, %r10 + +#CHECK: lgg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x4c] +#CHECK: lgg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x4c] +#CHECK: lgg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x4c] +#CHECK: lgg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x4c] +#CHECK: lgg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x4c] +#CHECK: lgg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x4c] +#CHECK: lgg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x4c] +#CHECK: lgg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x4c] +#CHECK: lgg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x4c] +#CHECK: lgg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x4c] + + lgg %r0, -524288 + lgg %r0, -1 + lgg %r0, 0 + lgg %r0, 1 + lgg %r0, 524287 + lgg %r0, 0(%r1) + lgg %r0, 0(%r15) + lgg %r0, 524287(%r1,%r15) + lgg %r0, 524287(%r15,%r1) + lgg %r15, 0 + +#CHECK: lgsc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x4d] +#CHECK: lgsc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x4d] +#CHECK: lgsc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x4d] +#CHECK: lgsc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x4d] +#CHECK: lgsc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x4d] +#CHECK: lgsc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x4d] +#CHECK: lgsc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x4d] +#CHECK: lgsc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x4d] +#CHECK: lgsc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x4d] + + lgsc %r0, -524288 + lgsc %r0, -1 + lgsc %r0, 0 + lgsc %r0, 1 + lgsc %r0, 524287 + lgsc %r0, 0(%r1) + lgsc %r0, 0(%r15) + lgsc %r0, 524287(%r1,%r15) + lgsc %r0, 524287(%r15,%r1) + +#CHECK: llgfsg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x48] +#CHECK: llgfsg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x48] +#CHECK: llgfsg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x48] +#CHECK: llgfsg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x48] +#CHECK: llgfsg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x48] +#CHECK: llgfsg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x48] +#CHECK: llgfsg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x48] +#CHECK: llgfsg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x48] +#CHECK: llgfsg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x48] +#CHECK: llgfsg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x48] + + llgfsg %r0, -524288 + llgfsg %r0, -1 + llgfsg %r0, 0 + llgfsg %r0, 1 + llgfsg %r0, 524287 + llgfsg %r0, 0(%r1) + llgfsg %r0, 0(%r15) + llgfsg %r0, 524287(%r1,%r15) + llgfsg %r0, 524287(%r15,%r1) + llgfsg %r15, 0 + +#CHECK: mg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x84] +#CHECK: mg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x84] +#CHECK: mg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x84] +#CHECK: mg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x84] +#CHECK: mg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x84] +#CHECK: mg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x84] +#CHECK: mg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x84] +#CHECK: mg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x84] +#CHECK: mg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x84] +#CHECK: mg %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x84] + + mg %r0, -524288 + mg %r0, -1 + mg %r0, 0 + mg %r0, 1 + mg %r0, 524287 + mg %r0, 0(%r1) + mg %r0, 0(%r15) + mg %r0, 524287(%r1,%r15) + mg %r0, 524287(%r15,%r1) + mg %r14, 0 + +#CHECK: mgh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x3c] +#CHECK: mgh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x3c] +#CHECK: mgh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x3c] +#CHECK: mgh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x3c] +#CHECK: mgh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x3c] +#CHECK: mgh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x3c] +#CHECK: mgh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x3c] +#CHECK: mgh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x3c] +#CHECK: mgh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x3c] +#CHECK: mgh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x3c] + + mgh %r0, -524288 + mgh %r0, -1 + mgh %r0, 0 + mgh %r0, 1 + mgh %r0, 524287 + mgh %r0, 0(%r1) + mgh %r0, 0(%r15) + mgh %r0, 524287(%r1,%r15) + mgh %r0, 524287(%r15,%r1) + mgh %r15, 0 + +#CHECK: mgrk %r0, %r0, %r0 # encoding: [0xb9,0xec,0x00,0x00] +#CHECK: mgrk %r0, %r0, %r15 # encoding: [0xb9,0xec,0xf0,0x00] +#CHECK: mgrk %r0, %r15, %r0 # encoding: [0xb9,0xec,0x00,0x0f] +#CHECK: mgrk %r14, %r0, %r0 # encoding: [0xb9,0xec,0x00,0xe0] +#CHECK: mgrk %r6, %r8, %r9 # encoding: [0xb9,0xec,0x90,0x68] + + mgrk %r0,%r0,%r0 + mgrk %r0,%r0,%r15 + mgrk %r0,%r15,%r0 + mgrk %r14,%r0,%r0 + mgrk %r6,%r8,%r9 + +#CHECK: msc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x53] +#CHECK: msc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x53] +#CHECK: msc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x53] +#CHECK: msc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x53] +#CHECK: msc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x53] +#CHECK: msc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x53] +#CHECK: msc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x53] +#CHECK: msc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x53] +#CHECK: msc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x53] +#CHECK: msc %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x53] + + msc %r0, -524288 + msc %r0, -1 + msc %r0, 0 + msc %r0, 1 + msc %r0, 524287 + msc %r0, 0(%r1) + msc %r0, 0(%r15) + msc %r0, 524287(%r1,%r15) + msc %r0, 524287(%r15,%r1) + msc %r15, 0 + +#CHECK: msgc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x83] +#CHECK: msgc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x83] +#CHECK: msgc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x83] +#CHECK: msgc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x83] +#CHECK: msgc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x83] +#CHECK: msgc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x83] +#CHECK: msgc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x83] +#CHECK: msgc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x83] +#CHECK: msgc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x83] +#CHECK: msgc %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x83] + + msgc %r0, -524288 + msgc %r0, -1 + msgc %r0, 0 + msgc %r0, 1 + msgc %r0, 524287 + msgc %r0, 0(%r1) + msgc %r0, 0(%r15) + msgc %r0, 524287(%r1,%r15) + msgc %r0, 524287(%r15,%r1) + msgc %r15, 0 + +#CHECK: msrkc %r0, %r0, %r0 # encoding: [0xb9,0xfd,0x00,0x00] +#CHECK: msrkc %r0, %r0, %r15 # encoding: [0xb9,0xfd,0xf0,0x00] +#CHECK: msrkc %r0, %r15, %r0 # encoding: [0xb9,0xfd,0x00,0x0f] +#CHECK: msrkc %r15, %r0, %r0 # encoding: [0xb9,0xfd,0x00,0xf0] +#CHECK: msrkc %r7, %r8, %r9 # encoding: [0xb9,0xfd,0x90,0x78] + + msrkc %r0,%r0,%r0 + msrkc %r0,%r0,%r15 + msrkc %r0,%r15,%r0 + msrkc %r15,%r0,%r0 + msrkc %r7,%r8,%r9 + +#CHECK: msgrkc %r0, %r0, %r0 # encoding: [0xb9,0xed,0x00,0x00] +#CHECK: msgrkc %r0, %r0, %r15 # encoding: [0xb9,0xed,0xf0,0x00] +#CHECK: msgrkc %r0, %r15, %r0 # encoding: [0xb9,0xed,0x00,0x0f] +#CHECK: msgrkc %r15, %r0, %r0 # encoding: [0xb9,0xed,0x00,0xf0] +#CHECK: msgrkc %r7, %r8, %r9 # encoding: [0xb9,0xed,0x90,0x78] + + msgrkc %r0,%r0,%r0 + msgrkc %r0,%r0,%r15 + msgrkc %r0,%r15,%r0 + msgrkc %r15,%r0,%r0 + msgrkc %r7,%r8,%r9 + +#CHECK: prno %r2, %r2 # encoding: [0xb9,0x3c,0x00,0x22] +#CHECK: prno %r2, %r14 # encoding: [0xb9,0x3c,0x00,0x2e] +#CHECK: prno %r14, %r2 # encoding: [0xb9,0x3c,0x00,0xe2] +#CHECK: prno %r6, %r10 # encoding: [0xb9,0x3c,0x00,0x6a] + + prno %r2, %r2 + prno %r2, %r14 + prno %r14, %r2 + prno %r6, %r10 + +#CHECK: sgh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x39] +#CHECK: sgh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x39] +#CHECK: sgh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x39] +#CHECK: sgh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x39] +#CHECK: sgh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x39] +#CHECK: sgh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x39] +#CHECK: sgh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x39] +#CHECK: sgh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x39] +#CHECK: sgh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x39] +#CHECK: sgh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x39] + + sgh %r0, -524288 + sgh %r0, -1 + sgh %r0, 0 + sgh %r0, 1 + sgh %r0, 524287 + sgh %r0, 0(%r1) + sgh %r0, 0(%r15) + sgh %r0, 524287(%r1,%r15) + sgh %r0, 524287(%r15,%r1) + sgh %r15, 0 + +#CHECK: stgsc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x49] +#CHECK: stgsc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x49] +#CHECK: stgsc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x49] +#CHECK: stgsc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x49] +#CHECK: stgsc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x49] +#CHECK: stgsc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x49] +#CHECK: stgsc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x49] +#CHECK: stgsc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x49] +#CHECK: stgsc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x49] + + stgsc %r0, -524288 + stgsc %r0, -1 + stgsc %r0, 0 + stgsc %r0, 1 + stgsc %r0, 524287 + stgsc %r0, 0(%r1) + stgsc %r0, 0(%r15) + stgsc %r0, 524287(%r1,%r15) + stgsc %r0, 524287(%r15,%r1) + +#CHECK: vap %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x71] +#CHECK: vap %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x71] +#CHECK: vap %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x71] +#CHECK: vap %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x71] +#CHECK: vap %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x71] +#CHECK: vap %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x71] +#CHECK: vap %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x71] + + vap %v0, %v0, %v0, 0, 0 + vap %v0, %v0, %v0, 0, 15 + vap %v0, %v0, %v0, 255, 0 + vap %v0, %v0, %v31, 0, 0 + vap %v0, %v31, %v0, 0, 0 + vap %v31, %v0, %v0, 0, 0 + vap %v13, %v17, %v21, 0x79, 11 + +#CHECK: vbperm %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x85] +#CHECK: vbperm %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x85] +#CHECK: vbperm %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x85] +#CHECK: vbperm %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x85] +#CHECK: vbperm %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x85] +#CHECK: vbperm %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x85] +#CHECK: vbperm %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x85] +#CHECK: vbperm %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x85] + + vbperm %v0, %v0, %v0 + vbperm %v0, %v0, %v15 + vbperm %v0, %v0, %v31 + vbperm %v0, %v15, %v0 + vbperm %v0, %v31, %v0 + vbperm %v15, %v0, %v0 + vbperm %v31, %v0, %v0 + vbperm %v18, %v3, %v20 + +#CHECK: vcp %v0, %v0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x77] +#CHECK: vcp %v0, %v0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x77] +#CHECK: vcp %v15, %v0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x77] +#CHECK: vcp %v31, %v0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x77] +#CHECK: vcp %v0, %v15, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x77] +#CHECK: vcp %v0, %v31, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x77] +#CHECK: vcp %v3, %v18, 4 # encoding: [0xe6,0x03,0x20,0x40,0x02,0x77] + + vcp %v0, %v0, 0 + vcp %v0, %v0, 15 + vcp %v15, %v0, 0 + vcp %v31, %v0, 0 + vcp %v0, %v15, 0 + vcp %v0, %v31, 0 + vcp %v3, %v18, 4 + +#CHECK: vcvb %r0, %v0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x50] +#CHECK: vcvb %r0, %v0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x50] +#CHECK: vcvb %r15, %v0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x50] +#CHECK: vcvb %r0, %v15, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x50] +#CHECK: vcvb %r0, %v31, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x50] +#CHECK: vcvb %r3, %v18, 4 # encoding: [0xe6,0x32,0x00,0x40,0x04,0x50] + + vcvb %r0, %v0, 0 + vcvb %r0, %v0, 15 + vcvb %r15, %v0, 0 + vcvb %r0, %v15, 0 + vcvb %r0, %v31, 0 + vcvb %r3, %v18, 4 + +#CHECK: vcvbg %r0, %v0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x52] +#CHECK: vcvbg %r0, %v0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x52] +#CHECK: vcvbg %r15, %v0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x52] +#CHECK: vcvbg %r0, %v15, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x52] +#CHECK: vcvbg %r0, %v31, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x52] +#CHECK: vcvbg %r3, %v18, 4 # encoding: [0xe6,0x32,0x00,0x40,0x04,0x52] + + vcvbg %r0, %v0, 0 + vcvbg %r0, %v0, 15 + vcvbg %r15, %v0, 0 + vcvbg %r0, %v15, 0 + vcvbg %r0, %v31, 0 + vcvbg %r3, %v18, 4 + +#CHECK: vcvd %v0, %r0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x58] +#CHECK: vcvd %v0, %r0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x58] +#CHECK: vcvd %v0, %r0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x58] +#CHECK: vcvd %v0, %r15, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x58] +#CHECK: vcvd %v15, %r0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x58] +#CHECK: vcvd %v31, %r0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x58] +#CHECK: vcvd %v18, %r9, 52, 11 # encoding: [0xe6,0x29,0x00,0xb3,0x48,0x58] + + vcvd %v0, %r0, 0, 0 + vcvd %v0, %r0, 0, 15 + vcvd %v0, %r0, 255, 0 + vcvd %v0, %r15, 0, 0 + vcvd %v15, %r0, 0, 0 + vcvd %v31, %r0, 0, 0 + vcvd %v18, %r9, 0x34, 11 + +#CHECK: vcvdg %v0, %r0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x5a] +#CHECK: vcvdg %v0, %r0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x5a] +#CHECK: vcvdg %v0, %r0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x5a] +#CHECK: vcvdg %v0, %r15, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x5a] +#CHECK: vcvdg %v15, %r0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x5a] +#CHECK: vcvdg %v31, %r0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x5a] +#CHECK: vcvdg %v18, %r9, 52, 11 # encoding: [0xe6,0x29,0x00,0xb3,0x48,0x5a] + + vcvdg %v0, %r0, 0, 0 + vcvdg %v0, %r0, 0, 15 + vcvdg %v0, %r0, 255, 0 + vcvdg %v0, %r15, 0, 0 + vcvdg %v15, %r0, 0, 0 + vcvdg %v31, %r0, 0, 0 + vcvdg %v18, %r9, 0x34, 11 + +#CHECK: vdp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x7a] +#CHECK: vdp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x7a] +#CHECK: vdp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x7a] +#CHECK: vdp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x7a] +#CHECK: vdp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x7a] +#CHECK: vdp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x7a] +#CHECK: vdp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x7a] + + vdp %v0, %v0, %v0, 0, 0 + vdp %v0, %v0, %v0, 0, 15 + vdp %v0, %v0, %v0, 255, 0 + vdp %v0, %v0, %v31, 0, 0 + vdp %v0, %v31, %v0, 0, 0 + vdp %v31, %v0, %v0, 0, 0 + vdp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vfkedb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xe8] +#CHECK: vfkedb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x04,0x32,0xe8] +#CHECK: vfkedb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x04,0x34,0xe8] +#CHECK: vfkedb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x04,0x38,0xe8] +#CHECK: vfkedb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x04,0x3a,0xe8] + + vfkedb %v0, %v0, %v0 + vfkedb %v0, %v0, %v31 + vfkedb %v0, %v31, %v0 + vfkedb %v31, %v0, %v0 + vfkedb %v18, %v3, %v20 + +#CHECK: vfkedbs %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x14,0x30,0xe8] +#CHECK: vfkedbs %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x14,0x32,0xe8] +#CHECK: vfkedbs %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x14,0x34,0xe8] +#CHECK: vfkedbs %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x14,0x38,0xe8] +#CHECK: vfkedbs %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x14,0x3a,0xe8] + + vfkedbs %v0, %v0, %v0 + vfkedbs %v0, %v0, %v31 + vfkedbs %v0, %v31, %v0 + vfkedbs %v31, %v0, %v0 + vfkedbs %v18, %v3, %v20 + +#CHECK: vfkhdb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xeb] +#CHECK: vfkhdb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x04,0x32,0xeb] +#CHECK: vfkhdb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x04,0x34,0xeb] +#CHECK: vfkhdb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x04,0x38,0xeb] +#CHECK: vfkhdb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x04,0x3a,0xeb] + + vfkhdb %v0, %v0, %v0 + vfkhdb %v0, %v0, %v31 + vfkhdb %v0, %v31, %v0 + vfkhdb %v31, %v0, %v0 + vfkhdb %v18, %v3, %v20 + +#CHECK: vfkhdbs %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x14,0x30,0xeb] +#CHECK: vfkhdbs %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x14,0x32,0xeb] +#CHECK: vfkhdbs %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x14,0x34,0xeb] +#CHECK: vfkhdbs %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x14,0x38,0xeb] +#CHECK: vfkhdbs %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x14,0x3a,0xeb] + + vfkhdbs %v0, %v0, %v0 + vfkhdbs %v0, %v0, %v31 + vfkhdbs %v0, %v31, %v0 + vfkhdbs %v31, %v0, %v0 + vfkhdbs %v18, %v3, %v20 + +#CHECK: vfkhedb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xea] +#CHECK: vfkhedb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x04,0x32,0xea] +#CHECK: vfkhedb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x04,0x34,0xea] +#CHECK: vfkhedb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x04,0x38,0xea] +#CHECK: vfkhedb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x04,0x3a,0xea] + + vfkhedb %v0, %v0, %v0 + vfkhedb %v0, %v0, %v31 + vfkhedb %v0, %v31, %v0 + vfkhedb %v31, %v0, %v0 + vfkhedb %v18, %v3, %v20 + +#CHECK: vfkhedbs %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x14,0x30,0xea] +#CHECK: vfkhedbs %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x14,0x32,0xea] +#CHECK: vfkhedbs %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x14,0x34,0xea] +#CHECK: vfkhedbs %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x14,0x38,0xea] +#CHECK: vfkhedbs %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x14,0x3a,0xea] + + vfkhedbs %v0, %v0, %v0 + vfkhedbs %v0, %v0, %v31 + vfkhedbs %v0, %v31, %v0 + vfkhedbs %v31, %v0, %v0 + vfkhedbs %v18, %v3, %v20 + +#CHECK: vfmax %v0, %v0, %v0, 0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xef] +#CHECK: vfmax %v0, %v0, %v0, 15, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xef] +#CHECK: vfmax %v0, %v0, %v0, 0, 15, 0 # encoding: [0xe7,0x00,0x00,0x0f,0x00,0xef] +#CHECK: vfmax %v0, %v0, %v0, 0, 0, 4 # encoding: [0xe7,0x00,0x00,0x40,0x00,0xef] +#CHECK: vfmax %v0, %v0, %v31, 0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xef] +#CHECK: vfmax %v0, %v31, %v0, 0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xef] +#CHECK: vfmax %v31, %v0, %v0, 0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xef] +#CHECK: vfmax %v18, %v3, %v20, 11, 9, 12 # encoding: [0xe7,0x23,0x40,0xc9,0xba,0xef] + + vfmax %v0, %v0, %v0, 0, 0, 0 + vfmax %v0, %v0, %v0, 15, 0, 0 + vfmax %v0, %v0, %v0, 0, 15, 0 + vfmax %v0, %v0, %v0, 0, 0, 4 + vfmax %v0, %v0, %v31, 0, 0, 0 + vfmax %v0, %v31, %v0, 0, 0, 0 + vfmax %v31, %v0, %v0, 0, 0, 0 + vfmax %v18, %v3, %v20, 11, 9, 12 + +#CHECK: vfmaxdb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xef] +#CHECK: vfmaxdb %v0, %v0, %v0, 4 # encoding: [0xe7,0x00,0x00,0x40,0x30,0xef] +#CHECK: vfmaxdb %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xef] +#CHECK: vfmaxdb %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xef] +#CHECK: vfmaxdb %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xef] +#CHECK: vfmaxdb %v18, %v3, %v20, 12 # encoding: [0xe7,0x23,0x40,0xc0,0x3a,0xef] + + vfmaxdb %v0, %v0, %v0, 0 + vfmaxdb %v0, %v0, %v0, 4 + vfmaxdb %v0, %v0, %v31, 0 + vfmaxdb %v0, %v31, %v0, 0 + vfmaxdb %v31, %v0, %v0, 0 + vfmaxdb %v18, %v3, %v20, 12 + +#CHECK: vfmin %v0, %v0, %v0, 0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xee] +#CHECK: vfmin %v0, %v0, %v0, 15, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xee] +#CHECK: vfmin %v0, %v0, %v0, 0, 15, 0 # encoding: [0xe7,0x00,0x00,0x0f,0x00,0xee] +#CHECK: vfmin %v0, %v0, %v0, 0, 0, 4 # encoding: [0xe7,0x00,0x00,0x40,0x00,0xee] +#CHECK: vfmin %v0, %v0, %v31, 0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xee] +#CHECK: vfmin %v0, %v31, %v0, 0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xee] +#CHECK: vfmin %v31, %v0, %v0, 0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xee] +#CHECK: vfmin %v18, %v3, %v20, 11, 9, 12 # encoding: [0xe7,0x23,0x40,0xc9,0xba,0xee] + + vfmin %v0, %v0, %v0, 0, 0, 0 + vfmin %v0, %v0, %v0, 15, 0, 0 + vfmin %v0, %v0, %v0, 0, 15, 0 + vfmin %v0, %v0, %v0, 0, 0, 4 + vfmin %v0, %v0, %v31, 0, 0, 0 + vfmin %v0, %v31, %v0, 0, 0, 0 + vfmin %v31, %v0, %v0, 0, 0, 0 + vfmin %v18, %v3, %v20, 11, 9, 12 + +#CHECK: vfmindb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xee] +#CHECK: vfmindb %v0, %v0, %v0, 4 # encoding: [0xe7,0x00,0x00,0x40,0x30,0xee] +#CHECK: vfmindb %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xee] +#CHECK: vfmindb %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xee] +#CHECK: vfmindb %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xee] +#CHECK: vfmindb %v18, %v3, %v20, 12 # encoding: [0xe7,0x23,0x40,0xc0,0x3a,0xee] + + vfmindb %v0, %v0, %v0, 0 + vfmindb %v0, %v0, %v0, 4 + vfmindb %v0, %v0, %v31, 0 + vfmindb %v0, %v31, %v0, 0 + vfmindb %v31, %v0, %v0, 0 + vfmindb %v18, %v3, %v20, 12 + +#CHECK: vfnma %v0, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x9f] +#CHECK: vfnma %v0, %v0, %v0, %v0, 0, 15 # encoding: [0xe7,0x00,0x0f,0x00,0x00,0x9f] +#CHECK: vfnma %v0, %v0, %v0, %v0, 15, 0 # encoding: [0xe7,0x00,0x00,0x0f,0x00,0x9f] +#CHECK: vfnma %v0, %v0, %v0, %v31, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x9f] +#CHECK: vfnma %v0, %v0, %v31, %v0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x9f] +#CHECK: vfnma %v0, %v31, %v0, %v0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x9f] +#CHECK: vfnma %v31, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x9f] +#CHECK: vfnma %v13, %v17, %v21, %v25, 9, 11 # encoding: [0xe7,0xd1,0x5b,0x09,0x97,0x9f] + + vfnma %v0, %v0, %v0, %v0, 0, 0 + vfnma %v0, %v0, %v0, %v0, 0, 15 + vfnma %v0, %v0, %v0, %v0, 15, 0 + vfnma %v0, %v0, %v0, %v31, 0, 0 + vfnma %v0, %v0, %v31, %v0, 0, 0 + vfnma %v0, %v31, %v0, %v0, 0, 0 + vfnma %v31, %v0, %v0, %v0, 0, 0 + vfnma %v13, %v17, %v21, %v25, 9, 11 + +#CHECK: vfnmadb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x03,0x00,0x00,0x9f] +#CHECK: vfnmadb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x03,0x00,0xf1,0x9f] +#CHECK: vfnmadb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf3,0x00,0x02,0x9f] +#CHECK: vfnmadb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x03,0x00,0x04,0x9f] +#CHECK: vfnmadb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x03,0x00,0x08,0x9f] +#CHECK: vfnmadb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x00,0x97,0x9f] + + vfnmadb %v0, %v0, %v0, %v0 + vfnmadb %v0, %v0, %v0, %v31 + vfnmadb %v0, %v0, %v31, %v0 + vfnmadb %v0, %v31, %v0, %v0 + vfnmadb %v31, %v0, %v0, %v0 + vfnmadb %v13, %v17, %v21, %v25 + +#CHECK: vfnms %v0, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x9e] +#CHECK: vfnms %v0, %v0, %v0, %v0, 0, 15 # encoding: [0xe7,0x00,0x0f,0x00,0x00,0x9e] +#CHECK: vfnms %v0, %v0, %v0, %v0, 15, 0 # encoding: [0xe7,0x00,0x00,0x0f,0x00,0x9e] +#CHECK: vfnms %v0, %v0, %v0, %v31, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x9e] +#CHECK: vfnms %v0, %v0, %v31, %v0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x9e] +#CHECK: vfnms %v0, %v31, %v0, %v0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x9e] +#CHECK: vfnms %v31, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x9e] +#CHECK: vfnms %v13, %v17, %v21, %v25, 9, 11 # encoding: [0xe7,0xd1,0x5b,0x09,0x97,0x9e] + + vfnms %v0, %v0, %v0, %v0, 0, 0 + vfnms %v0, %v0, %v0, %v0, 0, 15 + vfnms %v0, %v0, %v0, %v0, 15, 0 + vfnms %v0, %v0, %v0, %v31, 0, 0 + vfnms %v0, %v0, %v31, %v0, 0, 0 + vfnms %v0, %v31, %v0, %v0, 0, 0 + vfnms %v31, %v0, %v0, %v0, 0, 0 + vfnms %v13, %v17, %v21, %v25, 9, 11 + +#CHECK: vfnmsdb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x03,0x00,0x00,0x9e] +#CHECK: vfnmsdb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x03,0x00,0xf1,0x9e] +#CHECK: vfnmsdb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf3,0x00,0x02,0x9e] +#CHECK: vfnmsdb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x03,0x00,0x04,0x9e] +#CHECK: vfnmsdb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x03,0x00,0x08,0x9e] +#CHECK: vfnmsdb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x00,0x97,0x9e] + + vfnmsdb %v0, %v0, %v0, %v0 + vfnmsdb %v0, %v0, %v0, %v31 + vfnmsdb %v0, %v0, %v31, %v0 + vfnmsdb %v0, %v31, %v0, %v0 + vfnmsdb %v31, %v0, %v0, %v0 + vfnmsdb %v13, %v17, %v21, %v25 + +#CHECK: vlip %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x49] +#CHECK: vlip %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x49] +#CHECK: vlip %v0, 65535, 0 # encoding: [0xe6,0x00,0xff,0xff,0x00,0x49] +#CHECK: vlip %v15, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x49] +#CHECK: vlip %v31, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x49] +#CHECK: vlip %v17, 4660, 7 # encoding: [0xe6,0x10,0x12,0x34,0x78,0x49] + + vlip %v0, 0, 0 + vlip %v0, 0, 15 + vlip %v0, 0xffff, 0 + vlip %v15, 0, 0 + vlip %v31, 0, 0 + vlip %v17, 0x1234, 7 + +#CHECK: vllezlf %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x60,0x04] +#CHECK: vllezlf %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x60,0x04] +#CHECK: vllezlf %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x60,0x04] +#CHECK: vllezlf %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x60,0x04] +#CHECK: vllezlf %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x60,0x04] +#CHECK: vllezlf %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x68,0x04] +#CHECK: vllezlf %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x68,0x04] + + vllezlf %v0, 0 + vllezlf %v0, 4095 + vllezlf %v0, 0(%r15) + vllezlf %v0, 0(%r15,%r1) + vllezlf %v15, 0 + vllezlf %v31, 0 + vllezlf %v18, 0x567(%r3,%r4) + +#CHECK: vlrl %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x35] +#CHECK: vlrl %v0, 4095, 0 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x35] +#CHECK: vlrl %v0, 0(%r15), 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x35] +#CHECK: vlrl %v0, 0, 255 # encoding: [0xe6,0xff,0x00,0x00,0x00,0x35] +#CHECK: vlrl %v15, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x35] +#CHECK: vlrl %v31, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x35] +#CHECK: vlrl %v18, 1383(%r4), 3 # encoding: [0xe6,0x03,0x45,0x67,0x21,0x35] + + vlrl %v0, 0, 0 + vlrl %v0, 4095, 0 + vlrl %v0, 0(%r15), 0 + vlrl %v0, 0, 255 + vlrl %v15, 0, 0 + vlrl %v31, 0, 0 + vlrl %v18, 1383(%r4), 3 + +#CHECK: vlrlr %v0, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x37] +#CHECK: vlrlr %v0, %r0, 4095 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x37] +#CHECK: vlrlr %v0, %r0, 0(%r15) # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x37] +#CHECK: vlrlr %v0, %r15, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x37] +#CHECK: vlrlr %v15, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x37] +#CHECK: vlrlr %v31, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x37] +#CHECK: vlrlr %v18, %r3, 1383(%r4) # encoding: [0xe6,0x03,0x45,0x67,0x21,0x37] + + vlrlr %v0, %r0, 0 + vlrlr %v0, %r0, 4095 + vlrlr %v0, %r0, 0(%r15) + vlrlr %v0, %r15, 0 + vlrlr %v15, %r0, 0 + vlrlr %v31, %r0, 0 + vlrlr %v18, %r3, 1383(%r4) + +#CHECK: vmsl %v0, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xb8] +#CHECK: vmsl %v0, %v0, %v0, %v0, 15, 0 # encoding: [0xe7,0x00,0x0f,0x00,0x00,0xb8] +#CHECK: vmsl %v0, %v0, %v0, %v0, 0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x00,0xb8] +#CHECK: vmsl %v0, %v0, %v0, %v15, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xb8] +#CHECK: vmsl %v0, %v0, %v0, %v31, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xb8] +#CHECK: vmsl %v0, %v0, %v15, %v0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0xb8] +#CHECK: vmsl %v0, %v0, %v31, %v0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xb8] +#CHECK: vmsl %v0, %v15, %v0, %v0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xb8] +#CHECK: vmsl %v0, %v31, %v0, %v0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xb8] +#CHECK: vmsl %v15, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xb8] +#CHECK: vmsl %v31, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xb8] +#CHECK: vmsl %v18, %v3, %v20, %v5, 0, 4 # encoding: [0xe7,0x23,0x40,0x40,0x5a,0xb8] +#CHECK: vmsl %v18, %v3, %v20, %v5, 11, 8 # encoding: [0xe7,0x23,0x4b,0x80,0x5a,0xb8] + + vmsl %v0, %v0, %v0, %v0, 0, 0 + vmsl %v0, %v0, %v0, %v0, 15, 0 + vmsl %v0, %v0, %v0, %v0, 0, 12 + vmsl %v0, %v0, %v0, %v15, 0, 0 + vmsl %v0, %v0, %v0, %v31, 0, 0 + vmsl %v0, %v0, %v15, %v0, 0, 0 + vmsl %v0, %v0, %v31, %v0, 0, 0 + vmsl %v0, %v15, %v0, %v0, 0, 0 + vmsl %v0, %v31, %v0, %v0, 0, 0 + vmsl %v15, %v0, %v0, %v0, 0, 0 + vmsl %v31, %v0, %v0, %v0, 0, 0 + vmsl %v18, %v3, %v20, %v5, 0, 4 + vmsl %v18, %v3, %v20, %v5, 11, 8 + +#CHECK: vmslg %v0, %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x03,0x00,0x00,0xb8] +#CHECK: vmslg %v0, %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x03,0xc0,0x00,0xb8] +#CHECK: vmslg %v0, %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0x03,0x00,0xf0,0xb8] +#CHECK: vmslg %v0, %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0x03,0x00,0xf1,0xb8] +#CHECK: vmslg %v0, %v0, %v15, %v0, 0 # encoding: [0xe7,0x00,0xf3,0x00,0x00,0xb8] +#CHECK: vmslg %v0, %v0, %v31, %v0, 0 # encoding: [0xe7,0x00,0xf3,0x00,0x02,0xb8] +#CHECK: vmslg %v0, %v15, %v0, %v0, 0 # encoding: [0xe7,0x0f,0x03,0x00,0x00,0xb8] +#CHECK: vmslg %v0, %v31, %v0, %v0, 0 # encoding: [0xe7,0x0f,0x03,0x00,0x04,0xb8] +#CHECK: vmslg %v15, %v0, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x03,0x00,0x00,0xb8] +#CHECK: vmslg %v31, %v0, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x03,0x00,0x08,0xb8] +#CHECK: vmslg %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x43,0x40,0x5a,0xb8] +#CHECK: vmslg %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x43,0x80,0x5a,0xb8] + + vmslg %v0, %v0, %v0, %v0, 0 + vmslg %v0, %v0, %v0, %v0, 12 + vmslg %v0, %v0, %v0, %v15, 0 + vmslg %v0, %v0, %v0, %v31, 0 + vmslg %v0, %v0, %v15, %v0, 0 + vmslg %v0, %v0, %v31, %v0, 0 + vmslg %v0, %v15, %v0, %v0, 0 + vmslg %v0, %v31, %v0, %v0, 0 + vmslg %v15, %v0, %v0, %v0, 0 + vmslg %v31, %v0, %v0, %v0, 0 + vmslg %v18, %v3, %v20, %v5, 4 + vmslg %v18, %v3, %v20, %v5, 8 + +#CHECK: vmp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x78] +#CHECK: vmp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x78] +#CHECK: vmp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x78] +#CHECK: vmp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x78] +#CHECK: vmp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x78] +#CHECK: vmp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x78] +#CHECK: vmp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x78] + + vmp %v0, %v0, %v0, 0, 0 + vmp %v0, %v0, %v0, 0, 15 + vmp %v0, %v0, %v0, 255, 0 + vmp %v0, %v0, %v31, 0, 0 + vmp %v0, %v31, %v0, 0, 0 + vmp %v31, %v0, %v0, 0, 0 + vmp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vmsp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x79] +#CHECK: vmsp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x79] +#CHECK: vmsp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x79] +#CHECK: vmsp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x79] +#CHECK: vmsp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x79] +#CHECK: vmsp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x79] +#CHECK: vmsp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x79] + + vmsp %v0, %v0, %v0, 0, 0 + vmsp %v0, %v0, %v0, 0, 15 + vmsp %v0, %v0, %v0, 255, 0 + vmsp %v0, %v0, %v31, 0, 0 + vmsp %v0, %v31, %v0, 0, 0 + vmsp %v31, %v0, %v0, 0, 0 + vmsp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vnn %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6e] +#CHECK: vnn %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6e] +#CHECK: vnn %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6e] +#CHECK: vnn %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6e] +#CHECK: vnn %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6e] + + vnn %v0, %v0, %v0 + vnn %v0, %v0, %v31 + vnn %v0, %v31, %v0 + vnn %v31, %v0, %v0 + vnn %v18, %v3, %v20 + +#CHECK: vnx %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6c] +#CHECK: vnx %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6c] +#CHECK: vnx %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6c] +#CHECK: vnx %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6c] +#CHECK: vnx %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6c] + + vnx %v0, %v0, %v0 + vnx %v0, %v0, %v31 + vnx %v0, %v31, %v0 + vnx %v31, %v0, %v0 + vnx %v18, %v3, %v20 + +#CHECK: voc %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6f] +#CHECK: voc %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6f] +#CHECK: voc %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6f] +#CHECK: voc %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6f] +#CHECK: voc %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6f] + + voc %v0, %v0, %v0 + voc %v0, %v0, %v31 + voc %v0, %v31, %v0 + voc %v31, %v0, %v0 + voc %v18, %v3, %v20 + +#CHECK: vpkz %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x34] +#CHECK: vpkz %v0, 4095, 0 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x34] +#CHECK: vpkz %v0, 0(%r15), 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x34] +#CHECK: vpkz %v0, 0, 255 # encoding: [0xe6,0xff,0x00,0x00,0x00,0x34] +#CHECK: vpkz %v15, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x34] +#CHECK: vpkz %v31, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x34] +#CHECK: vpkz %v18, 1383(%r4), 3 # encoding: [0xe6,0x03,0x45,0x67,0x21,0x34] + + vpkz %v0, 0, 0 + vpkz %v0, 4095, 0 + vpkz %v0, 0(%r15), 0 + vpkz %v0, 0, 255 + vpkz %v15, 0, 0 + vpkz %v31, 0, 0 + vpkz %v18, 1383(%r4), 3 + +#CHECK: vpopctb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x50] +#CHECK: vpopctb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x50] +#CHECK: vpopctb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x50] +#CHECK: vpopctb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x50] +#CHECK: vpopctb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x50] +#CHECK: vpopctb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x50] + + vpopctb %v0, %v0 + vpopctb %v0, %v15 + vpopctb %v0, %v31 + vpopctb %v15, %v0 + vpopctb %v31, %v0 + vpopctb %v14, %v17 + +#CHECK: vpopctf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x50] +#CHECK: vpopctf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x50] +#CHECK: vpopctf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x50] +#CHECK: vpopctf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x50] +#CHECK: vpopctf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x50] +#CHECK: vpopctf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0x50] + + vpopctf %v0, %v0 + vpopctf %v0, %v15 + vpopctf %v0, %v31 + vpopctf %v15, %v0 + vpopctf %v31, %v0 + vpopctf %v14, %v17 + +#CHECK: vpopctg %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x50] +#CHECK: vpopctg %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x50] +#CHECK: vpopctg %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x50] +#CHECK: vpopctg %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x50] +#CHECK: vpopctg %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x50] +#CHECK: vpopctg %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0x50] + + vpopctg %v0, %v0 + vpopctg %v0, %v15 + vpopctg %v0, %v31 + vpopctg %v15, %v0 + vpopctg %v31, %v0 + vpopctg %v14, %v17 + +#CHECK: vpopcth %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x50] +#CHECK: vpopcth %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x50] +#CHECK: vpopcth %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x50] +#CHECK: vpopcth %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x50] +#CHECK: vpopcth %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x50] +#CHECK: vpopcth %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0x50] + + vpopcth %v0, %v0 + vpopcth %v0, %v15 + vpopcth %v0, %v31 + vpopcth %v15, %v0 + vpopcth %v31, %v0 + vpopcth %v14, %v17 + +#CHECK: vpsop %v0, %v0, 0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x5b] +#CHECK: vpsop %v0, %v0, 0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x5b] +#CHECK: vpsop %v0, %v0, 0, 255, 0 # encoding: [0xe6,0x00,0xff,0x00,0x00,0x5b] +#CHECK: vpsop %v0, %v0, 255, 0, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x5b] +#CHECK: vpsop %v0, %v31, 0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x5b] +#CHECK: vpsop %v31, %v0, 0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x5b] +#CHECK: vpsop %v13, %v17, 52, 121, 11 # encoding: [0xe6,0xd1,0x79,0xb3,0x44,0x5b] + + vpsop %v0, %v0, 0, 0, 0 + vpsop %v0, %v0, 0, 0, 15 + vpsop %v0, %v0, 0, 255, 0 + vpsop %v0, %v0, 255, 0, 0 + vpsop %v0, %v31, 0, 0, 0 + vpsop %v31, %v0, 0, 0, 0 + vpsop %v13, %v17, 0x34, 0x79, 11 + +#CHECK: vrp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x7b] +#CHECK: vrp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x7b] +#CHECK: vrp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x7b] +#CHECK: vrp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x7b] +#CHECK: vrp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x7b] +#CHECK: vrp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x7b] +#CHECK: vrp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x7b] + + vrp %v0, %v0, %v0, 0, 0 + vrp %v0, %v0, %v0, 0, 15 + vrp %v0, %v0, %v0, 255, 0 + vrp %v0, %v0, %v31, 0, 0 + vrp %v0, %v31, %v0, 0, 0 + vrp %v31, %v0, %v0, 0, 0 + vrp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vsdp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x7e] +#CHECK: vsdp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x7e] +#CHECK: vsdp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x7e] +#CHECK: vsdp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x7e] +#CHECK: vsdp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x7e] +#CHECK: vsdp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x7e] +#CHECK: vsdp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x7e] + + vsdp %v0, %v0, %v0, 0, 0 + vsdp %v0, %v0, %v0, 0, 15 + vsdp %v0, %v0, %v0, 255, 0 + vsdp %v0, %v0, %v31, 0, 0 + vsdp %v0, %v31, %v0, 0, 0 + vsdp %v31, %v0, %v0, 0, 0 + vsdp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vsp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x73] +#CHECK: vsp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x73] +#CHECK: vsp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x73] +#CHECK: vsp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x73] +#CHECK: vsp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x73] +#CHECK: vsp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x73] +#CHECK: vsp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x73] + + vsp %v0, %v0, %v0, 0, 0 + vsp %v0, %v0, %v0, 0, 15 + vsp %v0, %v0, %v0, 255, 0 + vsp %v0, %v0, %v31, 0, 0 + vsp %v0, %v31, %v0, 0, 0 + vsp %v31, %v0, %v0, 0, 0 + vsp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vsrp %v0, %v0, 0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x59] +#CHECK: vsrp %v0, %v0, 0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x59] +#CHECK: vsrp %v0, %v0, 0, 255, 0 # encoding: [0xe6,0x00,0xff,0x00,0x00,0x59] +#CHECK: vsrp %v0, %v0, 255, 0, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x59] +#CHECK: vsrp %v0, %v31, 0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x59] +#CHECK: vsrp %v31, %v0, 0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x59] +#CHECK: vsrp %v13, %v17, 52, 121, 11 # encoding: [0xe6,0xd1,0x79,0xb3,0x44,0x59] + + vsrp %v0, %v0, 0, 0, 0 + vsrp %v0, %v0, 0, 0, 15 + vsrp %v0, %v0, 0, 255, 0 + vsrp %v0, %v0, 255, 0, 0 + vsrp %v0, %v31, 0, 0, 0 + vsrp %v31, %v0, 0, 0, 0 + vsrp %v13, %v17, 0x34, 0x79, 11 + +#CHECK: vstrl %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x3d] +#CHECK: vstrl %v0, 4095, 0 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x3d] +#CHECK: vstrl %v0, 0(%r15), 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x3d] +#CHECK: vstrl %v0, 0, 255 # encoding: [0xe6,0xff,0x00,0x00,0x00,0x3d] +#CHECK: vstrl %v15, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x3d] +#CHECK: vstrl %v31, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x3d] +#CHECK: vstrl %v18, 1383(%r4), 3 # encoding: [0xe6,0x03,0x45,0x67,0x21,0x3d] + + vstrl %v0, 0, 0 + vstrl %v0, 4095, 0 + vstrl %v0, 0(%r15), 0 + vstrl %v0, 0, 255 + vstrl %v15, 0, 0 + vstrl %v31, 0, 0 + vstrl %v18, 1383(%r4), 3 + +#CHECK: vstrlr %v0, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x3f] +#CHECK: vstrlr %v0, %r0, 4095 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x3f] +#CHECK: vstrlr %v0, %r0, 0(%r15) # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x3f] +#CHECK: vstrlr %v0, %r15, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x3f] +#CHECK: vstrlr %v15, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x3f] +#CHECK: vstrlr %v31, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x3f] +#CHECK: vstrlr %v18, %r3, 1383(%r4) # encoding: [0xe6,0x03,0x45,0x67,0x21,0x3f] + + vstrlr %v0, %r0, 0 + vstrlr %v0, %r0, 4095 + vstrlr %v0, %r0, 0(%r15) + vstrlr %v0, %r15, 0 + vstrlr %v15, %r0, 0 + vstrlr %v31, %r0, 0 + vstrlr %v18, %r3, 1383(%r4) + +#CHECK: vtp %v0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x5f] +#CHECK: vtp %v15 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x5f] +#CHECK: vtp %v31 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x5f] + + vtp %v0 + vtp %v15 + vtp %v31 + +#CHECK: vupkz %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x3c] +#CHECK: vupkz %v0, 4095, 0 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x3c] +#CHECK: vupkz %v0, 0(%r15), 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x3c] +#CHECK: vupkz %v0, 0, 255 # encoding: [0xe6,0xff,0x00,0x00,0x00,0x3c] +#CHECK: vupkz %v15, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x3c] +#CHECK: vupkz %v31, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x3c] +#CHECK: vupkz %v18, 1383(%r4), 3 # encoding: [0xe6,0x03,0x45,0x67,0x21,0x3c] + + vupkz %v0, 0, 0 + vupkz %v0, 4095, 0 + vupkz %v0, 0(%r15), 0 + vupkz %v0, 0, 255 + vupkz %v15, 0, 0 + vupkz %v31, 0, 0 + vupkz %v18, 1383(%r4), 3 + +#CHECK: wfkedb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xe8] +#CHECK: wfkedb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xe8] +#CHECK: wfkedb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x0c,0x32,0xe8] +#CHECK: wfkedb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x0c,0x34,0xe8] +#CHECK: wfkedb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x0c,0x38,0xe8] +#CHECK: wfkedb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x0c,0x3a,0xe8] + + wfkedb %v0, %v0, %v0 + wfkedb %f0, %f0, %f0 + wfkedb %v0, %v0, %v31 + wfkedb %v0, %v31, %v0 + wfkedb %v31, %v0, %v0 + wfkedb %v18, %v3, %v20 + +#CHECK: wfkedbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xe8] +#CHECK: wfkedbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xe8] +#CHECK: wfkedbs %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x1c,0x32,0xe8] +#CHECK: wfkedbs %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x1c,0x34,0xe8] +#CHECK: wfkedbs %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x1c,0x38,0xe8] +#CHECK: wfkedbs %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x1c,0x3a,0xe8] + + wfkedbs %v0, %v0, %v0 + wfkedbs %f0, %f0, %f0 + wfkedbs %v0, %v0, %v31 + wfkedbs %v0, %v31, %v0 + wfkedbs %v31, %v0, %v0 + wfkedbs %v18, %v3, %v20 + +#CHECK: wfkhdb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xeb] +#CHECK: wfkhdb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xeb] +#CHECK: wfkhdb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x0c,0x32,0xeb] +#CHECK: wfkhdb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x0c,0x34,0xeb] +#CHECK: wfkhdb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x0c,0x38,0xeb] +#CHECK: wfkhdb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x0c,0x3a,0xeb] + + wfkhdb %v0, %v0, %v0 + wfkhdb %f0, %f0, %f0 + wfkhdb %v0, %v0, %v31 + wfkhdb %v0, %v31, %v0 + wfkhdb %v31, %v0, %v0 + wfkhdb %v18, %v3, %v20 + +#CHECK: wfkhdbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xeb] +#CHECK: wfkhdbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xeb] +#CHECK: wfkhdbs %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x1c,0x32,0xeb] +#CHECK: wfkhdbs %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x1c,0x34,0xeb] +#CHECK: wfkhdbs %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x1c,0x38,0xeb] +#CHECK: wfkhdbs %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x1c,0x3a,0xeb] + + wfkhdbs %v0, %v0, %v0 + wfkhdbs %f0, %f0, %f0 + wfkhdbs %v0, %v0, %v31 + wfkhdbs %v0, %v31, %v0 + wfkhdbs %v31, %v0, %v0 + wfkhdbs %v18, %v3, %v20 + +#CHECK: wfkhedb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xea] +#CHECK: wfkhedb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xea] +#CHECK: wfkhedb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x0c,0x32,0xea] +#CHECK: wfkhedb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x0c,0x34,0xea] +#CHECK: wfkhedb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x0c,0x38,0xea] +#CHECK: wfkhedb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x0c,0x3a,0xea] + + wfkhedb %v0, %v0, %v0 + wfkhedb %f0, %f0, %f0 + wfkhedb %v0, %v0, %v31 + wfkhedb %v0, %v31, %v0 + wfkhedb %v31, %v0, %v0 + wfkhedb %v18, %v3, %v20 + +#CHECK: wfkhedbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xea] +#CHECK: wfkhedbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xea] +#CHECK: wfkhedbs %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x1c,0x32,0xea] +#CHECK: wfkhedbs %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x1c,0x34,0xea] +#CHECK: wfkhedbs %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x1c,0x38,0xea] +#CHECK: wfkhedbs %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x1c,0x3a,0xea] + + wfkhedbs %v0, %v0, %v0 + wfkhedbs %f0, %f0, %f0 + wfkhedbs %v0, %v0, %v31 + wfkhedbs %v0, %v31, %v0 + wfkhedbs %v31, %v0, %v0 + wfkhedbs %v18, %v3, %v20 + +#CHECK: wfmaxdb %f0, %f0, %f0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xef] +#CHECK: wfmaxdb %f0, %f0, %f0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xef] +#CHECK: wfmaxdb %f0, %f0, %f0, 4 # encoding: [0xe7,0x00,0x00,0x48,0x30,0xef] +#CHECK: wfmaxdb %f0, %f0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xef] +#CHECK: wfmaxdb %f0, %v31, %f0, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xef] +#CHECK: wfmaxdb %v31, %f0, %f0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xef] +#CHECK: wfmaxdb %v18, %f3, %v20, 11 # encoding: [0xe7,0x23,0x40,0xb8,0x3a,0xef] + + wfmaxdb %v0, %v0, %v0, 0 + wfmaxdb %f0, %f0, %f0, 0 + wfmaxdb %v0, %v0, %v0, 4 + wfmaxdb %v0, %v0, %v31, 0 + wfmaxdb %v0, %v31, %v0, 0 + wfmaxdb %v31, %v0, %v0, 0 + wfmaxdb %v18, %v3, %v20, 11 + +#CHECK: wfmindb %f0, %f0, %f0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xee] +#CHECK: wfmindb %f0, %f0, %f0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xee] +#CHECK: wfmindb %f0, %f0, %f0, 4 # encoding: [0xe7,0x00,0x00,0x48,0x30,0xee] +#CHECK: wfmindb %f0, %f0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xee] +#CHECK: wfmindb %f0, %v31, %f0, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xee] +#CHECK: wfmindb %v31, %f0, %f0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xee] +#CHECK: wfmindb %v18, %f3, %v20, 11 # encoding: [0xe7,0x23,0x40,0xb8,0x3a,0xee] + + wfmindb %v0, %v0, %v0, 0 + wfmindb %f0, %f0, %f0, 0 + wfmindb %v0, %v0, %v0, 4 + wfmindb %v0, %v0, %v31, 0 + wfmindb %v0, %v31, %v0, 0 + wfmindb %v31, %v0, %v0, 0 + wfmindb %v18, %v3, %v20, 11 + +#CHECK: wfnmadb %f0, %f0, %f0, %f0 # encoding: [0xe7,0x00,0x03,0x08,0x00,0x9f] +#CHECK: wfnmadb %f0, %f0, %f0, %f0 # encoding: [0xe7,0x00,0x03,0x08,0x00,0x9f] +#CHECK: wfnmadb %f0, %f0, %f0, %v31 # encoding: [0xe7,0x00,0x03,0x08,0xf1,0x9f] +#CHECK: wfnmadb %f0, %f0, %v31, %f0 # encoding: [0xe7,0x00,0xf3,0x08,0x02,0x9f] +#CHECK: wfnmadb %f0, %v31, %f0, %f0 # encoding: [0xe7,0x0f,0x03,0x08,0x04,0x9f] +#CHECK: wfnmadb %v31, %f0, %f0, %f0 # encoding: [0xe7,0xf0,0x03,0x08,0x08,0x9f] +#CHECK: wfnmadb %f13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x08,0x97,0x9f] + + wfnmadb %v0, %v0, %v0, %v0 + wfnmadb %f0, %f0, %f0, %f0 + wfnmadb %v0, %v0, %v0, %v31 + wfnmadb %v0, %v0, %v31, %v0 + wfnmadb %v0, %v31, %v0, %v0 + wfnmadb %v31, %v0, %v0, %v0 + wfnmadb %v13, %v17, %v21, %v25 + +#CHECK: wfnmsdb %f0, %f0, %f0, %f0 # encoding: [0xe7,0x00,0x03,0x08,0x00,0x9e] +#CHECK: wfnmsdb %f0, %f0, %f0, %f0 # encoding: [0xe7,0x00,0x03,0x08,0x00,0x9e] +#CHECK: wfnmsdb %f0, %f0, %f0, %v31 # encoding: [0xe7,0x00,0x03,0x08,0xf1,0x9e] +#CHECK: wfnmsdb %f0, %f0, %v31, %f0 # encoding: [0xe7,0x00,0xf3,0x08,0x02,0x9e] +#CHECK: wfnmsdb %f0, %v31, %f0, %f0 # encoding: [0xe7,0x0f,0x03,0x08,0x04,0x9e] +#CHECK: wfnmsdb %v31, %f0, %f0, %f0 # encoding: [0xe7,0xf0,0x03,0x08,0x08,0x9e] +#CHECK: wfnmsdb %f13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x08,0x97,0x9e] + + wfnmsdb %v0, %v0, %v0, %v0 + wfnmsdb %f0, %f0, %f0, %f0 + wfnmsdb %v0, %v0, %v0, %v31 + wfnmsdb %v0, %v0, %v31, %v0 + wfnmsdb %v0, %v31, %v0, %v0 + wfnmsdb %v31, %v0, %v0, %v0 + wfnmsdb %v13, %v17, %v21, %v25 + |
