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-rw-r--r--llvm/test/MC/Disassembler/Mips/dsp/valid-el.txt3
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt7
-rw-r--r--llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt7
-rw-r--r--llvm/test/MC/Mips/dsp/invalid.s4
-rw-r--r--llvm/test/MC/Mips/dsp/valid.s4
-rw-r--r--llvm/test/MC/Mips/dspr2/valid.s4
-rw-r--r--llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s7
-rw-r--r--llvm/test/MC/Mips/micromips-dsp/invalid.s2
-rw-r--r--llvm/test/MC/Mips/micromips-dsp/valid.s8
-rw-r--r--llvm/test/MC/Mips/micromips-dspr2/valid.s8
-rw-r--r--llvm/test/MC/Mips/micromips-invalid.s5
-rw-r--r--llvm/test/MC/Mips/micromips32r6/invalid.s1
-rw-r--r--llvm/test/MC/Mips/mips32r6/invalid.s1
-rw-r--r--llvm/test/MC/Mips/mips64r6/invalid.s1
14 files changed, 62 insertions, 0 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/dsp/valid-el.txt b/llvm/test/MC/Disassembler/Mips/dsp/valid-el.txt
index f7efe34671b..56f363b62a2 100644
--- a/llvm/test/MC/Disassembler/Mips/dsp/valid-el.txt
+++ b/llvm/test/MC/Disassembler/Mips/dsp/valid-el.txt
@@ -7,3 +7,6 @@
0x8a 0x51 0x54 0x7f # CHECK: lbux $10, $20($26)
0x0a 0x59 0x75 0x7f # CHECK: lhx $11, $21($27)
0x0a 0x60 0x96 0x7f # CHECK: lwx $12, $22($gp)
+0xb8 0x0e 0x30 0x7c # CHECK: shilo $ac1, 3
+0xf8 0x14 0xa0 0x7c # CHECK: wrdsp $5, 2
+0xf8 0xfc 0xa0 0x7c # CHECK: wrdsp $5
diff --git a/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
index 7fef4e2d08c..fdd404c4349 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
@@ -32,6 +32,9 @@
0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
+0x00 0xa4 0x19 0xad # CHECK: packrl.ph $3, $4, $5
+0x00 0xa4 0x1a 0x2d # CHECK: pick.ph $3, $4, $5
+0x00 0xa4 0x19 0xed # CHECK: pick.qb $3, $4, $5
0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2
0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4
0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
@@ -46,6 +49,8 @@
0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16
0x02 0x72 0x89 0x2d # CHECK: precrq_rs.ph.w $17, $18, $19
+0x00 0x03 0x40 0x1d # CHECK: shilo $ac1, 3
+0x00 0x05 0x52 0x7c # CHECK: shilov $ac1, $5
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
@@ -94,3 +99,5 @@
0x00 0x22 0x03 0x3c # CHECK: replv.ph $1, $2
0x00 0x22 0x13 0x3c # CHECK: replv.qb $1, $2
0x00 0x01 0x82 0x7c # CHECK: mthlip $1, $ac2
+0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5
+0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2
diff --git a/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt b/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
index 096b5bda4a3..1d9fc9e80d7 100644
--- a/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
+++ b/llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
@@ -45,6 +45,9 @@
0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
+0x00 0xa4 0x19 0xad # CHECK: packrl.ph $3, $4, $5
+0x00 0xa4 0x1a 0x2d # CHECK: pick.ph $3, $4, $5
+0x00 0xa4 0x19 0xed # CHECK: pick.qb $3, $4, $5
0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2
0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4
0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
@@ -62,6 +65,8 @@
0x01 0xac 0x58 0xad # CHECK: precrq.qb.ph $11, $12, $13
0x02 0x0f 0x71 0x6d # CHECK: precrqu_s.qb.ph $14, $15, $16
0x02 0x72 0x89 0x2d # CHECK: precrq_rs.ph.w $17, $18, $19
+0x00 0x03 0x40 0x1d # CHECK: shilo $ac1, 3
+0x00 0x05 0x52 0x7c # CHECK: shilov $ac1, $5
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
@@ -116,3 +121,5 @@
0x00 0x62 0x08 0xd5 # CHECK: muleu_s.ph.qbr $1, $2, $3
0x00,0x62,0x09,0x15 # CHECK: mulq_rs.ph $1, $2, $3
0x00 0x22 0x1a 0x55 # CHECK: prepend $1, $2, 3
+0x00 0xa7 0xd6 0x7c # CHECK: wrdsp $5
+0x00 0xa0 0x96 0x7c # CHECK: wrdsp $5, 2
diff --git a/llvm/test/MC/Mips/dsp/invalid.s b/llvm/test/MC/Mips/dsp/invalid.s
index 9ab471e0100..8bd0906e67f 100644
--- a/llvm/test/MC/Mips/dsp/invalid.s
+++ b/llvm/test/MC/Mips/dsp/invalid.s
@@ -19,3 +19,7 @@
shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
+ shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
+ shilo $ac1, -64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
+ wrdsp $5, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
+ wrdsp $5, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
diff --git a/llvm/test/MC/Mips/dsp/valid.s b/llvm/test/MC/Mips/dsp/valid.s
index 804669c5e46..f5926f3e259 100644
--- a/llvm/test/MC/Mips/dsp/valid.s
+++ b/llvm/test/MC/Mips/dsp/valid.s
@@ -101,6 +101,7 @@
repl.qb $1, 85 # CHECK: repl.qb $1, 85 # encoding: [0x7c,0x55,0x08,0x92]
replv.ph $1, $2 # CHECK: replv.ph $1, $2 # encoding: [0x7c,0x02,0x0a,0xd2]
replv.qb $1, $2 # CHECK: replv.qb $1, $2 # encoding: [0x7c,0x02,0x08,0xd2]
+ shilo $ac1, 3 # CHECK: shilo $ac1, 3 # encoding: [0x7c,0x30,0x0e,0xb8]
shilo $ac1, 16 # CHECK: shilo $ac1, 16 # encoding: [0x7d,0x00,0x0e,0xb8]
shilov $ac1, $2 # CHECK: shilov $ac1, $2 # encoding: [0x7c,0x40,0x0e,0xf8]
shll.ph $1, $2, 3 # CHECK: shll.ph $1, $2, 3 # encoding: [0x7c,0x62,0x0a,0x13]
@@ -125,3 +126,6 @@
subu.qb $1, $2, $3 # CHECK: subu.qb $1, $2, $3 # encoding: [0x7c,0x43,0x08,0x50]
subu_s.qb $1, $2, $3 # CHECK: subu_s.qb $1, $2, $3 # encoding: [0x7c,0x43,0x09,0x50]
wrdsp $1, 0 # CHECK: wrdsp $1, 0 # encoding: [0x7c,0x20,0x04,0xf8]
+ wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x7c,0xa0,0xfc,0xf8]
+ wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x7c,0xa0,0x14,0xf8]
+ wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x7c,0xa0,0xfc,0xf8]
diff --git a/llvm/test/MC/Mips/dspr2/valid.s b/llvm/test/MC/Mips/dspr2/valid.s
index ce9bd7309d7..c50e9d6e5ae 100644
--- a/llvm/test/MC/Mips/dspr2/valid.s
+++ b/llvm/test/MC/Mips/dspr2/valid.s
@@ -135,6 +135,7 @@
repl.qb $1, 85 # CHECK: repl.qb $1, 85 # encoding: [0x7c,0x55,0x08,0x92]
replv.ph $1, $2 # CHECK: replv.ph $1, $2 # encoding: [0x7c,0x02,0x0a,0xd2]
replv.qb $1, $2 # CHECK: replv.qb $1, $2 # encoding: [0x7c,0x02,0x08,0xd2]
+ shilo $ac1, 3 # CHECK: shilo $ac1, 3 # encoding: [0x7c,0x30,0x0e,0xb8]
shilo $ac1, 16 # CHECK: shilo $ac1, 16 # encoding: [0x7d,0x00,0x0e,0xb8]
shilov $ac1, $2 # CHECK: shilov $ac1, $2 # encoding: [0x7c,0x40,0x0e,0xf8]
shll.ph $1, $2, 3 # CHECK: shll.ph $1, $2, 3 # encoding: [0x7c,0x62,0x0a,0x13]
@@ -173,3 +174,6 @@
subuh.qb $1, $2, $3 # CHECK: subuh.qb $1, $2, $3 # encoding: [0x7c,0x43,0x08,0x58]
subuh_r.qb $1, $2, $3 # CHECK: subuh_r.qb $1, $2, $3 # encoding: [0x7c,0x43,0x08,0xd8]
wrdsp $1, 0 # CHECK: wrdsp $1, 0 # encoding: [0x7c,0x20,0x04,0xf8]
+ wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x7c,0xa0,0xfc,0xf8]
+ wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x7c,0xa0,0x14,0xf8]
+ wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x7c,0xa0,0xfc,0xf8]
diff --git a/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s
new file mode 100644
index 00000000000..d1ba873809d
--- /dev/null
+++ b/llvm/test/MC/Mips/micromips-dsp/invalid-wrong-error.s
@@ -0,0 +1,7 @@
+# Instructions that are correctly rejected but emit a wrong or misleading error.
+# RUN: not llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp 2>%t1
+# RUN: FileCheck %s < %t1
+
+ .set noat
+ wrdsp $5, 128 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+ wrdsp $5, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate
diff --git a/llvm/test/MC/Mips/micromips-dsp/invalid.s b/llvm/test/MC/Mips/micromips-dsp/invalid.s
index 8c631e0447b..55a6f8e2873 100644
--- a/llvm/test/MC/Mips/micromips-dsp/invalid.s
+++ b/llvm/test/MC/Mips/micromips-dsp/invalid.s
@@ -19,3 +19,5 @@
shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate
shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate
+ shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
+ shilo $ac1, -64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate
diff --git a/llvm/test/MC/Mips/micromips-dsp/valid.s b/llvm/test/MC/Mips/micromips-dsp/valid.s
index 85e3cd6f4b9..c147a6d850a 100644
--- a/llvm/test/MC/Mips/micromips-dsp/valid.s
+++ b/llvm/test/MC/Mips/micromips-dsp/valid.s
@@ -33,6 +33,9 @@
msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc]
mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc]
multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
+ packrl.ph $3, $4, $5 # CHECK: packrl.ph $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xad]
+ pick.ph $3, $4, $5 # CHECK: pick.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x2d]
+ pick.qb $3, $4, $5 # CHECK: pick.qb $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xed]
preceq.w.phl $1, $2 # CHECK: preceq.w.phl $1, $2 # encoding: [0x00,0x22,0x51,0x3c]
preceq.w.phr $3, $4 # CHECK: preceq.w.phr $3, $4 # encoding: [0x00,0x64,0x61,0x3c]
precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c]
@@ -47,6 +50,8 @@
precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0xad]
precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0x6d]
precrq_rs.ph.w $17, $18, $19 # CHECK: precrq_rs.ph.w $17, $18, $19 # encoding: [0x02,0x72,0x89,0x2d]
+ shilo $ac1, 3 # CHECK: shilo $ac1, 3 # encoding: [0x00,0x03,0x40,0x1d]
+ shilov $ac1, $5 # CHECK: shilov $ac1, $5 # encoding: [0x00,0x05,0x52,0x7c]
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
@@ -95,3 +100,6 @@
replv.ph $1, $2 # CHECK: replv.ph $1, $2 # encoding: [0x00,0x22,0x03,0x3c]
replv.qb $1, $2 # CHECK: replv.qb $1, $2 # encoding: [0x00,0x22,0x13,0x3c]
mthlip $1, $ac2 # CHECK: mthlip $1, $ac2 # encoding: [0x00,0x01,0x82,0x7c]
+ wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c]
+ wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x00,0xa0,0x96,0x7c]
+ wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c]
diff --git a/llvm/test/MC/Mips/micromips-dspr2/valid.s b/llvm/test/MC/Mips/micromips-dspr2/valid.s
index b236aea152a..b1d09cbc84c 100644
--- a/llvm/test/MC/Mips/micromips-dspr2/valid.s
+++ b/llvm/test/MC/Mips/micromips-dspr2/valid.s
@@ -46,6 +46,9 @@
msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc]
mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc]
multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
+ packrl.ph $3, $4, $5 # CHECK: packrl.ph $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xad]
+ pick.ph $3, $4, $5 # CHECK: pick.ph $3, $4, $5 # encoding: [0x00,0xa4,0x1a,0x2d]
+ pick.qb $3, $4, $5 # CHECK: pick.qb $3, $4, $5 # encoding: [0x00,0xa4,0x19,0xed]
preceq.w.phl $1, $2 # CHECK: preceq.w.phl $1, $2 # encoding: [0x00,0x22,0x51,0x3c]
preceq.w.phr $3, $4 # CHECK: preceq.w.phr $3, $4 # encoding: [0x00,0x64,0x61,0x3c]
precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c]
@@ -63,6 +66,8 @@
precrq.qb.ph $11, $12, $13 # CHECK: precrq.qb.ph $11, $12, $13 # encoding: [0x01,0xac,0x58,0xad]
precrqu_s.qb.ph $14, $15, $16 # CHECK: precrqu_s.qb.ph $14, $15, $16 # encoding: [0x02,0x0f,0x71,0x6d]
precrq_rs.ph.w $17, $18, $19 # CHECK: precrq_rs.ph.w $17, $18, $19 # encoding: [0x02,0x72,0x89,0x2d]
+ shilo $ac1, 3 # CHECK: shilo $ac1, 3 # encoding: [0x00,0x03,0x40,0x1d]
+ shilov $ac1, $5 # CHECK: shilov $ac1, $5 # encoding: [0x00,0x05,0x52,0x7c]
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
@@ -117,3 +122,6 @@
muleu_s.ph.qbr $1, $2, $3 # CHECK: muleu_s.ph.qbr $1, $2, $3 # encoding: [0x00,0x62,0x08,0xd5]
mulq_rs.ph $1, $2, $3 # CHECK: mulq_rs.ph $1, $2, $3 # encoding: [0x00,0x62,0x09,0x15]
prepend $1, $2, 3 # CHECK: prepend $1, $2, 3 # encoding: [0x00,0x22,0x1a,0x55]
+ wrdsp $5 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c]
+ wrdsp $5, 2 # CHECK: wrdsp $5, 2 # encoding: [0x00,0xa0,0x96,0x7c]
+ wrdsp $5, 31 # CHECK: wrdsp $5 # encoding: [0x00,0xa7,0xd6,0x7c]
diff --git a/llvm/test/MC/Mips/micromips-invalid.s b/llvm/test/MC/Mips/micromips-invalid.s
index 60c86987b09..7d34e79cf71 100644
--- a/llvm/test/MC/Mips/micromips-invalid.s
+++ b/llvm/test/MC/Mips/micromips-invalid.s
@@ -75,6 +75,11 @@
movep $8, $6, $2, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $5, $3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
movep $5, $6, $2, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
+ break 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
+ break 1024, 1024 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
+ wait 1024 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate
prefx -1, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
prefx 32, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
jraddiusp 1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected both 7-bit unsigned immediate and multiple of 4
diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s
index 35f698397ba..92d3f70c65a 100644
--- a/llvm/test/MC/Mips/micromips32r6/invalid.s
+++ b/llvm/test/MC/Mips/micromips32r6/invalid.s
@@ -22,6 +22,7 @@
break 1024, 5 # CHECK: :[[@LINE]]:9: error: expected 10-bit unsigned immediate
break 7, -1 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
break 7, 1024 # CHECK: :[[@LINE]]:12: error: expected 10-bit unsigned immediate
+ break 1023, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
cache -1, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
cache 32, 255($7) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
ext $2, $3, -1, 31 # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate
diff --git a/llvm/test/MC/Mips/mips32r6/invalid.s b/llvm/test/MC/Mips/mips32r6/invalid.s
index ace04085cb7..1656ac1da35 100644
--- a/llvm/test/MC/Mips/mips32r6/invalid.s
+++ b/llvm/test/MC/Mips/mips32r6/invalid.s
@@ -21,6 +21,7 @@ local_label:
break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
+ break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
// FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
diff --git a/llvm/test/MC/Mips/mips64r6/invalid.s b/llvm/test/MC/Mips/mips64r6/invalid.s
index 373ad94ad2a..cba20b15eea 100644
--- a/llvm/test/MC/Mips/mips64r6/invalid.s
+++ b/llvm/test/MC/Mips/mips64r6/invalid.s
@@ -19,6 +19,7 @@ local_label:
break 1024, 5 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
break 7, -1 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
break 7, 1024 # CHECK: :[[@LINE]]:18: error: expected 10-bit unsigned immediate
+ break 1024, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate
// FIXME: Following tests are temporarely disabled, until "PredicateControl not in hierarchy" problem is resolved
bltl $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
bltul $7, $8, local_label # -CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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