diff options
Diffstat (limited to 'llvm/test')
12 files changed, 52 insertions, 52 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll b/llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll index cfb8e3a38c4..37cc5411aa3 100644 --- a/llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll +++ b/llvm/test/CodeGen/AArch64/arm64-csldst-mmo.ll @@ -13,9 +13,9 @@ ; CHECK: SU(2): STRWui %WZR ; CHECK: SU(3): %X21<def>, %X20<def> = LDPXi %SP ; CHECK: Predecessors: -; CHECK-NEXT: out SU(0) -; CHECK-NEXT: out SU(0) -; CHECK-NEXT: ord SU(0) +; CHECK-NEXT: SU(0): Out +; CHECK-NEXT: SU(0): Out +; CHECK-NEXT: SU(0): Ord ; CHECK-NEXT: Successors: define void @test1() { entry: diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll b/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll index cde62fcb3f9..ad4feef7280 100644 --- a/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll +++ b/llvm/test/CodeGen/AArch64/arm64-misched-forwarding-A53.ll @@ -8,8 +8,8 @@ ; CHECK: shiftable ; CHECK: SU(2): %vreg2<def> = SUBXri %vreg1, 20, 0 ; CHECK: Successors: -; CHECK-NEXT: data SU(4): Latency=1 Reg=%vreg2 -; CHECK-NEXT: data SU(3): Latency=2 Reg=%vreg2 +; CHECK-NEXT: SU(4): Data Latency=1 Reg=%vreg2 +; CHECK-NEXT: SU(3): Data Latency=2 Reg=%vreg2 ; CHECK: ********** INTERVALS ********** define i64 @shiftable(i64 %A, i64 %B) { %tmp0 = sub i64 %B, 20 diff --git a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll index 748a4762d82..9cbf0cb3803 100644 --- a/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll +++ b/llvm/test/CodeGen/AArch64/arm64-misched-memdep-bug.ll @@ -7,11 +7,11 @@ ; CHECK: misched_bug:BB#0 entry ; CHECK: SU(2): %vreg2<def> = LDRWui %vreg0, 1; mem:LD4[%ptr1_plus1] GPR32:%vreg2 GPR64common:%vreg0 ; CHECK: Successors: -; CHECK-NEXT: data SU(5): Latency=4 Reg=%vreg2 -; CHECK-NEXT: ord SU(4): Latency=0 +; CHECK-NEXT: SU(5): Data Latency=4 Reg=%vreg2 +; CHECK-NEXT: SU(4): Ord Latency=0 ; CHECK: SU(3): STRWui %WZR, %vreg0, 0; mem:ST4[%ptr1] GPR64common:%vreg0 ; CHECK: Successors: -; CHECK: ord SU(4): Latency=0 +; CHECK: SU(4): Ord Latency=0 ; CHECK: SU(4): STRWui %WZR, %vreg1, 0; mem:ST4[%ptr2] GPR64common:%vreg1 ; CHECK: SU(5): %W0<def> = COPY %vreg2; GPR32:%vreg2 ; CHECK: ** ScheduleDAGMI::schedule picking next node diff --git a/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll b/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll index 4fbd8944f03..7e76dac214a 100644 --- a/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll +++ b/llvm/test/CodeGen/AArch64/tailcall_misched_graph.ll @@ -37,8 +37,8 @@ declare void @callee2(i8*, i8*, i8*, i8*, i8*, ; CHECK: SU({{.*}}): [[VRB]]<def> = LDRXui <fi#-2> ; CHECK-NOT: SU ; CHECK: Successors: -; CHECK: ord SU([[DEPSTOREB:.*]]): Latency=0 -; CHECK: ord SU([[DEPSTOREA:.*]]): Latency=0 +; CHECK: SU([[DEPSTOREB:.*]]): Ord Latency=0 +; CHECK: SU([[DEPSTOREA:.*]]): Ord Latency=0 ; CHECK: SU([[DEPSTOREA]]): STRXui %vreg{{.*}}, <fi#-4> ; CHECK: SU([[DEPSTOREB]]): STRXui %vreg{{.*}}, <fi#-3> diff --git a/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll b/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll index 9dcfe5007c0..ed5255bfbeb 100644 --- a/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll +++ b/llvm/test/CodeGen/ARM/2012-06-12-SchedMemLatency.ll @@ -6,23 +6,23 @@ ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}}Volatile -; CHECK-NOT: ord SU -; CHECK: ord SU(3): Latency=1 -; CHECK-NOT: ord SU +; CHECK-NOT: SU({{.*}}): Ord +; CHECK: SU(3): Ord Latency=1 +; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(3){{.*}}LDR{{.*}}Volatile -; CHECK-NOT: ord SU -; CHECK: ord SU(2): Latency=1 -; CHECK-NOT: ord SU +; CHECK-NOT: SU({{.*}}): Ord +; CHECK: SU(2): Ord Latency=1 +; CHECK-NOT: SU({{.*}}): Ord ; CHECK: Successors: ; CHECK: ** List Scheduling ; CHECK: SU(2){{.*}}STR{{.*}} -; CHECK-NOT: ord SU -; CHECK: ord SU(3): Latency=1 -; CHECK-NOT: ord SU +; CHECK-NOT: SU({{.*}}): Ord +; CHECK: SU(3): Ord Latency=1 +; CHECK-NOT: SU({{.*}}): Ord ; CHECK: SU(3){{.*}}LDR{{.*}} -; CHECK-NOT: ord SU -; CHECK: ord SU(2): Latency=1 -; CHECK-NOT: ord SU +; CHECK-NOT: SU({{.*}}): Ord +; CHECK: SU(2): Ord Latency=1 +; CHECK-NOT: SU({{.*}}): Ord ; CHECK: Successors: define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind { entry: diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll index d54848a6bcf..0ae2d5f6f2f 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll @@ -13,13 +13,13 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 4 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=1 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=3 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=3 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=4 define i32 @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize { %1 = load i32, i32* @a, align 4 diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll index 9cb076651f5..bc7a14b1028 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-ldm.ll @@ -8,9 +8,9 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 3 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=3 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=3 define i32 @foo(i32* %a) nounwind optsize { diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll index 774b0a907e3..67cddc14d04 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-stm-wrback.ll @@ -10,7 +10,7 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 2 ; CHECK: Successors -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=1 define i32 @bar(i32 %v0, i32 %v1, i32 %v2, i32* %addr) { diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vfma.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vfma.ll index e234e179ed0..372b2e2f5dc 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vfma.ll +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vfma.ll @@ -11,7 +11,7 @@ define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float ; > VMULS common latency = 5 ; CHECK: Latency : 5 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMULS read-advanced latency to VMLAS = 0 ; CHECK-SAME: Latency=0 @@ -20,7 +20,7 @@ define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float ; > VMLAS common latency = 9 ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAS read-advanced latency to the next VMLAS = 4 ; CHECK-SAME: Latency=4 @@ -28,7 +28,7 @@ define float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float ; CHECK-FAST: VFMAS ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAS not-optimized latency to VMOVRS = 9 ; CHECK-SAME: Latency=9 @@ -50,7 +50,7 @@ define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; > VMULfd common latency = 5 ; CHECK: Latency : 5 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; VMULfd read-advanced latency to VMLAfd = 0 ; CHECK-SAME: Latency=0 @@ -59,7 +59,7 @@ define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; > VMLAfd common latency = 9 ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAfd read-advanced latency to the next VMLAfd = 4 ; CHECK-SAME: Latency=4 @@ -67,7 +67,7 @@ define <2 x float> @Test2(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; CHECK-FAST: VFMAfd ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAfd not-optimized latency to VMOVRRD = 9 ; CHECK-SAME: Latency=9 @@ -88,7 +88,7 @@ define float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float ; > VMULS common latency = 5 ; CHECK: Latency : 5 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMULS read-advanced latency to VMLSS = 0 ; CHECK-SAME: Latency=0 @@ -97,7 +97,7 @@ define float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float ; > VMLSS common latency = 9 ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLSS read-advanced latency to the next VMLSS = 4 ; CHECK-SAME: Latency=4 @@ -105,7 +105,7 @@ define float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float ; CHECK-FAST: VFMSS ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLSS not-optimized latency to VMOVRS = 9 ; CHECK-SAME: Latency=9 @@ -127,7 +127,7 @@ define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; > VMULfd common latency = 5 ; CHECK: Latency : 5 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; VMULfd read-advanced latency to VMLSfd = 0 ; CHECK-SAME: Latency=0 @@ -136,7 +136,7 @@ define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; > VMLSfd common latency = 9 ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLSfd read-advanced latency to the next VMLSfd = 4 ; CHECK-SAME: Latency=4 @@ -144,7 +144,7 @@ define <2 x float> @Test4(<2 x float> %f1, <2 x float> %f2, <2 x float> %f3, <2 ; CHECK-FAST: VFMSfd ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLSfd not-optimized latency to VMOVRRD = 9 ; CHECK-SAME: Latency=9 @@ -165,7 +165,7 @@ define float @Test5(float %f1, float %f2, float %f3) { ; CHECK-FAST: VFNMS ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAS not-optimized latency to VMOVRS = 9 ; CHECK-SAME: Latency=9 @@ -184,7 +184,7 @@ define float @Test6(float %f1, float %f2, float %f3) { ; CHECK-FAST: VFNMA ; CHECK: Latency : 9 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; > VMLAS not-optimized latency to VMOVRS = 9 ; CHECK-SAME: Latency=9 diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll index 6cfa823fb96..b5edcc30422 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll @@ -13,15 +13,15 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 6 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=1 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=1 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=5 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=5 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=6 define i32 @bar(i32* %iptr) minsize optsize { %1 = load double, double* @a, align 8 diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll index 218b5b41a7e..12c7b3270c3 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vldm.ll @@ -8,11 +8,11 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 6 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=5 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=5 -; CHECK-NEXT: data +; CHECK-NEXT: Data ; CHECK-SAME: Latency=6 define double @foo(double* %a) nounwind optsize { diff --git a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll index af1c469d444..05c498eee49 100644 --- a/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll +++ b/llvm/test/CodeGen/ARM/cortex-a57-misched-vstm-wrback.ll @@ -9,7 +9,7 @@ ; CHECK: rdefs left ; CHECK-NEXT: Latency : 4 ; CHECK: Successors: -; CHECK: data +; CHECK: Data ; CHECK-SAME: Latency=1 @a = global double 0.0, align 4 |
