diff options
Diffstat (limited to 'llvm/test')
4 files changed, 168 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir index ef526c6f635..42d40f630aa 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir @@ -30,6 +30,7 @@ define void @test_and_s32() { ret void } define void @test_or_s32() { ret void } + define void @test_xor_s32() { ret void } define void @test_load_from_stack() { ret void } define void @test_load_f32() #0 { ret void } @@ -852,6 +853,39 @@ body: | ; CHECK: BX_RET 14, _, implicit %r0 ... --- +name: test_xor_s32 +# CHECK-LABEL: name: test_xor_s32 +legalized: true +regBankSelected: true +selected: false +# CHECK: selected: true +registers: + - { id: 0, class: gprb } + - { id: 1, class: gprb } + - { id: 2, class: gprb } +# CHECK: id: 0, class: gpr +# CHECK: id: 1, class: gpr +# CHECK: id: 2, class: gpr +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0 + + %1(s32) = COPY %r1 + ; CHECK: [[VREGY:%[0-9]+]] = COPY %r1 + + %2(s32) = G_XOR %0, %1 + ; CHECK: [[VREGRES:%[0-9]+]] = EORrr [[VREGX]], [[VREGY]], 14, _ + + %r0 = COPY %2(s32) + ; CHECK: %r0 = COPY [[VREGRES]] + + BX_RET 14, _, implicit %r0 + ; CHECK: BX_RET 14, _, implicit %r0 +... +--- name: test_load_from_stack # CHECK-LABEL: name: test_load_from_stack legalized: true diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll index c6d8fc9d2cc..2bef815ec51 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll @@ -207,6 +207,33 @@ entry: ret i32 %sum } +define i8 @test_xor_i8(i8 %x, i8 %y) { +; CHECK-LABEL: test_xor_i8: +; CHECK: eor r0, r0, r1 +; CHECK: bx lr +entry: + %sum = xor i8 %x, %y + ret i8 %sum +} + +define i16 @test_xor_i16(i16 %x, i16 %y) { +; CHECK-LABEL: test_xor_i16: +; CHECK: eor r0, r0, r1 +; CHECK: bx lr +entry: + %sum = xor i16 %x, %y + ret i16 %sum +} + +define i32 @test_xor_i32(i32 %x, i32 %y) { +; CHECK-LABEL: test_xor_i32: +; CHECK: eor r0, r0, r1 +; CHECK: bx lr +entry: + %sum = xor i32 %x, %y + ret i32 %sum +} + define i32 @test_stack_args_i32(i32 %p0, i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5) { ; CHECK-LABEL: test_stack_args_i32: ; CHECK: add [[P5ADDR:r[0-9]+]], sp, #4 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir index e306d9a896a..c6f6ca81c27 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir @@ -23,6 +23,10 @@ define void @test_or_s16() { ret void } define void @test_or_s32() { ret void } + define void @test_xor_s8() { ret void } + define void @test_xor_s16() { ret void } + define void @test_xor_s32() { ret void } + define void @test_load_from_stack() { ret void } define void @test_legal_loads() #0 { ret void } define void @test_legal_stores() #0 { ret void } @@ -461,6 +465,82 @@ body: | ... --- +name: test_xor_s8 +# CHECK-LABEL: name: test_xor_s8 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s8) = COPY %r0 + %1(s8) = COPY %r1 + %2(s8) = G_XOR %0, %1 + ; G_XOR with s8 should widen + ; CHECK: {{%[0-9]+}}(s32) = G_XOR {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}(s8) = G_XOR {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s8) + BX_RET 14, _, implicit %r0 +... +--- +name: test_xor_s16 +# CHECK-LABEL: name: test_xor_s16 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s16) = COPY %r0 + %1(s16) = COPY %r1 + %2(s16) = G_XOR %0, %1 + ; G_XOR with s16 should widen + ; CHECK: {{%[0-9]+}}(s32) = G_XOR {{%[0-9]+, %[0-9]+}} + ; CHECK-NOT: {{%[0-9]+}}(s16) = G_XOR {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s16) + BX_RET 14, _, implicit %r0 + +... +--- +name: test_xor_s32 +# CHECK-LABEL: name: test_xor_s32 +legalized: false +# CHECK: legalized: true +regBankSelected: false +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_XOR %0, %1 + ; G_XOR with s32 is legal, so we should find it unchanged in the output + ; CHECK: {{%[0-9]+}}(s32) = G_XOR {{%[0-9]+, %[0-9]+}} + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- name: test_load_from_stack # CHECK-LABEL: name: test_load_from_stack legalized: false diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir index 3a4b96bb6f1..9f5d863187d 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir @@ -18,6 +18,7 @@ define void @test_and_s32() { ret void} define void @test_or_s32() { ret void} + define void @test_xor_s32() { ret void} define void @test_loads() #0 { ret void } define void @test_stores() #0 { ret void } @@ -469,6 +470,32 @@ body: | ... --- +name: test_xor_s32 +# CHECK-LABEL: name: test_xor_s32 +legalized: true +regBankSelected: false +selected: false +# CHECK: registers: +# CHECK: - { id: 0, class: gprb, preferred-register: '' } +# CHECK: - { id: 1, class: gprb, preferred-register: '' } +# CHECK: - { id: 2, class: gprb, preferred-register: '' } + +registers: + - { id: 0, class: _ } + - { id: 1, class: _ } + - { id: 2, class: _ } +body: | + bb.0: + liveins: %r0, %r1 + + %0(s32) = COPY %r0 + %1(s32) = COPY %r1 + %2(s32) = G_XOR %0, %1 + %r0 = COPY %2(s32) + BX_RET 14, _, implicit %r0 + +... +--- name: test_loads # CHECK-LABEL: name: test_loads legalized: true |
