1 files changed, 48 insertions, 0 deletions
diff --git a/llvm/test/tools/llvm-mca/X86/Znver1/partial-reg-update-7.s b/llvm/test/tools/llvm-mca/X86/Znver1/partial-reg-update-7.s
new file mode 100644
index 00000000000..5be7b423241
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/X86/Znver1/partial-reg-update-7.s
@@ -0,0 +1,48 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=znver1 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
+
+# An instruction that writes to a 32-bit register will not have any false
+# dependence on the corresponding 64-bit register because the upper part of
+# the 64-bit register is set to zero
+
+imulq %rax, %rcx
+addl  %edx, %ecx
+addq  %rcx, %rdx
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      3
+# CHECK-NEXT: Total Cycles:      9
+# CHECK-NEXT: Dispatch Width:    4
+# CHECK-NEXT: IPC:               0.33
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  2      4     1.00                        imulq	%rax, %rcx
+# CHECK-NEXT:  1      1     0.25                        addl	%edx, %ecx
+# CHECK-NEXT:  1      1     0.25                        addq	%rcx, %rdx
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     012345678
+
+# CHECK:      [0,0]     DeeeeER .   imulq	%rax, %rcx
+# CHECK-NEXT: [0,1]     D====eER.   addl	%edx, %ecx
+# CHECK-NEXT: [0,2]     D=====eER   addq	%rcx, %rdx
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     1.0    1.0    0.0       imulq	%rax, %rcx
+# CHECK-NEXT: 1.     1     5.0    0.0    0.0       addl	%edx, %ecx
+# CHECK-NEXT: 2.     1     6.0    0.0    0.0       addq	%rcx, %rdx