diff options
Diffstat (limited to 'llvm/test/Transforms')
3 files changed, 19 insertions, 7 deletions
diff --git a/llvm/test/Transforms/InstCombine/sext.ll b/llvm/test/Transforms/InstCombine/sext.ll index f04afcc747b..4caa0f1fbb1 100644 --- a/llvm/test/Transforms/InstCombine/sext.ll +++ b/llvm/test/Transforms/InstCombine/sext.ll @@ -193,3 +193,15 @@ define i32 @test17(i1 %x) nounwind { ; CHECK-NEXT: [[TEST17:%.*]] = zext i1 %x to i32 ; CHECK-NEXT: ret i32 [[TEST17]] } + +define i32 @test18(i16 %x) { + %cmp = icmp slt i16 %x, 0 + %sel = select i1 %cmp, i16 0, i16 %x + %ext = sext i16 %sel to i32 + ret i32 %ext +; CHECK-LABEL: @test18( +; CHECK-NEXT: %[[cmp:.*]] = icmp slt i16 %x, 0 +; CHECK-NEXT: %[[sel:.*]] = select i1 %[[cmp]], i16 0, i16 %x +; CHECK-NEXT: %[[ext:.*]] = zext i16 %[[sel]] to i32 +; CHECK-NEXT: ret i32 %[[ext]] +} diff --git a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll index 9ee6e6d529a..99a063b8c6e 100644 --- a/llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll +++ b/llvm/test/Transforms/LoopVectorize/interleaved-accesses-pred-stores.ll @@ -13,7 +13,7 @@ target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128" ; CHECK: %n.mod.vf = and i64 %[[N:.+]], 1 ; CHECK: %[[IsZero:[a-zA-Z0-9]+]] = icmp eq i64 %n.mod.vf, 0 ; CHECK: %[[R:.+]] = select i1 %[[IsZero]], i64 2, i64 %n.mod.vf -; CHECK: %n.vec = sub i64 %[[N]], %[[R]] +; CHECK: %n.vec = sub nsw i64 %[[N]], %[[R]] ; ; CHECK: vector.body: ; CHECK: %wide.vec = load <4 x i64>, <4 x i64>* %{{.*}} @@ -62,7 +62,7 @@ for.end: ; CHECK: %n.mod.vf = and i64 %[[N:.+]], 1 ; CHECK: %[[IsZero:[a-zA-Z0-9]+]] = icmp eq i64 %n.mod.vf, 0 ; CHECK: %[[R:.+]] = select i1 %[[IsZero]], i64 2, i64 %n.mod.vf -; CHECK: %n.vec = sub i64 %[[N]], %[[R]] +; CHECK: %n.vec = sub nsw i64 %[[N]], %[[R]] ; ; CHECK: vector.body: ; CHECK: %[[L1:.+]] = load <4 x i64>, <4 x i64>* %{{.*}} @@ -121,7 +121,7 @@ for.end: ; CHECK: %n.mod.vf = and i64 %[[N:.+]], 1 ; CHECK: %[[IsZero:[a-zA-Z0-9]+]] = icmp eq i64 %n.mod.vf, 0 ; CHECK: %[[R:.+]] = select i1 %[[IsZero]], i64 2, i64 %n.mod.vf -; CHECK: %n.vec = sub i64 %[[N]], %[[R]] +; CHECK: %n.vec = sub nsw i64 %[[N]], %[[R]] ; ; CHECK: vector.body: ; CHECK: %[[L1:.+]] = load <4 x i64>, <4 x i64>* %{{.*}} diff --git a/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll b/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll index 868c3a2cdab..34998782aa8 100644 --- a/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll +++ b/llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll @@ -577,7 +577,7 @@ for.body: ; preds = %for.body, %entry ; CHECK: %n.mod.vf = and i64 %[[N:.+]], 3 ; CHECK: %[[IsZero:[a-zA-Z0-9]+]] = icmp eq i64 %n.mod.vf, 0 ; CHECK: %[[R:[a-zA-Z0-9]+]] = select i1 %[[IsZero]], i64 4, i64 %n.mod.vf -; CHECK: %n.vec = sub i64 %[[N]], %[[R]] +; CHECK: %n.vec = sub nsw i64 %[[N]], %[[R]] ; CHECK: vector.body: ; CHECK: %[[L1:.+]] = load <8 x i32>, <8 x i32>* {{.*}} ; CHECK: %[[X1:.+]] = extractelement <8 x i32> %[[L1]], i32 0 @@ -625,7 +625,7 @@ for.end: ; CHECK: %n.mod.vf = and i64 %[[N:.+]], 3 ; CHECK: %[[IsZero:[a-zA-Z0-9]+]] = icmp eq i64 %n.mod.vf, 0 ; CHECK: %[[R:[a-zA-Z0-9]+]] = select i1 %[[IsZero]], i64 4, i64 %n.mod.vf -; CHECK: %n.vec = sub i64 %[[N]], %[[R]] +; CHECK: %n.vec = sub nsw i64 %[[N]], %[[R]] ; CHECK: vector.body: ; CHECK: %[[Phi:.+]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ {{.*}}, %vector.body ] ; CHECK: %[[L1:.+]] = load <8 x i32>, <8 x i32>* {{.*}} @@ -678,7 +678,7 @@ for.end: ; CHECK: %n.mod.vf = and i64 %[[N:.+]], 3 ; CHECK: %[[IsZero:[a-zA-Z0-9]+]] = icmp eq i64 %n.mod.vf, 0 ; CHECK: %[[R:[a-zA-Z0-9]+]] = select i1 %[[IsZero]], i64 4, i64 %n.mod.vf -; CHECK: %n.vec = sub i64 %[[N]], %[[R]] +; CHECK: %n.vec = sub nsw i64 %[[N]], %[[R]] ; CHECK: vector.body: ; CHECK: %[[L1:.+]] = load <8 x i32>, <8 x i32>* {{.*}} ; CHECK: %[[X1:.+]] = extractelement <8 x i32> %[[L1]], i32 0 @@ -726,7 +726,7 @@ for.end: ; CHECK: %n.mod.vf = and i64 %[[N:.+]], 3 ; CHECK: %[[IsZero:[a-zA-Z0-9]+]] = icmp eq i64 %n.mod.vf, 0 ; CHECK: %[[R:[a-zA-Z0-9]+]] = select i1 %[[IsZero]], i64 4, i64 %n.mod.vf -; CHECK: %n.vec = sub i64 %[[N]], %[[R]] +; CHECK: %n.vec = sub nsw i64 %[[N]], %[[R]] ; CHECK: vector.body: ; CHECK: %[[Phi:.+]] = phi <4 x i32> [ zeroinitializer, %vector.ph ], [ {{.*}}, %vector.body ] ; CHECK: %[[L1:.+]] = load <8 x i32>, <8 x i32>* {{.*}} |
