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-rw-r--r--llvm/test/Transforms/InstCombine/and2.ll12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/and2.ll b/llvm/test/Transforms/InstCombine/and2.ll
index 504391aa485..e88fd598300 100644
--- a/llvm/test/Transforms/InstCombine/and2.ll
+++ b/llvm/test/Transforms/InstCombine/and2.ll
@@ -42,3 +42,15 @@ define <4 x i32> @test5(<4 x i32> %A) {
%2 = and <4 x i32> <i32 1, i32 2, i32 3, i32 4>, %1
ret <4 x i32> %2
}
+
+; Check that we combine "if x!=0 && x!=-1" into "if x+1u>1"
+define i32 @test6(i64 %x) nounwind {
+; CHECK: @test6
+; CHECK-NEXT: add i64 %x, 1
+; CHECK-NEXT: icmp ugt i64 %x.off, 1
+ %cmp1 = icmp ne i64 %x, -1
+ %not.cmp = icmp ne i64 %x, 0
+ %.cmp1 = and i1 %cmp1, %not.cmp
+ %land.ext = zext i1 %.cmp1 to i32
+ ret i32 %land.ext
+}
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