diff options
Diffstat (limited to 'llvm/test/Transforms/LoopStrengthReduce/ARM')
5 files changed, 0 insertions, 613 deletions
diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll deleted file mode 100644 index 7768c62fceb..00000000000 --- a/llvm/test/Transforms/LoopStrengthReduce/ARM/2012-06-15-lsr-noaddrmode.ll +++ /dev/null @@ -1,97 +0,0 @@ -; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a8 %s -o - -arm-atomic-cfg-tidy=0 | FileCheck %s -; -; LSR should only check for valid address modes when the IV user is a -; memory address. -; svn r158536, rdar://11635990 -; -; Note that we still don't produce the best code here because we fail -; to coalesce the IV. See <rdar://problem/11680670> [coalescer] IVs -; need to be scheduled to expose coalescing. - -; LSR before the fix: -;The chosen solution requires 4 regs, with addrec cost 1, plus 3 base adds, plus 2 setup cost: -; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32 -; reg(%v3) + reg({0,+,-1}<%while.cond.i.i>) + imm(1) -; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i32 -; reg(%v3) + reg({0,+,-1}<%while.cond.i.i>) -; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32* -; reg((-4 + (4 * %v3) + %v1)) + 4*reg({0,+,-1}<%while.cond.i.i>) -; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32* -; reg((-4 + (4 * %v3) + %v4)) + 4*reg({0,+,-1}<%while.cond.i.i>) -; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32 -; reg(%v3) -; -; LSR after the fix: -;The chosen solution requires 4 regs, with addrec cost 1, plus 1 base add, plus 2 setup cost: -; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32 -; reg({%v3,+,-1}<nsw><%while.cond.i.i>) + imm(1) -; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i32 -; reg({%v3,+,-1}<nsw><%while.cond.i.i>) -; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32* -; reg((-4 + %v1)) + 4*reg({%v3,+,-1}<nsw><%while.cond.i.i>) -; LSR Use: Kind=Address of i32, Offsets={0}, widest fixup type: i32* -; reg((-4 + %v4)) + 4*reg({%v3,+,-1}<nsw><%while.cond.i.i>) -; LSR Use: Kind=Special, Offsets={0}, all-fixups-outside-loop, widest fixup type: i32 -; reg(%v3) - - -%s = type { i32* } - -@ncol = external global i32, align 4 - -declare i32* @getptr() nounwind -declare %s* @getstruct() nounwind - -; CHECK: @main -; Check that the loop preheader contains no address computation. -; CHECK: %while.cond.i.i -; CHECK-NOT: add{{.*}}lsl -; CHECK: ldr{{.*}}lsl #2 -; CHECK: ldr{{.*}}lsl #2 -define i32 @main() nounwind ssp { -entry: - %v0 = load i32, i32* @ncol, align 4 - %v1 = tail call i32* @getptr() nounwind - %cmp10.i = icmp eq i32 %v0, 0 - br label %while.cond.outer - -while.cond.outer: - %call18 = tail call %s* @getstruct() nounwind - br label %while.cond - -while.cond: - %cmp20 = icmp eq i32* %v1, null - br label %while.body - -while.body: - %v3 = load i32, i32* @ncol, align 4 - br label %end_of_chain - -end_of_chain: - %state.i = getelementptr inbounds %s, %s* %call18, i32 0, i32 0 - %v4 = load i32*, i32** %state.i, align 4 - br label %while.cond.i.i - -while.cond.i.i: - %counter.0.i.i = phi i32 [ %v3, %end_of_chain ], [ %dec.i.i, %land.rhs.i.i ] - %dec.i.i = add nsw i32 %counter.0.i.i, -1 - %tobool.i.i = icmp eq i32 %counter.0.i.i, 0 - br i1 %tobool.i.i, label %where.exit, label %land.rhs.i.i - -land.rhs.i.i: - %arrayidx.i.i = getelementptr inbounds i32, i32* %v4, i32 %dec.i.i - %v5 = load i32, i32* %arrayidx.i.i, align 4 - %arrayidx1.i.i = getelementptr inbounds i32, i32* %v1, i32 %dec.i.i - %v6 = load i32, i32* %arrayidx1.i.i, align 4 - %cmp.i.i = icmp eq i32 %v5, %v6 - br i1 %cmp.i.i, label %while.cond.i.i, label %equal_data.exit.i - -equal_data.exit.i: - ret i32 %counter.0.i.i - -where.exit: - br label %while.end.i - -while.end.i: - ret i32 %v3 -} diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/addrec-is-loop-invariant.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/addrec-is-loop-invariant.ll deleted file mode 100644 index 261c3cceed6..00000000000 --- a/llvm/test/Transforms/LoopStrengthReduce/ARM/addrec-is-loop-invariant.ll +++ /dev/null @@ -1,35 +0,0 @@ -; RUN: llc -mtriple=armv8-eabi -verify-machineinstrs %s -o /dev/null - -; This test ensures that Loop Strength Reduction will -; not create an Add Reccurence Expression if not all -; its operands are loop invariants. - -define void @add_rec_expr() { -entry: - br label %loop0 - -loop0: - %c.0 = phi i32 [ 0, %entry ], [ %inc.0, %loop0 ] - %inc.0 = add nuw i32 %c.0, 1 - br i1 undef, label %loop0, label %bb1 - -bb1: - %mul.0 = mul i32 %c.0, %c.0 - %gelptr.0 = getelementptr inbounds i16, i16* undef, i32 %mul.0 - br label %loop1 - -loop1: - %inc.1 = phi i32 [ %inc.2, %bb4 ], [ 0, %bb1 ] - %mul.1 = mul i32 %inc.1, %c.0 - br label %bb3 - -bb3: - %add.0 = add i32 undef, %mul.1 - %gelptr.1 = getelementptr inbounds i16, i16* %gelptr.0, i32 %add.0 - store i16 undef, i16* %gelptr.1, align 2 - br label %bb4 - -bb4: - %inc.2 = add nuw i32 %inc.1, 1 - br label %loop1 -} diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/complexity.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/complexity.ll deleted file mode 100644 index 197bb53ab51..00000000000 --- a/llvm/test/Transforms/LoopStrengthReduce/ARM/complexity.ll +++ /dev/null @@ -1,112 +0,0 @@ -target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" - -; RUN: opt -mtriple=thumbv7em %s -S -loop-reduce -lsr-complexity-limit=65536 -o - | FileCheck %s -; RUN: opt -mtriple=thumbv7em %s -S -loop-reduce -lsr-complexity-limit=2147483647 -o - | FileCheck %s - -; CHECK-LABEL: for.body12.us.us: -; CHECK: [[LSR_IV6:%[^ ]+]] = phi i16* [ [[SCEVGEP7:%[^ ]+]], %for.body12.us.us ], [ [[SCEVGEP5:%[^ ]+]], %for.cond9.preheader.us.us ] -; CHECK: phi i32 -; CHECK: [[LSR_IV:%[^ ]+]] = phi i16* [ [[SCEVGEP1:%[^ ]+]], %for.body12.us.us ], [ [[SCEVGEP:%[^ ]+]], %for.cond9.preheader.us.us ] -; CHECK: phi i32 -; CHECK: [[SCEVGEP1]] = getelementptr i16, i16* [[LSR_IV]], i32 4 -; CHECK: [[SCEVGEP7]] = getelementptr i16, i16* [[LSR_IV6]], i32 4 - -define void @convolve(i16** nocapture readonly %input_image, i16** nocapture readonly %filter, i32 %filter_dim, i32 %out_width, i32 %out_height, i32** nocapture readonly %convolved) { -entry: - %cmp92 = icmp eq i32 %out_height, 0 - br i1 %cmp92, label %for.cond.cleanup, label %for.cond1.preheader.lr.ph - -for.cond1.preheader.lr.ph: ; preds = %entry - %xtraiter = and i32 %filter_dim, 3 - %unroll_iter = sub i32 %filter_dim, %xtraiter - br label %for.cond1.preheader - -for.cond1.preheader: ; preds = %for.cond.cleanup3, %for.cond1.preheader.lr.ph - %res_y.093 = phi i32 [ 0, %for.cond1.preheader.lr.ph ], [ %add28, %for.cond.cleanup3 ] - %arrayidx22 = getelementptr inbounds i32*, i32** %convolved, i32 %res_y.093 - %tmp3 = load i32*, i32** %arrayidx22, align 4 - br label %for.cond9.preheader.us.us.preheader - -for.cond9.preheader.us.us.preheader: ; preds = %for.cond5.for.cond.cleanup7_crit_edge.us, %for.cond5.preheader.lr.ph - %res_x.060.us = phi i32 [ %add25.us, %for.cond5.for.cond.cleanup7_crit_edge.us ], [ 0, %for.cond1.preheader ] - br label %for.cond9.preheader.us.us - -for.cond9.preheader.us.us: ; preds = %for.cond9.for.cond.cleanup11_crit_edge.us.us, %for.cond9.preheader.us.us.preheader - %filter_y.056.us.us = phi i32 [ %inc20.us.us, %for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa ], [ 0, %for.cond9.preheader.us.us.preheader ] - %result_element.055.us.us = phi i32 [ %add18.us.us.3, %for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa ], [ 0, %for.cond9.preheader.us.us.preheader ] - %add.us.us = add i32 %filter_y.056.us.us, %res_y.093 - %arrayidx.us.us = getelementptr inbounds i16*, i16** %filter, i32 %filter_y.056.us.us - %tmp5 = load i16*, i16** %arrayidx.us.us, align 4 - %arrayidx15.us.us = getelementptr inbounds i16*, i16** %input_image, i32 %add.us.us - %tmp6 = load i16*, i16** %arrayidx15.us.us, align 4 - br label %for.body12.us.us - -for.body12.us.us: ; preds = %for.body12.us.us, %for.cond9.preheader.us.us - %filter_x.053.us.us = phi i32 [ %inc.us.us.3, %for.body12.us.us ], [ 0, %for.cond9.preheader.us.us ] - %result_element.152.us.us = phi i32 [ %add18.us.us.3, %for.body12.us.us ], [ %result_element.055.us.us, %for.cond9.preheader.us.us ] - %niter = phi i32 [ %niter.nsub.3, %for.body12.us.us ], [ %unroll_iter, %for.cond9.preheader.us.us ] - %add13.us.us = add i32 %filter_x.053.us.us, %res_x.060.us - %arrayidx14.us.us = getelementptr inbounds i16, i16* %tmp5, i32 %filter_x.053.us.us - %tmp9 = load i16, i16* %arrayidx14.us.us, align 2 - %conv.us.us = sext i16 %tmp9 to i32 - %arrayidx16.us.us = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us - %tmp10 = load i16, i16* %arrayidx16.us.us, align 2 - %conv17.us.us = sext i16 %tmp10 to i32 - %mul.us.us = mul nsw i32 %conv17.us.us, %conv.us.us - %add18.us.us = add nsw i32 %mul.us.us, %result_element.152.us.us - %inc.us.us = or i32 %filter_x.053.us.us, 1 - %add13.us.us.1 = add i32 %inc.us.us, %res_x.060.us - %arrayidx14.us.us.1 = getelementptr inbounds i16, i16* %tmp5, i32 %inc.us.us - %tmp11 = load i16, i16* %arrayidx14.us.us.1, align 2 - %conv.us.us.1 = sext i16 %tmp11 to i32 - %arrayidx16.us.us.1 = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us.1 - %tmp12 = load i16, i16* %arrayidx16.us.us.1, align 2 - %conv17.us.us.1 = sext i16 %tmp12 to i32 - %mul.us.us.1 = mul nsw i32 %conv17.us.us.1, %conv.us.us.1 - %add18.us.us.1 = add nsw i32 %mul.us.us.1, %add18.us.us - %inc.us.us.1 = or i32 %filter_x.053.us.us, 2 - %add13.us.us.2 = add i32 %inc.us.us.1, %res_x.060.us - %arrayidx14.us.us.2 = getelementptr inbounds i16, i16* %tmp5, i32 %inc.us.us.1 - %tmp13 = load i16, i16* %arrayidx14.us.us.2, align 2 - %conv.us.us.2 = sext i16 %tmp13 to i32 - %arrayidx16.us.us.2 = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us.2 - %tmp14 = load i16, i16* %arrayidx16.us.us.2, align 2 - %conv17.us.us.2 = sext i16 %tmp14 to i32 - %mul.us.us.2 = mul nsw i32 %conv17.us.us.2, %conv.us.us.2 - %add18.us.us.2 = add nsw i32 %mul.us.us.2, %add18.us.us.1 - %inc.us.us.2 = or i32 %filter_x.053.us.us, 3 - %add13.us.us.3 = add i32 %inc.us.us.2, %res_x.060.us - %arrayidx14.us.us.3 = getelementptr inbounds i16, i16* %tmp5, i32 %inc.us.us.2 - %tmp15 = load i16, i16* %arrayidx14.us.us.3, align 2 - %conv.us.us.3 = sext i16 %tmp15 to i32 - %arrayidx16.us.us.3 = getelementptr inbounds i16, i16* %tmp6, i32 %add13.us.us.3 - %tmp16 = load i16, i16* %arrayidx16.us.us.3, align 2 - %conv17.us.us.3 = sext i16 %tmp16 to i32 - %mul.us.us.3 = mul nsw i32 %conv17.us.us.3, %conv.us.us.3 - %add18.us.us.3 = add nsw i32 %mul.us.us.3, %add18.us.us.2 - %inc.us.us.3 = add i32 %filter_x.053.us.us, 4 - %niter.nsub.3 = add i32 %niter, -4 - %niter.ncmp.3 = icmp eq i32 %niter.nsub.3, 0 - br i1 %niter.ncmp.3, label %for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa, label %for.body12.us.us - -for.cond9.for.cond.cleanup11_crit_edge.us.us.unr-lcssa: ; preds = %for.body12.us.us, %for.cond9.preheader.us.us - %inc20.us.us = add nuw i32 %filter_y.056.us.us, 1 - %exitcond98 = icmp eq i32 %inc20.us.us, %filter_dim - br i1 %exitcond98, label %for.cond5.for.cond.cleanup7_crit_edge.us, label %for.cond9.preheader.us.us - -for.cond5.for.cond.cleanup7_crit_edge.us: ; preds = %for.cond9.for.cond.cleanup11_crit_edge.us.us - %arrayidx23.us = getelementptr inbounds i32, i32* %tmp3, i32 %res_x.060.us - store i32 %add18.us.us.3, i32* %arrayidx23.us, align 4 - %add25.us = add nuw i32 %res_x.060.us, 1 - %exitcond99 = icmp eq i32 %add25.us, %out_width - br i1 %exitcond99, label %for.cond.cleanup3, label %for.cond9.preheader.us.us.preheader - -for.cond.cleanup3: ; preds = %for.cond5.for.cond.cleanup7_crit_edge.us, %for.cond5.preheader.preheader, %for.cond1.preheader - %add28 = add nuw i32 %res_y.093, 1 - %exitcond100 = icmp eq i32 %add28, %out_height - br i1 %exitcond100, label %for.cond.cleanup, label %for.cond1.preheader - -for.cond.cleanup: ; preds = %for.cond.cleanup3, %entry - ret void -} - diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll b/llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll deleted file mode 100644 index dcb27d58efe..00000000000 --- a/llvm/test/Transforms/LoopStrengthReduce/ARM/ivchain-ARM.ll +++ /dev/null @@ -1,366 +0,0 @@ -; RUN: llc -O3 -mtriple=thumb-eabi -mcpu=cortex-a9 %s -o - | FileCheck %s -check-prefix=A9 - -; @simple is the most basic chain of address induction variables. Chaining -; saves at least one register and avoids complex addressing and setup -; code. -; -; A9: @simple -; no expensive address computation in the preheader -; A9: lsl -; A9-NOT: lsl -; A9: %loop -; no complex address modes -; A9-NOT: lsl -define i32 @simple(i32* %a, i32* %b, i32 %x) nounwind { -entry: - br label %loop -loop: - %iv = phi i32* [ %a, %entry ], [ %iv4, %loop ] - %s = phi i32 [ 0, %entry ], [ %s4, %loop ] - %v = load i32, i32* %iv - %iv1 = getelementptr inbounds i32, i32* %iv, i32 %x - %v1 = load i32, i32* %iv1 - %iv2 = getelementptr inbounds i32, i32* %iv1, i32 %x - %v2 = load i32, i32* %iv2 - %iv3 = getelementptr inbounds i32, i32* %iv2, i32 %x - %v3 = load i32, i32* %iv3 - %s1 = add i32 %s, %v - %s2 = add i32 %s1, %v1 - %s3 = add i32 %s2, %v2 - %s4 = add i32 %s3, %v3 - %iv4 = getelementptr inbounds i32, i32* %iv3, i32 %x - %cmp = icmp eq i32* %iv4, %b - br i1 %cmp, label %exit, label %loop -exit: - ret i32 %s4 -} - -; @user is not currently chained because the IV is live across memory ops. -; -; A9: @user -; stride multiples computed in the preheader -; A9: lsl -; A9: lsl -; A9: %loop -; complex address modes -; A9: lsl -; A9: lsl -define i32 @user(i32* %a, i32* %b, i32 %x) nounwind { -entry: - br label %loop -loop: - %iv = phi i32* [ %a, %entry ], [ %iv4, %loop ] - %s = phi i32 [ 0, %entry ], [ %s4, %loop ] - %v = load i32, i32* %iv - %iv1 = getelementptr inbounds i32, i32* %iv, i32 %x - %v1 = load i32, i32* %iv1 - %iv2 = getelementptr inbounds i32, i32* %iv1, i32 %x - %v2 = load i32, i32* %iv2 - %iv3 = getelementptr inbounds i32, i32* %iv2, i32 %x - %v3 = load i32, i32* %iv3 - %s1 = add i32 %s, %v - %s2 = add i32 %s1, %v1 - %s3 = add i32 %s2, %v2 - %s4 = add i32 %s3, %v3 - %iv4 = getelementptr inbounds i32, i32* %iv3, i32 %x - store i32 %s4, i32* %iv - %cmp = icmp eq i32* %iv4, %b - br i1 %cmp, label %exit, label %loop -exit: - ret i32 %s4 -} - -; @extrastride is a slightly more interesting case of a single -; complete chain with multiple strides. The test case IR is what LSR -; used to do, and exactly what we don't want to do. LSR's new IV -; chaining feature should now undo the damage. -; -; A9: extrastride: -; no spills -; A9-NOT: str -; only one stride multiple in the preheader -; A9: lsl -; A9-NOT: {{str r|lsl}} -; A9: %for.body{{$}} -; no complex address modes or reloads -; A9-NOT: {{ldr .*[sp]|lsl}} -define void @extrastride(i8* nocapture %main, i32 %main_stride, i32* nocapture %res, i32 %x, i32 %y, i32 %z) nounwind { -entry: - %cmp8 = icmp eq i32 %z, 0 - br i1 %cmp8, label %for.end, label %for.body.lr.ph - -for.body.lr.ph: ; preds = %entry - %add.ptr.sum = shl i32 %main_stride, 1 ; s*2 - %add.ptr1.sum = add i32 %add.ptr.sum, %main_stride ; s*3 - %add.ptr2.sum = add i32 %x, %main_stride ; s + x - %add.ptr4.sum = shl i32 %main_stride, 2 ; s*4 - %add.ptr3.sum = add i32 %add.ptr2.sum, %add.ptr4.sum ; total IV stride = s*5+x - br label %for.body - -for.body: ; preds = %for.body.lr.ph, %for.body - %main.addr.011 = phi i8* [ %main, %for.body.lr.ph ], [ %add.ptr6, %for.body ] - %i.010 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] - %res.addr.09 = phi i32* [ %res, %for.body.lr.ph ], [ %add.ptr7, %for.body ] - %0 = bitcast i8* %main.addr.011 to i32* - %1 = load i32, i32* %0, align 4 - %add.ptr = getelementptr inbounds i8, i8* %main.addr.011, i32 %main_stride - %2 = bitcast i8* %add.ptr to i32* - %3 = load i32, i32* %2, align 4 - %add.ptr1 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr.sum - %4 = bitcast i8* %add.ptr1 to i32* - %5 = load i32, i32* %4, align 4 - %add.ptr2 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr1.sum - %6 = bitcast i8* %add.ptr2 to i32* - %7 = load i32, i32* %6, align 4 - %add.ptr3 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr4.sum - %8 = bitcast i8* %add.ptr3 to i32* - %9 = load i32, i32* %8, align 4 - %add = add i32 %3, %1 - %add4 = add i32 %add, %5 - %add5 = add i32 %add4, %7 - %add6 = add i32 %add5, %9 - store i32 %add6, i32* %res.addr.09, align 4 - %add.ptr6 = getelementptr inbounds i8, i8* %main.addr.011, i32 %add.ptr3.sum - %add.ptr7 = getelementptr inbounds i32, i32* %res.addr.09, i32 %y - %inc = add i32 %i.010, 1 - %cmp = icmp eq i32 %inc, %z - br i1 %cmp, label %for.end, label %for.body - -for.end: ; preds = %for.body, %entry - ret void -} - -; @foldedidx is an unrolled variant of this loop: -; for (unsigned long i = 0; i < len; i += s) { -; c[i] = a[i] + b[i]; -; } -; where 's' can be folded into the addressing mode. -; Consequently, we should *not* form any chains. -; -; A9: foldedidx: -; A9: ldrb{{(.w)?}} {{r[0-9]|lr}}, [{{r[0-9]|lr}}, #3] -define void @foldedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c) nounwind ssp { -entry: - br label %for.body - -for.body: ; preds = %for.body, %entry - %i.07 = phi i32 [ 0, %entry ], [ %inc.3, %for.body ] - %arrayidx = getelementptr inbounds i8, i8* %a, i32 %i.07 - %0 = load i8, i8* %arrayidx, align 1 - %conv5 = zext i8 %0 to i32 - %arrayidx1 = getelementptr inbounds i8, i8* %b, i32 %i.07 - %1 = load i8, i8* %arrayidx1, align 1 - %conv26 = zext i8 %1 to i32 - %add = add nsw i32 %conv26, %conv5 - %conv3 = trunc i32 %add to i8 - %arrayidx4 = getelementptr inbounds i8, i8* %c, i32 %i.07 - store i8 %conv3, i8* %arrayidx4, align 1 - %inc1 = or i32 %i.07, 1 - %arrayidx.1 = getelementptr inbounds i8, i8* %a, i32 %inc1 - %2 = load i8, i8* %arrayidx.1, align 1 - %conv5.1 = zext i8 %2 to i32 - %arrayidx1.1 = getelementptr inbounds i8, i8* %b, i32 %inc1 - %3 = load i8, i8* %arrayidx1.1, align 1 - %conv26.1 = zext i8 %3 to i32 - %add.1 = add nsw i32 %conv26.1, %conv5.1 - %conv3.1 = trunc i32 %add.1 to i8 - %arrayidx4.1 = getelementptr inbounds i8, i8* %c, i32 %inc1 - store i8 %conv3.1, i8* %arrayidx4.1, align 1 - %inc.12 = or i32 %i.07, 2 - %arrayidx.2 = getelementptr inbounds i8, i8* %a, i32 %inc.12 - %4 = load i8, i8* %arrayidx.2, align 1 - %conv5.2 = zext i8 %4 to i32 - %arrayidx1.2 = getelementptr inbounds i8, i8* %b, i32 %inc.12 - %5 = load i8, i8* %arrayidx1.2, align 1 - %conv26.2 = zext i8 %5 to i32 - %add.2 = add nsw i32 %conv26.2, %conv5.2 - %conv3.2 = trunc i32 %add.2 to i8 - %arrayidx4.2 = getelementptr inbounds i8, i8* %c, i32 %inc.12 - store i8 %conv3.2, i8* %arrayidx4.2, align 1 - %inc.23 = or i32 %i.07, 3 - %arrayidx.3 = getelementptr inbounds i8, i8* %a, i32 %inc.23 - %6 = load i8, i8* %arrayidx.3, align 1 - %conv5.3 = zext i8 %6 to i32 - %arrayidx1.3 = getelementptr inbounds i8, i8* %b, i32 %inc.23 - %7 = load i8, i8* %arrayidx1.3, align 1 - %conv26.3 = zext i8 %7 to i32 - %add.3 = add nsw i32 %conv26.3, %conv5.3 - %conv3.3 = trunc i32 %add.3 to i8 - %arrayidx4.3 = getelementptr inbounds i8, i8* %c, i32 %inc.23 - store i8 %conv3.3, i8* %arrayidx4.3, align 1 - %inc.3 = add nsw i32 %i.07, 4 - %exitcond.3 = icmp eq i32 %inc.3, 400 - br i1 %exitcond.3, label %for.end, label %for.body - -for.end: ; preds = %for.body - ret void -} - -; @testNeon is an important example of the nead for ivchains. -; -; Currently we have two extra add.w's that keep the store address -; live past the next increment because ISEL is unfortunately undoing -; the store chain. ISEL also fails to convert all but one of the stores to -; post-increment addressing. However, the loads should use -; post-increment addressing, no add's or add.w's beyond the three -; mentioned. Most importantly, there should be no spills or reloads! -; -; A9: testNeon: -; A9: %.lr.ph -; A9: add.w r -; A9-NOT: lsl.w -; A9-NOT: {{ldr|str|adds|add r}} -; A9: vst1.8 {{.*}} [r{{[0-9]+}}], r{{[0-9]+}} -; A9: add.w r -; A9-NOT: {{ldr|str|adds|add r}} -; A9-NOT: add.w r -; A9: bne -define hidden void @testNeon(i8* %ref_data, i32 %ref_stride, i32 %limit, <16 x i8>* nocapture %data) nounwind optsize { - %1 = icmp sgt i32 %limit, 0 - br i1 %1, label %.lr.ph, label %45 - -.lr.ph: ; preds = %0 - %2 = shl nsw i32 %ref_stride, 1 - %3 = mul nsw i32 %ref_stride, 3 - %4 = shl nsw i32 %ref_stride, 2 - %5 = mul nsw i32 %ref_stride, 5 - %6 = mul nsw i32 %ref_stride, 6 - %7 = mul nsw i32 %ref_stride, 7 - %8 = shl nsw i32 %ref_stride, 3 - %9 = sub i32 0, %8 - %10 = mul i32 %limit, -64 - br label %11 - -; <label>:11 ; preds = %11, %.lr.ph - %.05 = phi i8* [ %ref_data, %.lr.ph ], [ %42, %11 ] - %counter.04 = phi i32 [ 0, %.lr.ph ], [ %44, %11 ] - %result.03 = phi <16 x i8> [ zeroinitializer, %.lr.ph ], [ %41, %11 ] - %.012 = phi <16 x i8>* [ %data, %.lr.ph ], [ %43, %11 ] - %12 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %.05, i32 1) nounwind - %13 = getelementptr inbounds i8, i8* %.05, i32 %ref_stride - %14 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %13, i32 1) nounwind - %15 = shufflevector <1 x i64> %12, <1 x i64> %14, <2 x i32> <i32 0, i32 1> - %16 = bitcast <2 x i64> %15 to <16 x i8> - %17 = getelementptr inbounds <16 x i8>, <16 x i8>* %.012, i32 1 - store <16 x i8> %16, <16 x i8>* %.012, align 4 - %18 = getelementptr inbounds i8, i8* %.05, i32 %2 - %19 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %18, i32 1) nounwind - %20 = getelementptr inbounds i8, i8* %.05, i32 %3 - %21 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %20, i32 1) nounwind - %22 = shufflevector <1 x i64> %19, <1 x i64> %21, <2 x i32> <i32 0, i32 1> - %23 = bitcast <2 x i64> %22 to <16 x i8> - %24 = getelementptr inbounds <16 x i8>, <16 x i8>* %.012, i32 2 - store <16 x i8> %23, <16 x i8>* %17, align 4 - %25 = getelementptr inbounds i8, i8* %.05, i32 %4 - %26 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %25, i32 1) nounwind - %27 = getelementptr inbounds i8, i8* %.05, i32 %5 - %28 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %27, i32 1) nounwind - %29 = shufflevector <1 x i64> %26, <1 x i64> %28, <2 x i32> <i32 0, i32 1> - %30 = bitcast <2 x i64> %29 to <16 x i8> - %31 = getelementptr inbounds <16 x i8>, <16 x i8>* %.012, i32 3 - store <16 x i8> %30, <16 x i8>* %24, align 4 - %32 = getelementptr inbounds i8, i8* %.05, i32 %6 - %33 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %32, i32 1) nounwind - %34 = getelementptr inbounds i8, i8* %.05, i32 %7 - %35 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %34, i32 1) nounwind - %36 = shufflevector <1 x i64> %33, <1 x i64> %35, <2 x i32> <i32 0, i32 1> - %37 = bitcast <2 x i64> %36 to <16 x i8> - store <16 x i8> %37, <16 x i8>* %31, align 4 - %38 = add <16 x i8> %16, %23 - %39 = add <16 x i8> %38, %30 - %40 = add <16 x i8> %39, %37 - %41 = add <16 x i8> %result.03, %40 - %42 = getelementptr i8, i8* %.05, i32 %9 - %43 = getelementptr inbounds <16 x i8>, <16 x i8>* %.012, i32 -64 - %44 = add nsw i32 %counter.04, 1 - %exitcond = icmp eq i32 %44, %limit - br i1 %exitcond, label %._crit_edge, label %11 - -._crit_edge: ; preds = %11 - %scevgep = getelementptr <16 x i8>, <16 x i8>* %data, i32 %10 - br label %45 - -; <label>:45 ; preds = %._crit_edge, %0 - %result.0.lcssa = phi <16 x i8> [ %41, %._crit_edge ], [ zeroinitializer, %0 ] - %.01.lcssa = phi <16 x i8>* [ %scevgep, %._crit_edge ], [ %data, %0 ] - store <16 x i8> %result.0.lcssa, <16 x i8>* %.01.lcssa, align 4 - ret void -} - -declare <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8*, i32) nounwind readonly - -; Handle chains in which the same offset is used for both loads and -; stores to the same array. -; rdar://11410078. -; -; A9: @testReuse -; A9: %for.body -; A9: vld1.8 {d{{[0-9]+}}}, [[BASE:[r[0-9]+]]], [[INC:r[0-9]]] -; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vld1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]], [[INC]] -; A9: vst1.8 {d{{[0-9]+}}}, [[BASE]] -; A9: bne -define void @testReuse(i8* %src, i32 %stride) nounwind ssp { -entry: - %mul = shl nsw i32 %stride, 2 - %idx.neg = sub i32 0, %mul - %mul1 = mul nsw i32 %stride, 3 - %idx.neg2 = sub i32 0, %mul1 - %mul5 = shl nsw i32 %stride, 1 - %idx.neg6 = sub i32 0, %mul5 - %idx.neg10 = sub i32 0, %stride - br label %for.body - -for.body: ; preds = %for.body, %entry - %i.0110 = phi i32 [ 0, %entry ], [ %inc, %for.body ] - %src.addr = phi i8* [ %src, %entry ], [ %add.ptr45, %for.body ] - %add.ptr = getelementptr inbounds i8, i8* %src.addr, i32 %idx.neg - %vld1 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %add.ptr, i32 1) - %add.ptr3 = getelementptr inbounds i8, i8* %src.addr, i32 %idx.neg2 - %vld2 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %add.ptr3, i32 1) - %add.ptr7 = getelementptr inbounds i8, i8* %src.addr, i32 %idx.neg6 - %vld3 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %add.ptr7, i32 1) - %add.ptr11 = getelementptr inbounds i8, i8* %src.addr, i32 %idx.neg10 - %vld4 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %add.ptr11, i32 1) - %vld5 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %src.addr, i32 1) - %add.ptr17 = getelementptr inbounds i8, i8* %src.addr, i32 %stride - %vld6 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %add.ptr17, i32 1) - %add.ptr20 = getelementptr inbounds i8, i8* %src.addr, i32 %mul5 - %vld7 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %add.ptr20, i32 1) - %add.ptr23 = getelementptr inbounds i8, i8* %src.addr, i32 %mul1 - %vld8 = tail call <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8* %add.ptr23, i32 1) - %vadd1 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld1, <8 x i8> %vld2) nounwind - %vadd2 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld2, <8 x i8> %vld3) nounwind - %vadd3 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld3, <8 x i8> %vld4) nounwind - %vadd4 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld4, <8 x i8> %vld5) nounwind - %vadd5 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld5, <8 x i8> %vld6) nounwind - %vadd6 = tail call <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8> %vld6, <8 x i8> %vld7) nounwind - tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* %add.ptr3, <8 x i8> %vadd1, i32 1) - tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* %add.ptr7, <8 x i8> %vadd2, i32 1) - tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* %add.ptr11, <8 x i8> %vadd3, i32 1) - tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* %src.addr, <8 x i8> %vadd4, i32 1) - tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* %add.ptr17, <8 x i8> %vadd5, i32 1) - tail call void @llvm.arm.neon.vst1.p0i8.v8i8(i8* %add.ptr20, <8 x i8> %vadd6, i32 1) - %inc = add nsw i32 %i.0110, 1 - %add.ptr45 = getelementptr inbounds i8, i8* %src.addr, i32 8 - %exitcond = icmp eq i32 %inc, 4 - br i1 %exitcond, label %for.end, label %for.body - -for.end: ; preds = %for.body - ret void -} - -declare <8 x i8> @llvm.arm.neon.vld1.v8i8.p0i8(i8*, i32) nounwind readonly - -declare void @llvm.arm.neon.vst1.p0i8.v8i8(i8*, <8 x i8>, i32) nounwind - -declare <8 x i8> @llvm.arm.neon.vhaddu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone diff --git a/llvm/test/Transforms/LoopStrengthReduce/ARM/lit.local.cfg b/llvm/test/Transforms/LoopStrengthReduce/ARM/lit.local.cfg deleted file mode 100644 index 98c6700c209..00000000000 --- a/llvm/test/Transforms/LoopStrengthReduce/ARM/lit.local.cfg +++ /dev/null @@ -1,3 +0,0 @@ -if not 'ARM' in config.root.targets: - config.unsupported = True - |
