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-rw-r--r--llvm/test/Transforms/InstSimplify/select.ll23
1 files changed, 20 insertions, 3 deletions
diff --git a/llvm/test/Transforms/InstSimplify/select.ll b/llvm/test/Transforms/InstSimplify/select.ll
index f126490bd5a..433b4e495aa 100644
--- a/llvm/test/Transforms/InstSimplify/select.ll
+++ b/llvm/test/Transforms/InstSimplify/select.ll
@@ -41,14 +41,31 @@ define i32 @cond_is_true(i32 %A, i32 %B) {
ret i32 %C
}
-define i32 @equal_arms(i1 %C, i32 %I) {
+define i32 @equal_arms(i1 %cond, i32 %x) {
; CHECK-LABEL: @equal_arms(
-; CHECK-NEXT: ret i32 [[I:%.*]]
+; CHECK-NEXT: ret i32 [[X:%.*]]
;
- %V = select i1 %C, i32 %I, i32 %I
+ %V = select i1 %cond, i32 %x, i32 %x
ret i32 %V
}
+define <2 x i32> @equal_arms_vec(<2 x i1> %cond, <2 x i32> %x) {
+; CHECK-LABEL: @equal_arms_vec(
+; CHECK-NEXT: ret <2 x i32> [[X:%.*]]
+;
+ %V = select <2 x i1> %cond, <2 x i32> %x, <2 x i32> %x
+ ret <2 x i32> %V
+}
+
+define <2 x i32> @equal_arms_vec_undef(<2 x i1> %cond) {
+; CHECK-LABEL: @equal_arms_vec_undef(
+; CHECK-NEXT: [[V:%.*]] = select <2 x i1> [[COND:%.*]], <2 x i32> <i32 42, i32 undef>, <2 x i32> <i32 undef, i32 42>
+; CHECK-NEXT: ret <2 x i32> [[V]]
+;
+ %V = select <2 x i1> %cond, <2 x i32> <i32 42, i32 undef>, <2 x i32> <i32 undef, i32 42>
+ ret <2 x i32> %V
+}
+
define <2 x i8> @vsel_tvec(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @vsel_tvec(
; CHECK-NEXT: ret <2 x i8> [[X:%.*]]
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