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-rw-r--r--llvm/test/Transforms/InstCombine/adjust-for-minmax.ll80
1 files changed, 48 insertions, 32 deletions
diff --git a/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll b/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll
index 1cb9322e57d..813171b8085 100644
--- a/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll
+++ b/llvm/test/Transforms/InstCombine/adjust-for-minmax.ll
@@ -68,12 +68,13 @@ define i32 @smax3(i32 %n) {
ret i32 %m
}
+; FIXME
; Swap vector signed pred and select ops.
define <2 x i32> @smax3_vec(<2 x i32> %n) {
; CHECK-LABEL: @smax3_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, zeroinitializer
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
@@ -94,12 +95,13 @@ define i32 @smin3(i32 %n) {
ret i32 %m
}
+; FIXME
; Swap vector signed pred and select ops.
define <2 x i32> @smin3_vec(<2 x i32> %n) {
; CHECK-LABEL: @smin3_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, zeroinitializer
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, <i32 1, i32 1>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp slt <2 x i32> %n, <i32 1, i32 1>
@@ -120,12 +122,13 @@ define i32 @umax3(i32 %n) {
ret i32 %m
}
+; FIXME
; Swap vector unsigned pred and select ops.
define <2 x i32> @umax3_vec(<2 x i32> %n) {
; CHECK-LABEL: @umax3_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 5, i32 5>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 5, i32 5>, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 4, i32 4>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 5, i32 5>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ugt <2 x i32> %n, <i32 4, i32 4>
@@ -146,12 +149,13 @@ define i32 @umin3(i32 %n) {
ret i32 %m
}
+; FIXME
; Swap vector unsigned pred and select ops.
define <2 x i32> @umin3_vec(<2 x i32> %n) {
; CHECK-LABEL: @umin3_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 6, i32 6>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 6, i32 6>, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 7, i32 7>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 6, i32 6>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ult <2 x i32> %n, <i32 7, i32 7>
@@ -172,12 +176,13 @@ define i32 @smax4(i32 %n) {
ret i32 %m
}
+; FIXME
; Canonicalize vector signed pred and swap pred and select ops.
define <2 x i32> @smax4_vec(<2 x i32> %n) {
; CHECK-LABEL: @smax4_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, zeroinitializer
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, <i32 -1, i32 -1>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sge <2 x i32> %n, zeroinitializer
@@ -198,12 +203,13 @@ define i32 @smin4(i32 %n) {
ret i32 %m
}
+; FIXME
; Canonicalize vector signed pred and swap pred and select ops.
define <2 x i32> @smin4_vec(<2 x i32> %n) {
; CHECK-LABEL: @smin4_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp sgt <2 x i32> %n, zeroinitializer
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> zeroinitializer, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp slt <2 x i32> %n, <i32 1, i32 1>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> zeroinitializer
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp sle <2 x i32> %n, zeroinitializer
@@ -224,12 +230,13 @@ define i32 @umax4(i32 %n) {
ret i32 %m
}
+; FIXME
; Canonicalize vector unsigned pred and swap pred and select ops.
define <2 x i32> @umax4_vec(<2 x i32> %n) {
; CHECK-LABEL: @umax4_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 8, i32 8>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 8, i32 8>, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 7, i32 7>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 8, i32 8>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp uge <2 x i32> %n, <i32 8, i32 8>
@@ -250,12 +257,13 @@ define i32 @umin4(i32 %n) {
ret i32 %m
}
+; FIXME
; Canonicalize vector unsigned pred and swap pred and select ops.
define <2 x i32> @umin4_vec(<2 x i32> %n) {
; CHECK-LABEL: @umin4_vec(
-; CHECK-NEXT: [[T:%.*]] = icmp ugt <2 x i32> %n, <i32 9, i32 9>
-; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> <i32 9, i32 9>, <2 x i32> %n
+; CHECK-NEXT: [[T:%.*]] = icmp ult <2 x i32> %n, <i32 10, i32 10>
+; CHECK-NEXT: [[M:%.*]] = select <2 x i1> [[T]], <2 x i32> %n, <2 x i32> <i32 9, i32 9>
; CHECK-NEXT: ret <2 x i32> [[M]]
;
%t = icmp ule <2 x i32> %n, <i32 9, i32 9>
@@ -276,11 +284,12 @@ define i64 @smax_sext(i32 %a) {
ret i64 %max
}
+; FIXME
define <2 x i64> @smax_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @smax_sext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i64> [[A_EXT]], zeroinitializer
-; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> zeroinitializer, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
+; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> zeroinitializer
; CHECK-NEXT: ret <2 x i64> [[MAX]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -302,11 +311,12 @@ define i64 @smin_sext(i32 %a) {
ret i64 %min
}
+; FIXME
define <2 x i64>@smin_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @smin_sext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt <2 x i64> [[A_EXT]], zeroinitializer
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> zeroinitializer, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp slt <2 x i32> %a, <i32 1, i32 1>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> zeroinitializer
; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -328,11 +338,12 @@ define i64 @umax_sext(i32 %a) {
ret i64 %max
}
+; FIXME
define <2 x i64> @umax_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umax_sext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3, i64 3>
-; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 3, i64 3>, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2>
+; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3>
; CHECK-NEXT: ret <2 x i64> [[MAX]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -354,11 +365,12 @@ define i64 @umin_sext(i32 %a) {
ret i64 %min
}
+; FIXME
define <2 x i64> @umin_sext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umin_sext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2, i64 2>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 2, i64 2>, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2>
; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -380,11 +392,12 @@ define i64 @umax_sext2(i32 %a) {
ret i64 %min
}
+; FIXME
define <2 x i64> @umax_sext2_vec(<2 x i32> %a) {
; CHECK-LABEL: @umax_sext2_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2, i64 2>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 2, i64 2>, <2 x i64> [[A_EXT]]
; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -406,11 +419,12 @@ define i64 @umin_sext2(i32 %a) {
ret i64 %min
}
+; FIXME
define <2 x i64> @umin_sext2_vec(<2 x i32> %a) {
; CHECK-LABEL: @umin_sext2_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = sext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3, i64 3>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3>
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 3, i64 3>, <2 x i64> [[A_EXT]]
; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = sext <2 x i32> %a to <2 x i64>
@@ -432,11 +446,12 @@ define i64 @umax_zext(i32 %a) {
ret i64 %max
}
+; FIXME
define <2 x i64> @umax_zext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umax_zext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = zext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i64> [[A_EXT]], <i64 3, i64 3>
-; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 3, i64 3>, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> %a, <i32 2, i32 2>
+; CHECK-NEXT: [[MAX:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 3, i64 3>
; CHECK-NEXT: ret <2 x i64> [[MAX]]
;
%a_ext = zext <2 x i32> %a to <2 x i64>
@@ -458,11 +473,12 @@ define i64 @umin_zext(i32 %a) {
ret i64 %min
}
+; FIXME
define <2 x i64> @umin_zext_vec(<2 x i32> %a) {
; CHECK-LABEL: @umin_zext_vec(
; CHECK-NEXT: [[A_EXT:%.*]] = zext <2 x i32> %a to <2 x i64>
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i64> [[A_EXT]], <i64 2, i64 2>
-; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> <i64 2, i64 2>, <2 x i64> [[A_EXT]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> %a, <i32 3, i32 3>
+; CHECK-NEXT: [[MIN:%.*]] = select <2 x i1> [[CMP]], <2 x i64> [[A_EXT]], <2 x i64> <i64 2, i64 2>
; CHECK-NEXT: ret <2 x i64> [[MIN]]
;
%a_ext = zext <2 x i32> %a to <2 x i64>
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