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-rw-r--r--llvm/test/Transforms/InstCombine/vector-mul.ll445
1 files changed, 445 insertions, 0 deletions
diff --git a/llvm/test/Transforms/InstCombine/vector-mul.ll b/llvm/test/Transforms/InstCombine/vector-mul.ll
new file mode 100644
index 00000000000..d9809281edb
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/vector-mul.ll
@@ -0,0 +1,445 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -instcombine -S | FileCheck %s
+
+; Check that instcombine rewrites multiply by a vector
+; of known constant power-of-2 elements with vector shift.
+
+define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
+; CHECK-LABEL: @Zero_i8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret <4 x i8> zeroinitializer
+;
+entry:
+ %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
+ ret <4 x i8> %mul
+}
+
+define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
+; CHECK-LABEL: @Identity_i8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret <4 x i8> [[INVEC:%.*]]
+;
+entry:
+ %mul = mul <4 x i8> %InVec, <i8 1, i8 1, i8 1, i8 1>
+ ret <4 x i8> %mul
+}
+
+define <4 x i8> @AddToSelf_i8(<4 x i8> %InVec) {
+; CHECK-LABEL: @AddToSelf_i8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 1, i8 1, i8 1, i8 1>
+; CHECK-NEXT: ret <4 x i8> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
+ ret <4 x i8> %mul
+}
+
+define <4 x i8> @SplatPow2Test1_i8(<4 x i8> %InVec) {
+; CHECK-LABEL: @SplatPow2Test1_i8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 2, i8 2, i8 2, i8 2>
+; CHECK-NEXT: ret <4 x i8> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 4, i8 4>
+ ret <4 x i8> %mul
+}
+
+define <4 x i8> @SplatPow2Test2_i8(<4 x i8> %InVec) {
+; CHECK-LABEL: @SplatPow2Test2_i8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 3, i8 3, i8 3, i8 3>
+; CHECK-NEXT: ret <4 x i8> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i8> %InVec, <i8 8, i8 8, i8 8, i8 8>
+ ret <4 x i8> %mul
+}
+
+define <4 x i8> @MulTest1_i8(<4 x i8> %InVec) {
+; CHECK-LABEL: @MulTest1_i8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 0, i8 1, i8 2, i8 3>
+; CHECK-NEXT: ret <4 x i8> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i8> %InVec, <i8 1, i8 2, i8 4, i8 8>
+ ret <4 x i8> %mul
+}
+
+define <4 x i8> @MulTest2_i8(<4 x i8> %InVec) {
+; CHECK-LABEL: @MulTest2_i8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i8> [[INVEC:%.*]], <i8 3, i8 3, i8 3, i8 3>
+; CHECK-NEXT: ret <4 x i8> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i8> %InVec, <i8 3, i8 3, i8 3, i8 3>
+ ret <4 x i8> %mul
+}
+
+define <4 x i8> @MulTest3_i8(<4 x i8> %InVec) {
+; CHECK-LABEL: @MulTest3_i8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i8> [[INVEC:%.*]], <i8 2, i8 2, i8 1, i8 1>
+; CHECK-NEXT: ret <4 x i8> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 2, i8 2>
+ ret <4 x i8> %mul
+}
+
+define <4 x i8> @MulTest4_i8(<4 x i8> %InVec) {
+; CHECK-LABEL: @MulTest4_i8(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i8> [[INVEC:%.*]], <i8 4, i8 4, i8 0, i8 1>
+; CHECK-NEXT: ret <4 x i8> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i8> %InVec, <i8 4, i8 4, i8 0, i8 1>
+ ret <4 x i8> %mul
+}
+
+define <4 x i16> @Zero_i16(<4 x i16> %InVec) {
+; CHECK-LABEL: @Zero_i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret <4 x i16> zeroinitializer
+;
+entry:
+ %mul = mul <4 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0>
+ ret <4 x i16> %mul
+}
+
+define <4 x i16> @Identity_i16(<4 x i16> %InVec) {
+; CHECK-LABEL: @Identity_i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret <4 x i16> [[INVEC:%.*]]
+;
+entry:
+ %mul = mul <4 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1>
+ ret <4 x i16> %mul
+}
+
+define <4 x i16> @AddToSelf_i16(<4 x i16> %InVec) {
+; CHECK-LABEL: @AddToSelf_i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i16> [[INVEC:%.*]], <i16 1, i16 1, i16 1, i16 1>
+; CHECK-NEXT: ret <4 x i16> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i16> %InVec, <i16 2, i16 2, i16 2, i16 2>
+ ret <4 x i16> %mul
+}
+
+define <4 x i16> @SplatPow2Test1_i16(<4 x i16> %InVec) {
+; CHECK-LABEL: @SplatPow2Test1_i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i16> [[INVEC:%.*]], <i16 2, i16 2, i16 2, i16 2>
+; CHECK-NEXT: ret <4 x i16> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i16> %InVec, <i16 4, i16 4, i16 4, i16 4>
+ ret <4 x i16> %mul
+}
+
+define <4 x i16> @SplatPow2Test2_i16(<4 x i16> %InVec) {
+; CHECK-LABEL: @SplatPow2Test2_i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i16> [[INVEC:%.*]], <i16 3, i16 3, i16 3, i16 3>
+; CHECK-NEXT: ret <4 x i16> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i16> %InVec, <i16 8, i16 8, i16 8, i16 8>
+ ret <4 x i16> %mul
+}
+
+define <4 x i16> @MulTest1_i16(<4 x i16> %InVec) {
+; CHECK-LABEL: @MulTest1_i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i16> [[INVEC:%.*]], <i16 0, i16 1, i16 2, i16 3>
+; CHECK-NEXT: ret <4 x i16> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i16> %InVec, <i16 1, i16 2, i16 4, i16 8>
+ ret <4 x i16> %mul
+}
+
+define <4 x i16> @MulTest2_i16(<4 x i16> %InVec) {
+; CHECK-LABEL: @MulTest2_i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i16> [[INVEC:%.*]], <i16 3, i16 3, i16 3, i16 3>
+; CHECK-NEXT: ret <4 x i16> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i16> %InVec, <i16 3, i16 3, i16 3, i16 3>
+ ret <4 x i16> %mul
+}
+
+define <4 x i16> @MulTest3_i16(<4 x i16> %InVec) {
+; CHECK-LABEL: @MulTest3_i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i16> [[INVEC:%.*]], <i16 2, i16 2, i16 1, i16 1>
+; CHECK-NEXT: ret <4 x i16> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i16> %InVec, <i16 4, i16 4, i16 2, i16 2>
+ ret <4 x i16> %mul
+}
+
+define <4 x i16> @MulTest4_i16(<4 x i16> %InVec) {
+; CHECK-LABEL: @MulTest4_i16(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i16> [[INVEC:%.*]], <i16 4, i16 4, i16 0, i16 2>
+; CHECK-NEXT: ret <4 x i16> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i16> %InVec, <i16 4, i16 4, i16 0, i16 2>
+ ret <4 x i16> %mul
+}
+
+define <4 x i32> @Zero_i32(<4 x i32> %InVec) {
+; CHECK-LABEL: @Zero_i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret <4 x i32> zeroinitializer
+;
+entry:
+ %mul = mul <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
+ ret <4 x i32> %mul
+}
+
+define <4 x i32> @Identity_i32(<4 x i32> %InVec) {
+; CHECK-LABEL: @Identity_i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret <4 x i32> [[INVEC:%.*]]
+;
+entry:
+ %mul = mul <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
+ ret <4 x i32> %mul
+}
+
+define <4 x i32> @AddToSelf_i32(<4 x i32> %InVec) {
+; CHECK-LABEL: @AddToSelf_i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i32> [[INVEC:%.*]], <i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i32> %InVec, <i32 2, i32 2, i32 2, i32 2>
+ ret <4 x i32> %mul
+}
+
+define <4 x i32> @SplatPow2Test1_i32(<4 x i32> %InVec) {
+; CHECK-LABEL: @SplatPow2Test1_i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i32> [[INVEC:%.*]], <i32 2, i32 2, i32 2, i32 2>
+; CHECK-NEXT: ret <4 x i32> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i32> %InVec, <i32 4, i32 4, i32 4, i32 4>
+ ret <4 x i32> %mul
+}
+
+define <4 x i32> @SplatPow2Test2_i32(<4 x i32> %InVec) {
+; CHECK-LABEL: @SplatPow2Test2_i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i32> [[INVEC:%.*]], <i32 3, i32 3, i32 3, i32 3>
+; CHECK-NEXT: ret <4 x i32> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i32> %InVec, <i32 8, i32 8, i32 8, i32 8>
+ ret <4 x i32> %mul
+}
+
+define <4 x i32> @MulTest1_i32(<4 x i32> %InVec) {
+; CHECK-LABEL: @MulTest1_i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i32> [[INVEC:%.*]], <i32 0, i32 1, i32 2, i32 3>
+; CHECK-NEXT: ret <4 x i32> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i32> %InVec, <i32 1, i32 2, i32 4, i32 8>
+ ret <4 x i32> %mul
+}
+
+define <4 x i32> @MulTest2_i32(<4 x i32> %InVec) {
+; CHECK-LABEL: @MulTest2_i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[INVEC:%.*]], <i32 3, i32 3, i32 3, i32 3>
+; CHECK-NEXT: ret <4 x i32> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i32> %InVec, <i32 3, i32 3, i32 3, i32 3>
+ ret <4 x i32> %mul
+}
+
+define <4 x i32> @MulTest3_i32(<4 x i32> %InVec) {
+; CHECK-LABEL: @MulTest3_i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i32> [[INVEC:%.*]], <i32 2, i32 2, i32 1, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i32> %InVec, <i32 4, i32 4, i32 2, i32 2>
+ ret <4 x i32> %mul
+}
+
+define <4 x i32> @MulTest4_i32(<4 x i32> %InVec) {
+; CHECK-LABEL: @MulTest4_i32(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[INVEC:%.*]], <i32 4, i32 4, i32 0, i32 1>
+; CHECK-NEXT: ret <4 x i32> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i32> %InVec, <i32 4, i32 4, i32 0, i32 1>
+ ret <4 x i32> %mul
+}
+
+define <4 x i64> @Zero_i64(<4 x i64> %InVec) {
+; CHECK-LABEL: @Zero_i64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret <4 x i64> zeroinitializer
+;
+entry:
+ %mul = mul <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
+ ret <4 x i64> %mul
+}
+
+define <4 x i64> @Identity_i64(<4 x i64> %InVec) {
+; CHECK-LABEL: @Identity_i64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: ret <4 x i64> [[INVEC:%.*]]
+;
+entry:
+ %mul = mul <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
+ ret <4 x i64> %mul
+}
+
+define <4 x i64> @AddToSelf_i64(<4 x i64> %InVec) {
+; CHECK-LABEL: @AddToSelf_i64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i64> [[INVEC:%.*]], <i64 1, i64 1, i64 1, i64 1>
+; CHECK-NEXT: ret <4 x i64> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i64> %InVec, <i64 2, i64 2, i64 2, i64 2>
+ ret <4 x i64> %mul
+}
+
+define <4 x i64> @SplatPow2Test1_i64(<4 x i64> %InVec) {
+; CHECK-LABEL: @SplatPow2Test1_i64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i64> [[INVEC:%.*]], <i64 2, i64 2, i64 2, i64 2>
+; CHECK-NEXT: ret <4 x i64> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i64> %InVec, <i64 4, i64 4, i64 4, i64 4>
+ ret <4 x i64> %mul
+}
+
+define <4 x i64> @SplatPow2Test2_i64(<4 x i64> %InVec) {
+; CHECK-LABEL: @SplatPow2Test2_i64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i64> [[INVEC:%.*]], <i64 3, i64 3, i64 3, i64 3>
+; CHECK-NEXT: ret <4 x i64> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i64> %InVec, <i64 8, i64 8, i64 8, i64 8>
+ ret <4 x i64> %mul
+}
+
+define <4 x i64> @MulTest1_i64(<4 x i64> %InVec) {
+; CHECK-LABEL: @MulTest1_i64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i64> [[INVEC:%.*]], <i64 0, i64 1, i64 2, i64 3>
+; CHECK-NEXT: ret <4 x i64> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i64> %InVec, <i64 1, i64 2, i64 4, i64 8>
+ ret <4 x i64> %mul
+}
+
+define <4 x i64> @MulTest2_i64(<4 x i64> %InVec) {
+; CHECK-LABEL: @MulTest2_i64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i64> [[INVEC:%.*]], <i64 3, i64 3, i64 3, i64 3>
+; CHECK-NEXT: ret <4 x i64> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i64> %InVec, <i64 3, i64 3, i64 3, i64 3>
+ ret <4 x i64> %mul
+}
+
+define <4 x i64> @MulTest3_i64(<4 x i64> %InVec) {
+; CHECK-LABEL: @MulTest3_i64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = shl <4 x i64> [[INVEC:%.*]], <i64 2, i64 2, i64 1, i64 1>
+; CHECK-NEXT: ret <4 x i64> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i64> %InVec, <i64 4, i64 4, i64 2, i64 2>
+ ret <4 x i64> %mul
+}
+
+define <4 x i64> @MulTest4_i64(<4 x i64> %InVec) {
+; CHECK-LABEL: @MulTest4_i64(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i64> [[INVEC:%.*]], <i64 4, i64 4, i64 0, i64 1>
+; CHECK-NEXT: ret <4 x i64> [[MUL]]
+;
+entry:
+ %mul = mul <4 x i64> %InVec, <i64 4, i64 4, i64 0, i64 1>
+ ret <4 x i64> %mul
+}
+
+; Test also that the following rewriting rule works with vectors
+; of integers as well:
+; ((X << C1)*C2) == (X * (C2 << C1))
+
+define <4 x i8> @ShiftMulTest1(<4 x i8> %InVec) {
+; CHECK-LABEL: @ShiftMulTest1(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i8> [[INVEC:%.*]], <i8 12, i8 12, i8 12, i8 12>
+; CHECK-NEXT: ret <4 x i8> [[MUL]]
+;
+entry:
+ %shl = shl <4 x i8> %InVec, <i8 2, i8 2, i8 2, i8 2>
+ %mul = mul <4 x i8> %shl, <i8 3, i8 3, i8 3, i8 3>
+ ret <4 x i8> %mul
+}
+
+define <4 x i16> @ShiftMulTest2(<4 x i16> %InVec) {
+; CHECK-LABEL: @ShiftMulTest2(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i16> [[INVEC:%.*]], <i16 12, i16 12, i16 12, i16 12>
+; CHECK-NEXT: ret <4 x i16> [[MUL]]
+;
+entry:
+ %shl = shl <4 x i16> %InVec, <i16 2, i16 2, i16 2, i16 2>
+ %mul = mul <4 x i16> %shl, <i16 3, i16 3, i16 3, i16 3>
+ ret <4 x i16> %mul
+}
+
+define <4 x i32> @ShiftMulTest3(<4 x i32> %InVec) {
+; CHECK-LABEL: @ShiftMulTest3(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[INVEC:%.*]], <i32 12, i32 12, i32 12, i32 12>
+; CHECK-NEXT: ret <4 x i32> [[MUL]]
+;
+entry:
+ %shl = shl <4 x i32> %InVec, <i32 2, i32 2, i32 2, i32 2>
+ %mul = mul <4 x i32> %shl, <i32 3, i32 3, i32 3, i32 3>
+ ret <4 x i32> %mul
+}
+
+define <4 x i64> @ShiftMulTest4(<4 x i64> %InVec) {
+; CHECK-LABEL: @ShiftMulTest4(
+; CHECK-NEXT: entry:
+; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i64> [[INVEC:%.*]], <i64 12, i64 12, i64 12, i64 12>
+; CHECK-NEXT: ret <4 x i64> [[MUL]]
+;
+entry:
+ %shl = shl <4 x i64> %InVec, <i64 2, i64 2, i64 2, i64 2>
+ %mul = mul <4 x i64> %shl, <i64 3, i64 3, i64 3, i64 3>
+ ret <4 x i64> %mul
+}
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