diff options
Diffstat (limited to 'llvm/test/MC')
22 files changed, 153 insertions, 103 deletions
diff --git a/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt b/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt index 5bdf8f17eb6..382e085acf9 100644 --- a/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2-el.txt @@ -136,11 +136,11 @@ 0x22 0x98 0xd1 0xb9 # CHECK: swr $17, -26590($14) 0x34 0x00 0x03 0x00 # CHECK: teq $zero, $3 0x34 0x9b 0xa7 0x00 # CHECK: teq $5, $7, 620 -0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, 48032 +0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, -17504 0x30 0x00 0xea 0x00 # CHECK: tge $7, $10 0x30 0x55 0xb3 0x00 # CHECK: tge $5, $19, 340 0xa1 0x13 0x28 0x06 # CHECK: tgei $17, 5025 -0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, 36915 +0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, -28621 0x31 0x00 0xdc 0x02 # CHECK: tgeu $22, $gp 0xf1 0x5e 0x8e 0x02 # CHECK: tgeu $20, $14, 379 0x08 0x00 0x00 0x42 # CHECK: tlbp @@ -149,13 +149,13 @@ 0x06 0x00 0x00 0x42 # CHECK: tlbwr 0x32 0x00 0xed 0x01 # CHECK: tlt $15, $13 0x72 0x21 0x53 0x00 # CHECK: tlt $2, $19, 133 -0xbd 0xad 0xca 0x05 # CHECK: tlti $14, 44477 -0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, 60460 +0xbd 0xad 0xca 0x05 # CHECK: tlti $14, -21059 +0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, -5076 0x33 0x00 0x70 0x01 # CHECK: tltu $11, $16 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 -0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, 35889 +0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, -29647 0x8d 0x75 0x20 0x46 # CHECK: trunc.w.d $f22, $f14 0x0d 0xf7 0x00 0x46 # CHECK: trunc.w.s $f28, $f30 0x26 0x90 0x9e 0x00 # CHECK: xor $18, $4, $fp diff --git a/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt b/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt index a0b766a5dc1..6158ea8ca02 100644 --- a/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt +++ b/llvm/test/MC/Disassembler/Mips/mips2/valid-mips2.txt @@ -72,14 +72,14 @@ 0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x09 0x33 0x00 0x2a # CHECK: j 80478376 0x0b 0x2a 0xd1 0x44 # CHECK: j 212550928 diff --git a/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt b/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt index 6ffe7748e95..939b7966859 100644 --- a/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3-el.txt @@ -184,11 +184,11 @@ 0x22 0x98 0xd1 0xb9 # CHECK: swr $17, -26590($14) 0x34 0x00 0x03 0x00 # CHECK: teq $zero, $3 0x34 0x9b 0xa7 0x00 # CHECK: teq $5, $7, 620 -0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, 48032 +0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, -17504 0x30 0x00 0xea 0x00 # CHECK: tge $7, $10 0x30 0x55 0xb3 0x00 # CHECK: tge $5, $19, 340 0xa1 0x13 0x28 0x06 # CHECK: tgei $17, 5025 -0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, 36915 +0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, -28621 0x31 0x00 0xdc 0x02 # CHECK: tgeu $22, $gp 0xf1 0x5e 0x8e 0x02 # CHECK: tgeu $20, $14, 379 0x08 0x00 0x00 0x42 # CHECK: tlbp @@ -197,13 +197,13 @@ 0x06 0x00 0x00 0x42 # CHECK: tlbwr 0x32 0x00 0xed 0x01 # CHECK: tlt $15, $13 0x72 0x21 0x53 0x00 # CHECK: tlt $2, $19, 133 -0xbd 0xad 0xca 0x05 # CHECK: tlti $14, 44477 -0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, 60460 +0xbd 0xad 0xca 0x05 # CHECK: tlti $14, -21059 +0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, -5076 0x33 0x00 0x70 0x01 # CHECK: tltu $11, $16 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 -0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, 35889 +0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, -29647 0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23 0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31 0x8d 0x75 0x20 0x46 # CHECK: trunc.w.d $f22, $f14 diff --git a/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt b/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt index fb244e2f154..4877280000f 100644 --- a/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt +++ b/llvm/test/MC/Disassembler/Mips/mips3/valid-mips3.txt @@ -103,14 +103,14 @@ 0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x09 0x33 0x00 0x2a # CHECK: j 80478376 0x0b 0x2a 0xd1 0x44 # CHECK: j 212550928 diff --git a/llvm/test/MC/Disassembler/Mips/mips32/valid-mips32.txt b/llvm/test/MC/Disassembler/Mips/mips32/valid-mips32.txt index f71b2a16fcf..d86f9e518fa 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32/valid-mips32.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32/valid-mips32.txt @@ -105,14 +105,14 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt index acce76bcfdd..7ee4f4bf7fa 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r2/valid-mips32r2.txt @@ -110,15 +110,15 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 0x07 0xdf 0xe8 0x07 # CHECK: synci -6137($fp) -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt index 18dbd9ea7a4..8e5c16b4a33 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r3/valid-mips32r3.txt @@ -107,15 +107,15 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 0x07 0xdf 0xe8 0x07 # CHECK: synci -6137($fp) -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 diff --git a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt index 8b553cfab2c..afe1b695dea 100644 --- a/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt +++ b/llvm/test/MC/Disassembler/Mips/mips32r5/valid-mips32r5.txt @@ -107,15 +107,15 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 0x07 0xdf 0xe8 0x07 # CHECK: synci -6137($fp) -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt index 1d1044d3205..4a3d78cde55 100644 --- a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt +++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4-el.txt @@ -204,11 +204,11 @@ 0x08 0x98 0x4c 0x4f # CHECK: swxc1 $f19, $12($26) 0x34 0x00 0x03 0x00 # CHECK: teq $zero, $3 0x34 0x9b 0xa7 0x00 # CHECK: teq $5, $7, 620 -0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, 48032 +0xa0 0xbb 0xac 0x06 # CHECK: teqi $21, -17504 0x30 0x00 0xea 0x00 # CHECK: tge $7, $10 0x30 0x55 0xb3 0x00 # CHECK: tge $5, $19, 340 0xa1 0x13 0x28 0x06 # CHECK: tgei $17, 5025 -0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, 36915 +0x33 0x90 0xa9 0x07 # CHECK: tgeiu $sp, -28621 0x31 0x00 0xdc 0x02 # CHECK: tgeu $22, $gp 0xf1 0x5e 0x8e 0x02 # CHECK: tgeu $20, $14, 379 0x08 0x00 0x00 0x42 # CHECK: tlbp @@ -217,13 +217,13 @@ 0x06 0x00 0x00 0x42 # CHECK: tlbwr 0x32 0x00 0xed 0x01 # CHECK: tlt $15, $13 0x72 0x21 0x53 0x00 # CHECK: tlt $2, $19, 133 -0xbd 0xad 0xca 0x05 # CHECK: tlti $14, 44477 -0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, 60460 +0xbd 0xad 0xca 0x05 # CHECK: tlti $14, -21059 +0x2c 0xec 0xeb 0x07 # CHECK: tltiu $ra, -5076 0x33 0x00 0x70 0x01 # CHECK: tltu $11, $16 0x33 0xfe 0x1d 0x02 # CHECK: tltu $16, $sp, 1016 0x36 0x00 0xd1 0x00 # CHECK: tne $6, $17 0x76 0xdd 0xe8 0x00 # CHECK: tne $7, $8, 885 -0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, 35889 +0x31 0x8c 0x8e 0x05 # CHECK: tnei $12, -29647 0xc9 0xbd 0x20 0x46 # CHECK: trunc.l.d $f23, $f23 0x09 0xff 0x00 0x46 # CHECK: trunc.l.s $f28, $f31 0x8d 0x75 0x20 0x46 # CHECK: trunc.w.d $f22, $f14 diff --git a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt index 47ab90809ec..f225d2cc220 100644 --- a/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt +++ b/llvm/test/MC/Disassembler/Mips/mips4/valid-mips4.txt @@ -107,14 +107,14 @@ 0x04 0xd0 0x14 0x9b # CHECK: bltzal $6, 21104 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x09 0x33 0x00 0x2a # CHECK: j 80478376 0x0b 0x2a 0xd1 0x44 # CHECK: j 212550928 diff --git a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt index 2ba1ecdf5b8..5b5427db1e1 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64/valid-mips64.txt @@ -147,14 +147,14 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt index ac9d2b80862..5de751234c8 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r2/valid-mips64r2.txt @@ -161,14 +161,14 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt index 31b9f66bce1..01c02ad8222 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r3/valid-mips64r3.txt @@ -158,14 +158,14 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 diff --git a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt index 1fa0e629b37..12e5294d36d 100644 --- a/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt +++ b/llvm/test/MC/Disassembler/Mips/mips64r5/valid-mips64r5.txt @@ -158,14 +158,14 @@ 0x04 0xd1 0x01 0x4c # CHECK: bgezal $6, 1332 0x04 0xd1 0x14 0x9b # CHECK: bgezal $6, 21104 0x04 0xd2 0x00 0x7a # CHECK: bltzall $6, 492 -0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, 35889 +0x05 0x8e 0x8c 0x31 # CHECK: tnei $12, -29647 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296 -0x05 0xca 0xad 0xbd # CHECK: tlti $14, 44477 +0x05 0xca 0xad 0xbd # CHECK: tlti $14, -21059 0x06 0x22 0xf6 0x45 # CHECK: bltzl $17, -9960 0x06 0x28 0x13 0xa1 # CHECK: tgei $17, 5025 -0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, 48032 -0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, 36915 -0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, 60460 +0x06 0xac 0xbb 0xa0 # CHECK: teqi $21, -17504 +0x07 0xa9 0x90 0x33 # CHECK: tgeiu $sp, -28621 +0x07 0xeb 0xec 0x2c # CHECK: tltiu $ra, -5076 0x08 0x00 0x00 0x01 # CHECK: j 4 0x08 0x00 0x01 0x4c # CHECK: j 1328 0x09 0x33 0x00 0x2a # CHECK: j 80478376 diff --git a/llvm/test/MC/Mips/dsp/invalid.s b/llvm/test/MC/Mips/dsp/invalid.s index 8bd0906e67f..1d50b829985 100644 --- a/llvm/test/MC/Mips/dsp/invalid.s +++ b/llvm/test/MC/Mips/dsp/invalid.s @@ -1,25 +1,39 @@ # RUN: not llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mattr=dsp 2>%t1 # RUN: FileCheck %s < %t1 + extp $2, $ac1, -1 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate + extp $2, $ac1, 32 # CHECK: :[[@LINE]]:18: error: expected 5-bit unsigned immediate + extpdp $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + extpdp $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + extr.w $2, $ac1, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + extr.w $2, $ac1, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + extr_r.w $2, $ac1, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate + extr_r.w $2, $ac1, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate + extr_rs.w $2, $ac1, -1 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate + extr_rs.w $2, $ac1, 32 # CHECK: :[[@LINE]]:23: error: expected 5-bit unsigned immediate shll.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shll.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shll_s.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate shll_s.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate shll.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shll.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate - // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added - shll_s.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate - shll_s.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shll_s.w $3, $4, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shll_s.w $3, $4, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate shra.ph $3, $4, 16 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shra.ph $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 4-bit unsigned immediate shra_r.ph $3, $4, 16 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate shra_r.ph $3, $4, -1 # CHECK: :[[@LINE]]:21: error: expected 4-bit unsigned immediate - // FIXME: Following invalid tests are temporarely disabled, until operand check for uimm5 is added - shra_r.w $3, $4, 32 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate - shra_r.w $3, $4, -1 # -CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shra_r.w $3, $4, 32 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate + shra_r.w $3, $4, -1 # CHECK: :[[@LINE]]:20: error: expected 5-bit unsigned immediate shrl.qb $3, $4, 8 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shrl.qb $3, $4, -1 # CHECK: :[[@LINE]]:19: error: expected 3-bit unsigned immediate shilo $ac1, 64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate shilo $ac1, -64 # CHECK: :[[@LINE]]:15: error: expected 6-bit signed immediate - wrdsp $5, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate + repl.qb $2, -1 # CHECK: :[[@LINE]]:15: error: expected 8-bit unsigned immediate + repl.qb $2, 256 # CHECK: :[[@LINE]]:15: error: expected 8-bit unsigned immediate + repl.ph $2, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + repl.ph $2, 1024 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + rddsp $2, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate + rddsp $2, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate wrdsp $5, -1 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate + wrdsp $5, 1024 # CHECK: :[[@LINE]]:13: error: expected 10-bit unsigned immediate diff --git a/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s new file mode 100644 index 00000000000..df441ead705 --- /dev/null +++ b/llvm/test/MC/Mips/micromips32r6/invalid-wrong-error.s @@ -0,0 +1,27 @@ +# Instructions that are correctly rejected but emit a wrong or misleading error. +# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips32r6 -mattr=micromips 2>%t1 +# RUN: FileCheck %s < %t1 + + + # The 10-bit immediate supported by the standard encodings cause us to emit + # the diagnostic for the 10-bit form. This isn't exactly wrong but it is + # misleading. Ideally, we'd emit every way to achieve a valid match instead + # of picking only one. + teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + teq $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tge $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tge $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tge $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tgeu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tgeu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tgeu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tlt $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/micromips32r6/invalid.s b/llvm/test/MC/Mips/micromips32r6/invalid.s index 41c661b0492..579620ddc0f 100644 --- a/llvm/test/MC/Mips/micromips32r6/invalid.s +++ b/llvm/test/MC/Mips/micromips32r6/invalid.s @@ -54,28 +54,16 @@ pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tge $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tge $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tge $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tgeu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tgeu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tgeu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tlt $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tltu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tne $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tne $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tne $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range - teq $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tge $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tgeu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tltu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tne $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wait -1 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate wait 1024 # CHECK: :[[@LINE]]:8: error: expected 10-bit unsigned immediate wrpgpr $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/micromips64r6/invalid-wrong-error.s b/llvm/test/MC/Mips/micromips64r6/invalid-wrong-error.s new file mode 100644 index 00000000000..65e0249ca98 --- /dev/null +++ b/llvm/test/MC/Mips/micromips64r6/invalid-wrong-error.s @@ -0,0 +1,27 @@ +# Instructions that are correctly rejected but emit a wrong or misleading error. +# RUN: not llvm-mc %s -triple=mips -show-encoding -mcpu=mips64r6 -mattr=micromips 2>%t1 +# RUN: FileCheck %s < %t1 + + + # The 10-bit immediate supported by the standard encodings cause us to emit + # the diagnostic for the 10-bit form. This isn't exactly wrong but it is + # misleading. Ideally, we'd emit every way to achieve a valid match instead + # of picking only one. + teq $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + teq $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + teq $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tge $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tge $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tge $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tgeu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tgeu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tgeu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tlt $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tlt $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tlt $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tltu $8, $9, $2 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tltu $8, $9, -1 # CHECK: :[[@LINE]]:16: error: expected 10-bit unsigned immediate + tltu $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled + tne $8, $9, $2 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tne $8, $9, -1 # CHECK: :[[@LINE]]:15: error: expected 10-bit unsigned immediate + tne $8, $9, 16 # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/micromips64r6/invalid.s b/llvm/test/MC/Mips/micromips64r6/invalid.s index df1005dfa0b..a4d892572c2 100644 --- a/llvm/test/MC/Mips/micromips64r6/invalid.s +++ b/llvm/test/MC/Mips/micromips64r6/invalid.s @@ -79,28 +79,16 @@ pref 32, 255($7) # CHECK: :[[@LINE]]:8: error: expected 5-bit unsigned immediate teq $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction teq $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - teq $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tge $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tge $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tge $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tgeu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tgeu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tgeu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tlt $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tlt $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tlt $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tltu $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tltu $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tltu $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range tne $34, $9, 5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction tne $8, $35, 6 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tne $8, $9, 16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range - teq $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tge $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tgeu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tlt $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tltu $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction - tne $8, $9, $2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wrpgpr $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wrpgpr $3, $33 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction wsbh $34, $4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/Mips/mips32r2/invalid-dsp.s b/llvm/test/MC/Mips/mips32r2/invalid-dsp.s index 66e5f63129a..2314d39e812 100644 --- a/llvm/test/MC/Mips/mips32r2/invalid-dsp.s +++ b/llvm/test/MC/Mips/mips32r2/invalid-dsp.s @@ -77,7 +77,7 @@ precrq_rs.ph.w $a1,$k0,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled precrqu_s.qb.ph $zero,$gp,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled raddu.w.qb $25,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - repl.ph $at,-307 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + repl.ph $at,307 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled replv.ph $v1,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled replv.qb $25,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled shilo $ac1,26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips32r2/invalid-dspr2.s b/llvm/test/MC/Mips/mips32r2/invalid-dspr2.s index 5c31b465ca1..026ae183820 100644 --- a/llvm/test/MC/Mips/mips32r2/invalid-dspr2.s +++ b/llvm/test/MC/Mips/mips32r2/invalid-dspr2.s @@ -103,7 +103,7 @@ precrq_rs.ph.w $a1,$k0,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled precrqu_s.qb.ph $zero,$gp,$s5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled raddu.w.qb $25,$s3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled - repl.ph $at,-307 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + repl.ph $at,307 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled replv.ph $v1,$s7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled replv.qb $25,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled shilo $ac1,26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips32r2/invalid.s b/llvm/test/MC/Mips/mips32r2/invalid.s index 6001aeacf9b..9eb9fff5ac4 100644 --- a/llvm/test/MC/Mips/mips32r2/invalid.s +++ b/llvm/test/MC/Mips/mips32r2/invalid.s @@ -6,6 +6,8 @@ .text .set noreorder + andi $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate + andi $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate cache -1, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate cache 32, 255($7) # CHECK: :[[@LINE]]:15: error: expected 5-bit unsigned immediate # FIXME: Check '0 < pos + size <= 32' constraint on ext @@ -18,6 +20,8 @@ ins $2, $3, 32, 1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate jalr.hb $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different jalr.hb $31, $31 # CHECK: :[[@LINE]]:9: error: source and destination must be different + ori $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate + ori $2, $3, 65536 # CHECK: :[[@LINE]]:21: error: expected 16-bit unsigned immediate pref -1, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate pref 32, 255($7) # CHECK: :[[@LINE]]:14: error: expected 5-bit unsigned immediate sll $2, $3, -1 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate @@ -28,3 +32,5 @@ sra $2, $3, 32 # CHECK: :[[@LINE]]:21: error: expected 5-bit unsigned immediate rotr $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate rotr $2, $3, 32 # CHECK: :[[@LINE]]:22: error: expected 5-bit unsigned immediate + xori $2, $3, -1 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate + xori $2, $3, 65536 # CHECK: :[[@LINE]]:22: error: expected 16-bit unsigned immediate |
