5 files changed, 86 insertions, 16 deletions
diff --git a/llvm/test/MC/AMDGPU/sopc-err.s b/llvm/test/MC/AMDGPU/sopc-err.s
index 10b25445376..88788862f1d 100644
--- a/llvm/test/MC/AMDGPU/sopc-err.s
+++ b/llvm/test/MC/AMDGPU/sopc-err.s
@@ -1,13 +1,31 @@
 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
 
 s_set_gpr_idx_on s0, s1
-// GCN: error: invalid operand for instruction
+// VI: error: expected absolute expression
 
 s_set_gpr_idx_on s0, 16
-// GCN: error: invalid operand for instruction
+// VI: error: invalid immediate: only 4-bit values are legal
 
 s_set_gpr_idx_on s0, -1
-// GCN: error: invalid operand for instruction
+// VI: error: invalid immediate: only 4-bit values are legal
+
+s_set_gpr_idx_on s0, gpr_idx
+// VI: error: expected absolute expression
+
+s_set_gpr_idx_on s0, gpr_idx(
+// VI: error: expected a VGPR index mode or a closing parenthesis
+
+s_set_gpr_idx_on s0, gpr_idx(X)
+// VI: error: expected a VGPR index mode
+
+s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC1,DST)
+// VI: error: duplicate VGPR index mode
+
+s_set_gpr_idx_on s0, gpr_idx(DST
+// VI: error: expected a comma or a closing parenthesis
+
+s_set_gpr_idx_on s0, gpr_idx(SRC0,
+// VI: error: expected a VGPR index mode
 
 s_cmp_eq_i32 0x12345678, 0x12345679
 // GCN: error: only one literal operand is allowed
diff --git a/llvm/test/MC/AMDGPU/sopc.s b/llvm/test/MC/AMDGPU/sopc.s
index c7b337d75a5..55ef262318d 100644
--- a/llvm/test/MC/AMDGPU/sopc.s
+++ b/llvm/test/MC/AMDGPU/sopc.s
@@ -71,18 +71,44 @@ s_cmp_lg_u64 s[0:1], s[2:3]
 // VI: s_cmp_lg_u64 s[0:1], s[2:3] ; encoding: [0x00,0x02,0x13,0xbf]
 // NOSICI: error: instruction not supported on this GPU
 
+gpr_idx = 1
+s_set_gpr_idx_on s0, gpr_idx
+// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf]
+// NOSICI: error:
+
+gpr_idx_mode = 10
+s_set_gpr_idx_on s0, gpr_idx_mode + 5
+// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf]
+// NOSICI: error:
+
 s_set_gpr_idx_on s0, 0
-// VI: s_set_gpr_idx_on s0, 0 ; encoding: [0x00,0x00,0x11,0xbf]
-// NOSICI: error: instruction not supported on this GPU
+// VI: s_set_gpr_idx_on s0, gpr_idx() ; encoding: [0x00,0x00,0x11,0xbf]
+// NOSICI: error:
+
+s_set_gpr_idx_on s0, gpr_idx()
+// VI: s_set_gpr_idx_on s0, gpr_idx() ; encoding: [0x00,0x00,0x11,0xbf]
+// NOSICI: error:
 
 s_set_gpr_idx_on s0, 1
-// VI: s_set_gpr_idx_on s0, src0 ; encoding: [0x00,0x01,0x11,0xbf]
-// NOSICI: error: instruction not supported on this GPU
+// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf]
+// NOSICI: error:
+
+s_set_gpr_idx_on s0, gpr_idx(SRC0)
+// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf]
+// NOSICI: error:
 
 s_set_gpr_idx_on s0, 3
-// VI: s_set_gpr_idx_on s0, src0 src1 ; encoding: [0x00,0x03,0x11,0xbf]
-// NOSICI: error: instruction not supported on this GPU
+// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1) ; encoding: [0x00,0x03,0x11,0xbf]
+// NOSICI: error:
+
+s_set_gpr_idx_on s0, gpr_idx(SRC1,SRC0)
+// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1) ; encoding: [0x00,0x03,0x11,0xbf]
+// NOSICI: error:
 
 s_set_gpr_idx_on s0, 15
-// VI: s_set_gpr_idx_on s0, dst src0 src1 src2 ; encoding: [0x00,0x0f,0x11,0xbf]
-// NOSICI: error: instruction not supported on this GPU
+// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf]
+// NOSICI: error:
+
+s_set_gpr_idx_on s0, gpr_idx(SRC0,DST,SRC2,SRC1)
+// VI: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf]
+// NOSICI: error:
diff --git a/llvm/test/MC/AMDGPU/sopp.s b/llvm/test/MC/AMDGPU/sopp.s
index f68b8227d76..deab19471ea 100644
--- a/llvm/test/MC/AMDGPU/sopp.s
+++ b/llvm/test/MC/AMDGPU/sopp.s
@@ -232,15 +232,23 @@ s_ttracedata
 
 s_set_gpr_idx_off
 // VI: 	s_set_gpr_idx_off ; encoding: [0x00,0x00,0x9c,0xbf]
-// NOSICI: error: instruction not supported on this GPU
+// NOSICI: error:
 
 s_set_gpr_idx_mode 0
-// VI: s_set_gpr_idx_mode 0 ; encoding: [0x00,0x00,0x9d,0xbf]
-// NOSICI: error: instruction not supported on this GPU
+// VI: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf]
+// NOSICI: error:
+
+s_set_gpr_idx_mode gpr_idx()
+// VI: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf]
+// NOSICI: error:
 
 s_set_gpr_idx_mode 15
-// VI: s_set_gpr_idx_mode dst src0 src1 src2 ; encoding: [0x0f,0x00,0x9d,0xbf]
-// NOSICI: error: instruction not supported on this GPU
+// VI: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
+// NOSICI: error:
+
+s_set_gpr_idx_mode gpr_idx(SRC2,SRC1,SRC0,DST)
+// VI: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
+// NOSICI: error:
 
 s_endpgm_saved
 // VI: s_endpgm_saved ; encoding: [0x00,0x00,0x9b,0xbf]
diff --git a/llvm/test/MC/Disassembler/AMDGPU/sopc_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/sopc_vi.txt
index 2c2dc07efd6..4bf2aefaf0c 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/sopc_vi.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/sopc_vi.txt
@@ -53,3 +53,15 @@
 
 # GCN: s_bitcmp0_b32 0xafaaffff, 0xafaaffff ; encoding: [0xff,0xff,0x0c,0xbf,0xff,0xff,0xaa,0xaf]
 0xff 0xff 0x0c 0xbf 0xff 0xff 0xaa 0xaf
+
+# GCN: s_set_gpr_idx_on s0, gpr_idx(SRC0) ; encoding: [0x00,0x01,0x11,0xbf]
+0x00,0x01,0x11,0xbf
+
+# GCN: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf]
+0x00,0x0f,0x11,0xbf
+
+# GCN: s_set_gpr_idx_on s0, gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x00,0x0f,0x11,0xbf]
+0x00,0x0f,0x11,0xbf
+
+# GCN: s_set_gpr_idx_on s0, 0xff ; encoding: [0x00,0xff,0x11,0xbf]
+0x00,0xff,0x11,0xbf
diff --git a/llvm/test/MC/Disassembler/AMDGPU/sopp_vi.txt b/llvm/test/MC/Disassembler/AMDGPU/sopp_vi.txt
index fb8b0e47c6b..9993fa91bb4 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/sopp_vi.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/sopp_vi.txt
@@ -125,3 +125,9 @@
 
 # GCN: s_ttracedata ; encoding: [0x00,0x00,0x96,0xbf]
 0x00 0x00 0x96 0xbf
+
+# GCN: s_set_gpr_idx_mode gpr_idx() ; encoding: [0x00,0x00,0x9d,0xbf]
+0x00,0x00,0x9d,0xbf
+
+# GCN: s_set_gpr_idx_mode gpr_idx(SRC0,SRC1,SRC2,DST) ; encoding: [0x0f,0x00,0x9d,0xbf]
+0x0f,0x00,0x9d,0xbf