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-rw-r--r--llvm/test/MC/ARM64/elf-relocs.s6
-rw-r--r--llvm/test/MC/ARM64/memory.s32
-rw-r--r--llvm/test/MC/ARM64/simd-ldst.s8
-rw-r--r--llvm/test/MC/ARM64/tls-relocs.s4
-rw-r--r--llvm/test/MC/Disassembler/ARM64/memory.txt8
5 files changed, 29 insertions, 29 deletions
diff --git a/llvm/test/MC/ARM64/elf-relocs.s b/llvm/test/MC/ARM64/elf-relocs.s
index 31446ff9692..b2de225c9ce 100644
--- a/llvm/test/MC/ARM64/elf-relocs.s
+++ b/llvm/test/MC/ARM64/elf-relocs.s
@@ -72,7 +72,7 @@
// CHECK-OBJ: 50 R_AARCH64_ADR_GOT_PAGE sym
adrp x29, :gottprel:sym
-// CHECK: adrp fp, :gottprel:sym
+// CHECK: adrp x29, :gottprel:sym
// CHECK-OBJ: 54 R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21 sym
adrp x2, :tlsdesc:sym
@@ -105,7 +105,7 @@ trickQuestion:
ldrsb w23, [x19, #:dtprel_lo12:sym]
ldrsb x17, [x13, #:dtprel_lo12_nc:sym]
ldr b11, [x7, #:dtprel_lo12:sym]
-// CHECK: ldrb w23, [fp, :dtprel_lo12_nc:sym]
+// CHECK: ldrb w23, [x29, :dtprel_lo12_nc:sym]
// CHECK: ldrsb w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsb x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr b11, [x7, :dtprel_lo12:sym]
@@ -144,7 +144,7 @@ trickQuestion:
ldrsh w23, [x19, #:dtprel_lo12:sym]
ldrsh x17, [x13, #:dtprel_lo12_nc:sym]
ldr h11, [x7, #:dtprel_lo12:sym]
-// CHECK: ldrh w23, [fp, :dtprel_lo12_nc:sym]
+// CHECK: ldrh w23, [x29, :dtprel_lo12_nc:sym]
// CHECK: ldrsh w23, [x19, :dtprel_lo12:sym]
// CHECK: ldrsh x17, [x13, :dtprel_lo12_nc:sym]
// CHECK: ldr h11, [x7, :dtprel_lo12:sym]
diff --git a/llvm/test/MC/ARM64/memory.s b/llvm/test/MC/ARM64/memory.s
index 0e8f1d5008e..ce6c62c58b0 100644
--- a/llvm/test/MC/ARM64/memory.s
+++ b/llvm/test/MC/ARM64/memory.s
@@ -208,7 +208,7 @@ foo:
; Pre-indexed loads and stores
;-----------------------------------------------------------------------------
- ldr fp, [x7, #8]!
+ ldr x29, [x7, #8]!
ldr lr, [x7, #8]!
ldr b5, [x0, #1]!
ldr h6, [x0, #2]!
@@ -217,14 +217,14 @@ foo:
ldr q9, [x0, #16]!
str lr, [x7, #-8]!
- str fp, [x7, #-8]!
+ str x29, [x7, #-8]!
str b5, [x0, #-1]!
str h6, [x0, #-2]!
str s7, [x0, #-4]!
str d8, [x0, #-8]!
str q9, [x0, #-16]!
-; CHECK: ldr fp, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8]
+; CHECK: ldr x29, [x7, #8]! ; encoding: [0xfd,0x8c,0x40,0xf8]
; CHECK: ldr lr, [x7, #8]! ; encoding: [0xfe,0x8c,0x40,0xf8]
; CHECK: ldr b5, [x0, #1]! ; encoding: [0x05,0x1c,0x40,0x3c]
; CHECK: ldr h6, [x0, #2]! ; encoding: [0x06,0x2c,0x40,0x7c]
@@ -233,7 +233,7 @@ foo:
; CHECK: ldr q9, [x0, #16]! ; encoding: [0x09,0x0c,0xc1,0x3c]
; CHECK: str lr, [x7, #-8]! ; encoding: [0xfe,0x8c,0x1f,0xf8]
-; CHECK: str fp, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8]
+; CHECK: str x29, [x7, #-8]! ; encoding: [0xfd,0x8c,0x1f,0xf8]
; CHECK: str b5, [x0, #-1]! ; encoding: [0x05,0xfc,0x1f,0x3c]
; CHECK: str h6, [x0, #-2]! ; encoding: [0x06,0xec,0x1f,0x7c]
; CHECK: str s7, [x0, #-4]! ; encoding: [0x07,0xcc,0x1f,0xbc]
@@ -244,14 +244,14 @@ foo:
; post-indexed loads and stores
;-----------------------------------------------------------------------------
str lr, [x7], #-8
- str fp, [x7], #-8
+ str x29, [x7], #-8
str b5, [x0], #-1
str h6, [x0], #-2
str s7, [x0], #-4
str d8, [x0], #-8
str q9, [x0], #-16
- ldr fp, [x7], #8
+ ldr x29, [x7], #8
ldr lr, [x7], #8
ldr b5, [x0], #1
ldr h6, [x0], #2
@@ -260,14 +260,14 @@ foo:
ldr q9, [x0], #16
; CHECK: str lr, [x7], #-8 ; encoding: [0xfe,0x84,0x1f,0xf8]
-; CHECK: str fp, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8]
+; CHECK: str x29, [x7], #-8 ; encoding: [0xfd,0x84,0x1f,0xf8]
; CHECK: str b5, [x0], #-1 ; encoding: [0x05,0xf4,0x1f,0x3c]
; CHECK: str h6, [x0], #-2 ; encoding: [0x06,0xe4,0x1f,0x7c]
; CHECK: str s7, [x0], #-4 ; encoding: [0x07,0xc4,0x1f,0xbc]
; CHECK: str d8, [x0], #-8 ; encoding: [0x08,0x84,0x1f,0xfc]
; CHECK: str q9, [x0], #-16 ; encoding: [0x09,0x04,0x9f,0x3c]
-; CHECK: ldr fp, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8]
+; CHECK: ldr x29, [x7], #8 ; encoding: [0xfd,0x84,0x40,0xf8]
; CHECK: ldr lr, [x7], #8 ; encoding: [0xfe,0x84,0x40,0xf8]
; CHECK: ldr b5, [x0], #1 ; encoding: [0x05,0x14,0x40,0x3c]
; CHECK: ldr h6, [x0], #2 ; encoding: [0x06,0x24,0x40,0x7c]
@@ -545,8 +545,8 @@ foo:
; unambiguous, i.e. negative or unaligned."
;-----------------------------------------------------------------------------
- ldr x11, [fp, #-8]
- ldr x11, [fp, #7]
+ ldr x11, [x29, #-8]
+ ldr x11, [x29, #7]
ldr w0, [x0, #2]
ldr w0, [x0, #-256]
ldr b2, [x1, #-2]
@@ -559,8 +559,8 @@ foo:
ldr q5, [x8, #8]
ldr q5, [x9, #-16]
-; CHECK: ldur x11, [fp, #-8] ; encoding: [0xab,0x83,0x5f,0xf8]
-; CHECK: ldur x11, [fp, #7] ; encoding: [0xab,0x73,0x40,0xf8]
+; CHECK: ldur x11, [x29, #-8] ; encoding: [0xab,0x83,0x5f,0xf8]
+; CHECK: ldur x11, [x29, #7] ; encoding: [0xab,0x73,0x40,0xf8]
; CHECK: ldur w0, [x0, #2] ; encoding: [0x00,0x20,0x40,0xb8]
; CHECK: ldur w0, [x0, #-256] ; encoding: [0x00,0x00,0x50,0xb8]
; CHECK: ldur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x5f,0x3c]
@@ -573,8 +573,8 @@ foo:
; CHECK: ldur q5, [x8, #8] ; encoding: [0x05,0x81,0xc0,0x3c]
; CHECK: ldur q5, [x9, #-16] ; encoding: [0x25,0x01,0xdf,0x3c]
- str x11, [fp, #-8]
- str x11, [fp, #7]
+ str x11, [x29, #-8]
+ str x11, [x29, #7]
str w0, [x0, #2]
str w0, [x0, #-256]
str b2, [x1, #-2]
@@ -587,8 +587,8 @@ foo:
str q5, [x8, #8]
str q5, [x9, #-16]
-; CHECK: stur x11, [fp, #-8] ; encoding: [0xab,0x83,0x1f,0xf8]
-; CHECK: stur x11, [fp, #7] ; encoding: [0xab,0x73,0x00,0xf8]
+; CHECK: stur x11, [x29, #-8] ; encoding: [0xab,0x83,0x1f,0xf8]
+; CHECK: stur x11, [x29, #7] ; encoding: [0xab,0x73,0x00,0xf8]
; CHECK: stur w0, [x0, #2] ; encoding: [0x00,0x20,0x00,0xb8]
; CHECK: stur w0, [x0, #-256] ; encoding: [0x00,0x00,0x10,0xb8]
; CHECK: stur b2, [x1, #-2] ; encoding: [0x22,0xe0,0x1f,0x3c]
diff --git a/llvm/test/MC/ARM64/simd-ldst.s b/llvm/test/MC/ARM64/simd-ldst.s
index a754c7231e2..75d038307e6 100644
--- a/llvm/test/MC/ARM64/simd-ldst.s
+++ b/llvm/test/MC/ARM64/simd-ldst.s
@@ -263,10 +263,10 @@ ld3st3_multiple:
; CHECK: ld3.8b { v9, v10, v11 }, [x9] ; encoding: [0x29,0x41,0x40,0x0c]
; CHECK: ld3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x40,0x4c]
-; CHECK: ld3.4h { v24, v25, v26 }, [fp] ; encoding: [0xb8,0x47,0x40,0x0c]
+; CHECK: ld3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x40,0x0c]
; CHECK: ld3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x40,0x4c]
; CHECK: ld3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x40,0x0c]
-; CHECK: ld3.4s { v4, v5, v6 }, [fp] ; encoding: [0xa4,0x4b,0x40,0x4c]
+; CHECK: ld3.4s { v4, v5, v6 }, [x29] ; encoding: [0xa4,0x4b,0x40,0x4c]
; CHECK: ld3.2d { v7, v8, v9 }, [x9] ; encoding: [0x27,0x4d,0x40,0x4c]
; CHECK: st3.8b { v4, v5, v6 }, [x19] ; encoding: [0x64,0x42,0x00,0x0c]
@@ -279,10 +279,10 @@ ld3st3_multiple:
; CHECK: st3.8b { v10, v11, v12 }, [x9] ; encoding: [0x2a,0x41,0x00,0x0c]
; CHECK: st3.16b { v14, v15, v16 }, [x19] ; encoding: [0x6e,0x42,0x00,0x4c]
-; CHECK: st3.4h { v24, v25, v26 }, [fp] ; encoding: [0xb8,0x47,0x00,0x0c]
+; CHECK: st3.4h { v24, v25, v26 }, [x29] ; encoding: [0xb8,0x47,0x00,0x0c]
; CHECK: st3.8h { v30, v31, v0 }, [x9] ; encoding: [0x3e,0x45,0x00,0x4c]
; CHECK: st3.2s { v2, v3, v4 }, [x19] ; encoding: [0x62,0x4a,0x00,0x0c]
-; CHECK: st3.4s { v7, v8, v9 }, [fp] ; encoding: [0xa7,0x4b,0x00,0x4c]
+; CHECK: st3.4s { v7, v8, v9 }, [x29] ; encoding: [0xa7,0x4b,0x00,0x4c]
; CHECK: st3.2d { v4, v5, v6 }, [x9] ; encoding: [0x24,0x4d,0x00,0x4c]
ld4st4_multiple:
diff --git a/llvm/test/MC/ARM64/tls-relocs.s b/llvm/test/MC/ARM64/tls-relocs.s
index 7e8b7545b40..49270146f11 100644
--- a/llvm/test/MC/ARM64/tls-relocs.s
+++ b/llvm/test/MC/ARM64/tls-relocs.s
@@ -121,7 +121,7 @@
ldrsb x29, [x28, #:tprel_lo12_nc:var]
// CHECK: ldrb w29, [lr, :tprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK: ldrsb fp, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK: ldrsb x29, [x28, :tprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :tprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLE_LDST8_TPREL_LO12 [[VARSYM]]
@@ -245,7 +245,7 @@
ldrsb x29, [x28, #:dtprel_lo12_nc:var]
// CHECK: ldrb w29, [lr, :dtprel_lo12:var] // encoding: [0xdd,0bAAAAAA11,0b01AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12:var, kind: fixup_arm64_ldst_imm12_scale1
-// CHECK: ldrsb fp, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
+// CHECK: ldrsb x29, [x28, :dtprel_lo12_nc:var] // encoding: [0x9d,0bAAAAAA11,0b10AAAAAA,0x39]
// CHECK-NEXT: // fixup A - offset: 0, value: :dtprel_lo12_nc:var, kind: fixup_arm64_ldst_imm12_scale1
// CHECK-ELF-NEXT: {{0x[0-9A-F]+}} R_AARCH64_TLSLD_LDST8_DTPREL_LO12 [[VARSYM]]
diff --git a/llvm/test/MC/Disassembler/ARM64/memory.txt b/llvm/test/MC/Disassembler/ARM64/memory.txt
index d0371cfc69f..5be3673f4e5 100644
--- a/llvm/test/MC/Disassembler/ARM64/memory.txt
+++ b/llvm/test/MC/Disassembler/ARM64/memory.txt
@@ -210,7 +210,7 @@
0x08 0x8c 0x40 0xfc
0x09 0x0c 0xc1 0x3c
-# CHECK: ldr fp, [x7, #8]!
+# CHECK: ldr x29, [x7, #8]!
# CHECK: ldr lr, [x7, #8]!
# CHECK: ldr b5, [x0, #1]!
# CHECK: ldr h6, [x0, #2]!
@@ -227,7 +227,7 @@
0x09 0x0c 0x9f 0x3c
# CHECK: str lr, [x7, #-8]!
-# CHECK: str fp, [x7, #-8]!
+# CHECK: str x29, [x7, #-8]!
# CHECK: str b5, [x0, #-1]!
# CHECK: str h6, [x0, #-2]!
# CHECK: str s7, [x0, #-4]!
@@ -247,7 +247,7 @@
0x09 0x04 0x9f 0x3c
# CHECK: str lr, [x7], #-8
-# CHECK: str fp, [x7], #-8
+# CHECK: str x29, [x7], #-8
# CHECK: str b5, [x0], #-1
# CHECK: str h6, [x0], #-2
# CHECK: str s7, [x0], #-4
@@ -262,7 +262,7 @@
0x08 0x84 0x40 0xfc
0x09 0x04 0xc1 0x3c
-# CHECK: ldr fp, [x7], #8
+# CHECK: ldr x29, [x7], #8
# CHECK: ldr lr, [x7], #8
# CHECK: ldr b5, [x0], #1
# CHECK: ldr h6, [x0], #2
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