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-rw-r--r--llvm/test/MC/ARM/basic-arm-instructions.s36
-rw-r--r--llvm/test/MC/Disassembler/ARM/arm-tests.txt6
-rw-r--r--llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt54
3 files changed, 73 insertions, 23 deletions
diff --git a/llvm/test/MC/ARM/basic-arm-instructions.s b/llvm/test/MC/ARM/basic-arm-instructions.s
index 66408820246..55d9f026195 100644
--- a/llvm/test/MC/ARM/basic-arm-instructions.s
+++ b/llvm/test/MC/ARM/basic-arm-instructions.s
@@ -928,15 +928,15 @@ Lforward:
@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
@ CHECK: msr APSR_nzcvqg, #5 @ encoding: [0x05,0xf0,0x2c,0xe3]
-@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
-@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x20,0xe3]
-@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x20,0xe3]
-@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
-@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
-@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2c,0xe3]
-@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
-@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2c,0xe3]
-@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2c,0xe3]
+@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3]
+@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x21,0xe3]
+@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x22,0xe3]
+@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3]
+@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3]
+@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2e,0xe3]
+@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3]
+@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3]
+@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3]
msr apsr, r0
msr apsr_g, r0
@@ -958,15 +958,15 @@ Lforward:
@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
@ CHECK: msr APSR_nzcvqg, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
-@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
-@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x20,0xe1]
-@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x20,0xe1]
-@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
-@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
-@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
-@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x28,0xe1]
-@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
-@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2c,0xe1]
+@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1]
+@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1]
+@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1]
+@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1]
+@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1]
+@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1]
+@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1]
@------------------------------------------------------------------------------
@ MUL
diff --git a/llvm/test/MC/Disassembler/ARM/arm-tests.txt b/llvm/test/MC/Disassembler/ARM/arm-tests.txt
index 36627a34881..69a094dd681 100644
--- a/llvm/test/MC/Disassembler/ARM/arm-tests.txt
+++ b/llvm/test/MC/Disassembler/ARM/arm-tests.txt
@@ -161,6 +161,12 @@
# CHECK: cpsie if, #10
0xca 0x00 0x0a 0xf1
+# CHECK: msr CPSR_fc, r0
+0x00 0xf0 0x29 0xe1
+
+# CHECK: msrmi CPSR_c, #4043309056
+0xf1 0xf4 0x21 0x43
+
# CHECK: rsbs r6, r7, r8
0x08 0x60 0x77 0xe0
diff --git a/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt b/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt
index 06aa8f756da..fc7eda537ab 100644
--- a/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt
+++ b/llvm/test/MC/Disassembler/ARM/basic-arm-instructions.txt
@@ -744,21 +744,65 @@
# MSR
#------------------------------------------------------------------------------
+# CHECK: msr CPSR_fc, #5
+# CHECK: msr APSR_g, #5
+# CHECK: msr APSR_nzcvq, #5
+# CHECK: msr APSR_nzcvq, #5
+# CHECK: msr APSR_nzcvqg, #5
+# CHECK: msr CPSR_fc, #5
# CHECK: msr CPSR_c, #5
# CHECK: msr CPSR_x, #5
-# CHECK: msr CPSR_xc, #5
-
+# CHECK: msr CPSR_fc, #5
+# CHECK: msr CPSR_fc, #5
+# CHECK: msr CPSR_fsx, #5
+# CHECK: msr SPSR_fc, #5
+# CHECK: msr SPSR_fsxc, #5
+# CHECK: msr CPSR_fsxc, #5
+
+0x05 0xf0 0x29 0xe3
0x05 0xf0 0x24 0xe3
0x05 0xf0 0x28 0xe3
+0x05 0xf0 0x28 0xe3
0x05 0xf0 0x2c 0xe3
-
+0x05 0xf0 0x29 0xe3
+0x05 0xf0 0x21 0xe3
+0x05 0xf0 0x22 0xe3
+0x05 0xf0 0x29 0xe3
+0x05 0xf0 0x29 0xe3
+0x05 0xf0 0x2e 0xe3
+0x05 0xf0 0x69 0xe3
+0x05 0xf0 0x6f 0xe3
+0x05 0xf0 0x2f 0xe3
+
+# CHECK: msr CPSR_fc, r0
+# CHECK: msr APSR_g, r0
+# CHECK: msr APSR_nzcvq, r0
+# CHECK: msr APSR_nzcvq, r0
+# CHECK: msr APSR_nzcvqg, r0
+# CHECK: msr CPSR_fc, r0
# CHECK: msr CPSR_c, r0
# CHECK: msr CPSR_x, r0
-# CHECK: msr CPSR_xc, r0
-
+# CHECK: msr CPSR_fc, r0
+# CHECK: msr CPSR_fc, r0
+# CHECK: msr CPSR_fsx, r0
+# CHECK: msr SPSR_fc, r0
+# CHECK: msr SPSR_fsxc, r0
+# CHECK: msr CPSR_fsxc, r0
+
+0x00 0xf0 0x29 0xe1
0x00 0xf0 0x24 0xe1
0x00 0xf0 0x28 0xe1
+0x00 0xf0 0x28 0xe1
0x00 0xf0 0x2c 0xe1
+0x00 0xf0 0x29 0xe1
+0x00 0xf0 0x21 0xe1
+0x00 0xf0 0x22 0xe1
+0x00 0xf0 0x29 0xe1
+0x00 0xf0 0x29 0xe1
+0x00 0xf0 0x2e 0xe1
+0x00 0xf0 0x69 0xe1
+0x00 0xf0 0x6f 0xe1
+0x00 0xf0 0x2f 0xe1
#------------------------------------------------------------------------------
# MUL
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